irradiation system
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Preset number of ions irradiation system Acknoledgement
ACKNOWLEDGEMENT
This work has been supported from contract HPRN-CT-2000-00047,
European Network on Ion Track Technology and from contract CNCSIS
586/2005 Sistem automat de iradiere a filmelor polimerice su br prestabilit
de ioni.
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Preset number of ions irradiation system Contents
Contents
Preface1. General description 1
2. Operating 2
1.1. Adjusting the preamplifier gain 41.2. Irradiation process 6
3. Ion detector 7
4. Preamplifier 8
5. Pulse shaper 9
6. Negative pulse suppressor 22
7. Analog to digital converter 11
8. Digital processor FPGA 12
9.1. 8 bit Computer interface 139.2. Clock divider 159.3. Instruction decoder 169.4. Registers 209.5. Irradiation machine 239.6. Peak detector 259.7. FIFO memory and interface 289.8. Acquire state machine 309.9. Printer state machine
31
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9.10.Encoder reader 319.11.PWM generators 339.12.Motor control block 349.13.Ion flux measurement 369.14.Driving flipping magnets 389.15.Digital circuit schematic 39
9. Communication interface 41
9.16.Data acquisition board 429.17.Communication protocol 43
10. Power circuits 43
10.1.Motors drivers 4410.2.Printer head drivers 4510.3.Driving TV cameras 4610.4.Interfacing the beam shutter 47
11. LabView program 48
11.1.Main control program 4811.2.Beam diagnostic VI 5011.3.Acquire VI 5011.4.Irradiation VI 52
12. Mechanics 54
12.1.Beam diagnostics 55
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12.2.Tape roller 56Appendix 1 66
Appendix 2 79
Appendix 3 84
Appendix 4 102
Appendix 5 119
Appendix 6 120
Bibliography
Acknowledgement
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PRESET NUMBER OF IONS IRRADIATION SYSTEM
1. General description
The system is aimed to irradiate long polymer films (polycarbonate,polyimmide, PET, etc), 35mm wide, with or without perforations, withpreset number of ions coming from an ion accelerator. Other goals tobe achieved by the present system are:
to mark on the tape good and bad frames, to be mobile (light weight and small dimensions), to be easy to install and to operate, to perform ion counting and energy analysis, to enable irradiation under different angles,
to be remote via Ethernet network.The system has three parts: a beam diagnostic system, a taperoller, and an electronic system.
The beam diagnostic system is aimed for trimming the beam
before the irradiation is started, down to 10100 ions per second, inorder to reduce the probability of double pulses at the detector level.This part works in vacuum. It has three main parts: the Faraday cupfor measuring the beam current, the fluorescent screen to see thebeam shape and roughly estimating the flux, and the TV camera toobserve the fluorescent screen. The fluorescent screen and theFaraday cup can be flipped in or out using to bi-stable magnets. Onthe flange of the beam diagnostic system there are 4 double BNC
connectors: Fluorescent screen magnet, Faraday cup magnet, TVcamera and Faraday cup repeller. First three are signals coming fromthe digital part of the electronic system and the repeller should beconnected to a picoamperemeter.
The tape roller consists of three DC motors and a printer headmounted on a metal plate. Two motors are attached on the two taperoles and the third one is driving a pressure rubber role. The motorsattached on the roles serve as breaks during irradiation or as tractionmotors for FF or REW the tape. The third motor has an angularencoder for measuring the tape displacement (the distance betweenframes).
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The hardware can be divided in three parts: the analog signalprocessing part (silicon detector, amplifier and shaping filters), thedigital part (digital signal processor, microinstruction executor andFIFO memory) and the power electronics (motors and magnetsdrivers).
The electronic system is controlled by a LabView program, runningon a portable computer, via an 8 bits data bus (digital I/O of DAQ NI DAQ6062). See Figure 1.
2. Operating
The irradiation system is a complex machine which has to fulfill many
tasks. These should be scheduled in a proper order: beam trimming,gain and sampling frequency adjustment and irradiation itself, inorder to obtain the expected results.
2.1. Beam trimming
The beam trimming is achieved using the beam diagnostic system. Itcan be controlled by three bits in the control register (address 1h) inthe digital processor: D5 TV camera switch, D6 fluorescent screenflipping magnet, D7 Faraday cup flipping magnet. Also the ion fluxcan be measured with frequency-meter available in the digitalprocessor. The result is available in register located at the address2h on 8 bits. An overflow is signaled by the 8 th bit in the status
Pressure
role
Preamplifier
Shaping
FilterADC
Memory
FPGA FIFO
Power
circuits
LAN
FF Motor
REW Motor
Printing
head
Digital
processor
Driving Motor
Angular
encoder
Communication
interface
Power
supply
Ion DetectorConfiguration
memory
Video
camera
Fluorescent
screenFaraday
cup
Beam
line
Beam
diagnostic
Tape roller
Electronics
EPF10k10LC84
EPC2
DAQ card
DAQ6062
pA
Figure 1 Detailed block diagram of the irradiation system
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register (address 0h). This process can be controlled with the VIBeamDiagControl (Figure 53).
There are three possibilities to adjust the beam, or evencombination of them. The first one (using the Faraday cup) starts
with flipping-in the Faraday cup (I, II, II, IV) and measuring thecurrent (V, VI). See Figure 3 a. The beam must be defocused, by theoperator, until the current is under a certain limit (between 1pA and10pA for Xe 27+ beam). Also, this can be completed with thefluorescent screen together with the TV camera (for experiencedoperator). First the fluorescent screen must be flipped in (I, II, II, IV),and then, using Netmeeting, to look to the image captured with theTV camera. The operator must decrease the beam, until a pale lightspot is visible on the screen. See Figure 3 b. Another alternative,more precise, is offered by the frequency-meter. It can be used fromthe beginning or after trimming with the previous one, for fineadjustment. First the threshold for the trigger must be set-up and the
beam line should be switched on (I). The signal coming from thedetector (II), amplified (III), shaped (IV), digitized (V), is triggered by adigital comparator and the pulses are counted along one second,every two seconds, by the frequency-meter (VI). The beam flux mustbe reduced until the desired number of ions per second is measured.See Figure 3 c. The number displayed will be not constant but thedispersion should not be more than 10 to 20 %. This is the mostprecise adjustment.
Pressure
role
Preamplifier
Shaping
Filter ADC
Memory
FPGA FIFO
Power
circuits
LAN
FF Motor
REW Motor
Printing
head
Digital
processor
Driving Motor
Angular
encoder
Communication
interface
Power
supply
Ion DetectorConfiguration
memory
Video
camera
Fluorescent
screenFaraday
cup
Beam
line
Beam
diagnostic
Tape roller
Electronics
EPF10k10LC84
EPC2
DAQ card
DAQ6062
pAI
II
III
IV
V
VI
a) Trimming the beam with the Faraday cup
BeamDiagControl.vi
Figure 2.a Trimming the ion beam
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2.2. Adjusting the preamplifier gain
In order to achieve this, a special block (Acquire) has been included
Pressure
role
Preamplifier
Shaping
FilterADC
Memory
FPGA FIFO
Power
circuits
LAN
FF Motor
REW Motor
Printing
head
Digital
processor
Driving Motor
Angular
encoder
Communication
interface
Power
supply
Ion DetectorConfiguration
memory
Video
camera
Fluorescent
screen
Faraday
cup
Beam
line
Beam
diagnostic
Tape roller
Electronics
EPF10k10LC84
EPC2
DAQ card
DAQ6062
pAI
II
III
V
b) Trimming the beam with the fluorescent screen
IV
BeamDiagControl.vi
NetMeeting
Pressure
role
Preamplifier
Shaping
FilterADC
Memory
FPGA
FIFO
Power
circuits
LA
FF Motor
REW Motor
Printing
head
Digital
processorDriving Motor
Angular
encoder
Communication
interface
Power
supply
Ion DetectorConfiguration
memory
Video
camera
Fluorescent
screenFaraday
cup
Beam
line
Beam
diagnostic
Tape roller
Electronics
EPF10k10LC84
EPC2
DAQ card
DAQ6062
pA
I
II
III
VI
b) Trimming the beam measuring the ion flux
IV
Frequency
meterV
BeamDiagControl.viVII
Figure 3.b Trimming the ion beam
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in the digital processor. It takes 256 samples of the signal, startingwhen the signal exceeds the threshold value, stored in the Thresholdregister, and stores them into the FIFO memory. Afterwards they canbe downloaded into computer byte by byte. For accomplishing this,
Acquire.vi has been developed. The ion beam is switched on (I) andthe gain of the preamplifier set-up (II), the signal generated by thedetector (III) is amplified (IV), shaped (V), digitized (VI), and then thesamples are stored into FIFO (VII). For collecting the bytes fromFIFO (VIII), every byte should be transferred into the digitalprocessor (readmemmachine) and then read via the communicationinterface from register MEM (IX). The data transferred into thecomputer are displayed on a graph (Acquire.vi) and saved on thedisk into a file starting with Acq followed by the date and the hour,with the extension txt. The operation should be repeated few timesto ensure that there are no limitations due to high gain, or, if thereare, the gain should be reduced until the pulse look like in Figure 5.
The program can save also a note at the beginning of the file. Theprocess is described by the following picture (Figure 4).
NOTE: the gain adjustment should be performed with the same tapethat will be irradiated in front of the detector in order to get properresults.
Pressure
role
Preamplifier
Shaping
FilterADC
Memory
FPGA
FIFO
Power
circuits
LAN
FF Motor
REW Motor
Printing
head
Digital
processorDriving Motor
Angular
encoder
Communication
interface
Power
supply
Ion DetectorConfiguration
memory
Video
camera
Fluorescent
screen
Faraday
cup
Beam
line
Beam
diagnostic
Tape roller
Electronics
EPF10k10LC84
EPC2
DAQ card
DAQ6062
pA
I
II
III
VII
IV
AcquireV
Acquire.vi
Readmem
machine
VI
VIII
IX
Figure 4 Acquiring pulses for gain adjustment
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2.3. Irradiation process
After the calibration is done, one can start the irradiation process. Forthis Main.vi is available. The gain value, determined in the previous
step, must be used. According to the pulse shape, and noiserecorded, the thresholds for good pulse must be chosen too. Thevirtual instrument is performing the irradiation automatically, savingthe peaks recorded in the log file (Irr + date and hour.txt) togetherwith some explaining note. The instrument is described in chapter 0.The irradiation process is thought as a sequential one, different tasksto be accomplished successively: switching-on the ion beam (I, II),waiting for receiving the desired number of ions (III, IV, V, VI, VII),reading the number of peaks and the peaks values (IX, X), deciding if
Figure 5 Pulse
XI, XIV
XVI
Pressure
role
Preamplifier
Shaping
FilterADC
Memory
FPGA
FIFO
Power
circuits
LAN
FF Motor
REW Motor
Printing
head
Digital
processorDriving Motor
Angular
encoder
Communication
interface
Power
supply
Ion DetectorConfiguration
memory
Video
camera
Fluorescent
screen
Faraday
cup
Beam
line
Beam
diagnostic
Tape roller
Electronics
EPF10k10LC84
EPC2
DAQ card
DAQ6062
pA
I
II
III
VII
IVPeak det
V
Acquire.vi
Readmem
machine
VI
VIII
X
Beam
Control
IXXIII
XII
XV
Figure 6 Irradiation process
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the irradiation is good, saving data to file, printing on tape (XI, XII,XIII), advancing the tape for next frame (XIV, XV, XVI). After thedesired number of samples is recorded, the beam is switched offautomatically (VII). This process is presented in Figure 6.
3. Ion detector
The ion detector is a PIN diode (S1223). It is dedicated foroptical measurements. In order to be used for ion detection, thequartz window has been removed.
Warning: removing the window will expose the diode to air.There is a very thin wire connecting the anode of the diode to theexternal pin. When manipulating, try not to touch the active area orthe gold bonding wire.
At zero voltage the maximum capacitance of the diode isabout 100pF (Figure8), which will give a slow response (long tail ofthe pulse) and a low sensitivity. In order to reach the maximumperformance, the diode should be reverse polarized (up to 20V)through 1Mohm resistor. The reverse voltage will reduce the straycapacitance: the result is increasing the sensitivity (U=Q/C and forconstant Q and smaller C the peak will be higher) and reducing thepulse tail (t=RinCdet faster discharge). The schematic is presented
in Figure 7. The DC voltage, at the detector level, must be very
100nF
100nF
100K
100K1M
1M
10F
100pF
10F
100pF
-5V
+5V
Det-
Det+
Figure 7 Biasing the PINdiode
Figure 8 PIN diode capacitance versusthe reverse voltage
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smooth and without noise, otherwise these will add to the usefulsignal.
4. Preamplifier
The preamplifier consists of two stages. The first one is aninstrumentation amplifier (Figure 9), capacitively coupled with thedetector. This is programmable gain stage with the gains 2, 4, 8, 16.Its role is to reject the common mode signals and to provide the fineadjustment of the overall gain. OP27 was used, because it is fast,has low noise and low offset. The gain can be calculated with thefollowing equation:
=
==
++=
k
i
k
k
i
k
i
k
kR
RRR
G
3
3
3
0
4
2
22
21
(1)Choosing R4=10k we obtain for the other resistors the
following values: R0 = 5k, R1=2.5K, R2=1.25K, R3=2.5K. For R0 willbe used 4.7K in series with 300, for R1 and R3 2.2K plus 300 will beused and for R2 1.1K plus 150. The feedback resistors have a 3p
G0G1
R4
R4
R3
20k
20k
20k20k
Op27
Op27
Op27Det-
Det+
Out
1M
1M
15p
15p
15p
1n
1n
R2
R2
R1
R0
R1
R0
+5V-5V
VDDVEE
VSS INH
Xcom
Ycom
X0
X1
X2
X3
Y0
Y1
Y2
Y3
A
B
4052 To
shaper
10k
10k
5k
5k
2k5
2k5
1k25
1k25
2k5
Figure 9 The first stage of the detector preamplifier
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capacitance in parallel for compensating the frequency response andavoiding the oscillation of the amplifier. The 1M resistances on eachinput allow biasing the positive inputs of the opamp.
The second stage is a simple inverter stage, also with
programmable gain in two steps 1 and 16. Its schematic is presentedin Figure 10. The total gain was divided in two stages to keep a highbandwidth for the preamplifier.
5. Pulse shaper
In order to avoid multiple pulses, rising on the previous tail, the
pulse tail must be shortened. This is usually achieved using a pulseshaper. The pulse shaper consists of two cascaded filters: a highpass filter followed by a low pass filter. Both are MFB 2 pole Besselfilters, in inverting configuration. Because the high pass filter willstrongly reduce the amplitude of the pulses, and to distribute thenecessary gain on both stages, the high pass has been used beforethe low pass filter.
The high pass filter is F1 in Figure 11 and the low pass filter isF2 in Figure 11.
16k 16k
OP27Out
15p
1k
15p
47p
G3
+5V-5V
VDDVEE
VSS INH
Xcom
Ycom
X0
X1
X2
X3
Y0
Y1
Y2
Y3
A
B
4052
In
Figure 10 The second stage of the preamplifier
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The high pass filter has the cutting frequency at 50KHz and the gain
of about 1.5. The low pass filter has the cutting frequency at 1MHzand the gain of about 1. After filtering the pulses, length decreases
from about 150s down to 3.5s, the amplitude remaining almostconstant. The measured 3dB bandwidth of the whole shaper is from42KHz to 310KHz with a maximum around 87KHz. The maximummeasured gain using sine wave is about 2.64 and using pulses fromthe fission source (similar to ion pulses) the gain is around 2.
6. Negative pulse suppressor
Because signal shaping with high pass filter produces an undergoing
of the signal under the zero axis after the pulse, and because the A/Dconverter has the input range from 0 to 2.5V a negative pulsesuppressor must be introduced on the signal path. It is shown in
120k
320k
OP27OutF1
15p
22p22p
InF1
InF2
4.7k
12k OP27OutF2
22p
33p
6.8p
4.7k
F1 F2
Figure 11 Shaping filter: F1 - High pass filter, F2 - Low pass filter
In
10k
OP37
Out
BAT85
3p
10k
From
shaper
BAT85
To
ADC
Figure 12 The negative pulse suppressor
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Figure 12.The circuit is a fast half wave precision rectifier. The diodes are fastSchottky diodes in order to have an accurate response. Thecompensation capacitor can miss from the circuit. This circuit will
give negative output voltages for positive inputs. This has to beconsidered in the following stage (see Figure 13).
7. Analog to digital converter
This stage performs the fast conversion (10Ms/s) of the shaped andrectified signal into digital data, in order to be processed by the DSP.The circuit consists of a level shifter, a voltage reference and theADC itself. The entire block is presented in Figure 13.
The level adapter is built around AD817, which is a fastsettling time, low offset operational amplifier, suitable for acting as abuffer in front of a fast ADC. It acts as an inverter with unity gain. Thepotentiometer in the noninverting input allows adjusting the DC levelof the signal at the ADC input for compensating its offset.The AD775 is a CMOS, low power, 8-bit, 20 MSPS sampling analog-to-digital converter (ADC). The AD775 features a built-in samplingfunction and on-chip reference bias resistors to pro-vide a complete8-bit ADC solution. The AD775 utilizes a pipelined/ping pong two-step flash architecture to provide high sampling rates (up to 35 MHz)
VCVC
DGND
DGNDDGND
DGND
VC
VC
ADCClk
AD775
1
2
3
4
5
6
7
8
9
10
11
1213
14
15
16
17
18
19
20
21
22
23
24NOE
DVSS
D0
D1
D2
D3
D4
D5
D6
D7
DVDD
CLKDVDD
AVDD
AVDD
VRTS
VRT
AVDD
VIN
AVSS
AVSS
VRBS
VRB
DVSS
1uF AD780
1234 5
678
NC+VinTEMPGND TRIM
VoutNC
SEL
100nF
100uF
100nF
100nF
51
10pF
100nF100nF
100nF
10
100nF
10
2.5V
-5Vaf
+5Vaf
+
-AD817
3
26
7 1
4 8
1k
1k
510
3pF
From suppressor
To digital processor
+5Vaf-5Vaf 1k
10k 10k100nF
Figure 13 The analog to digital converter
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beam (around 250us)
to allow the acquisition of the signal for gain adjustment to drive the motors of the tape roller to drive the printer head
The processor has been developed in MaxPlusII, at graphic level,all the schematics being available in Appendix 2 and along thischapter.
This is a combination between a simple microprocessor (registersand instruction decoder), a hardware digital signal processor (peakdetector) and some dedicated logic blocks (printing, tape advance,acquire). It was developed to fulfill the specifications above withminimum resources.
8.1. 8 bit Computer interface
The interface with a host computer or other processor is a bi-directional one, the data flow being managed by a Strobe signal
DIO7 Q7
DIO6 Q6
DIO5 Q5
DIO4 Q4
DIO3 Q3
DIO2 Q2
DIO1 Q1
DIO0 Q0
18
D
DFF
CLRN
QPRN
17
D
DFF
CLRN
QPRN
16
D
DFF
CLRN
QPRN
15
D
DFF
CLRN
QPRN
14
D
DFF
CLRN
QPRN
VCC19 nRSTINPUT
13
D
DFF
CLRN
QPRN
VCC10 nInhibitINPUTVCC5 nStrobe
INPUT
8
NOT
9
AND2
12
D
DFF
CLRN
QPRN
VCC7 DIO[7..0]INPUT
11
D
DFF
CLRN
QPRN
3 Q[7..0]OUTPUT
Figure 15 The schematic of the Receiver block
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generated by the host (computer or other processor). The data bus is8 bits wide.
The interface consists of two blocks: the data receiver (Figure15) and the debouncer (Figure 17). The data receiver is an 8 bits
register which temporarily store the received instruction code. Thesignals available are nStrobe, nInhibit and nRst, all of them beingactive on low level as it is suggested by the n in front of theirnames. nStrobe acts as a clock for the D type flip-flops in theregister, on its falling edge, the data present on the 8 data lines
(D07), being stored in, and becoming available at the 8 outputs
(Q07).The nInhibit inhibits the clock when the host is sending the
second byte of the instruction (for instruction with two bytes). Afterthe code of an instruction with two bytes is detected, the InstructionDecoder make active this signal until the second rising edge of thenStrobe. The waveforms in Figure 16 illustrate the functioning of thiscircuit.
The block debounceravoids false strobe edges (debouncer). Ifthe nStrobesignal generated by the host has not monotonous edges,the processor would interpret these, as many strobe edges and thecommunication would be erroneous. This block, sample three timesthe external nStrobesignal, on three consecutives clock cycles andonly if all values are low, it drives the dataout to low or only if all arehigh dataout will be high, otherwise the Dataout is stayingunchanged. This is realized with a shift register, working on theinternal 10MHz clock, and shifting the values of datasampled on thethree clocks. The coincidence of these 3 values is detected with a 2gates NAND 35 and OR 34 which drive a DFF 24. When the circuit isinitialized after the power up, all flip-flops are forced in the high logiclevel. The debouncer is shown in Figure 17 and associated
Figure 16 The associated waveforms for the block Receiver
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waveforms in Figure 18.
8.2. Clock divider
The programmable logic device is supplied with a 20MHz clock froman external oscillator. This clock is divided by two using a D type flip-flop to 10MHz, in order to ensure a duty cycle. Also this is theclock signal for the ADC. This signal is the main clock in the digitalprocessor. In order to obtain all the internal necessary clockfrequencies a 20 bit binary counter is used (clkdivblock in Figure 19).This block is designed using the Mega Wizard Plug-in Manager, but itcan be realized very easy cascading dividers by two, like the first
Figure 17 The debouncer
Figure 18 Waveforms for debouncer
Figure 19 The clock divider
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one. Every CLKDIV[k], k=0,117 will be a square wave with fillingfactor with the frequency:
[ ] kkCLKDIV
MHzf
2
10= (2)
8.3. Instruction decoder
The instructions the device accepts consist of one or twobytes. The one-byte instructions are commands (like Print, Irradiate,Go next frame, etc) and the two bytes instructions are for readingand writing to registers. The first byte contains on four bits theinstruction code and, on other four, the register number, and thesecond byte is the value to be written or read from the register. Thus,the instruction decoder must decode the first byte, and decide if it is acommand or a read-write instruction. First this instruction is fed intotwo binary to decimal decoders (4to16dec in Figure 20). One decode
the higher significant byte of the instruction (D[74]) and establishwhich instruction it is, and the other decodes the lower nibble
(D[30]) and establish which register is addressed. The outputs ofthe second decoder are taken into account only if the instructioncode was 1 or 2 (logic 0 on eq0 or eq1 outputs of the 4to16decnumber 3). In these cases, the nrd and nwr signals are used to
enable the storage of the low nibble (D[30]) in the second decoder(4to16dec number 4) for register addressing. If the instruction codewas different from 1 or 2, than it means that a command has beenreceived, and the second decoder is disabled (logic 0 at all outputs)and no registers are selected.
This block is also generating some other necessary signals forother blocks. Using a Johnson counter (jonson 19) and two AND(AND20 and 21) gates, a short pulse, delayed by seven clock cyclesfrom negative edge of the internal nStrobe signal, is generated (onthe output Q3). It is used as a clock for two flip-flops (DFF14 and 15)for generating the signals for inhibiting the receiver (nInhibitR andnInhibitT) during the second byte receiving or transmitting andisolating the instruction decoder from the data lines. Also, the outputQ2 of the Johnson counter (see Appendix 2) delivers a short pulse (1clock length), for storing the decoded instruction in the latches(latch15b 1 and 2). The inhibition state finishes on the first positiveclock edge after the second nStrobepositive edge. This means that
the stopstatesignal becomes for short time active and brings the two
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flip-flops to logic 1. This happens only when nrdor nwrare active,that is to say when it is a write or read instruction. Also two delayedreplicas of the nrdand nwr (nrd1 and nwr1) signals are generatedhere for having the proper timing for the registers reading or writing.
One of these signals is generated and remains active just for theduration of the second low state of the internal nStrobe of anyread/write instruction, when data is transferred into or from register.
Figure 20 The instruction decoder schematic
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Figure 22 shows the timing for all three types of instructions:write to register, read from register and command. The first windowshows a write operation in the control register. The code of thisinstruction is 11H: first 1 means write, and second 1 is the
address of the control register. The data lines available in the chartare the lines coming from the receiver block, and the data to bewritten in the register is not possible to be seen.
The nInhibitR signal becomes active seven clocks after thefirst negative edge of the internal nStrobeand keeps the state untilthe second positive edge of the same nStrobe. The nWR1 is activejust for the second internal nStrobe pulse, when the data is stored inthe register. Its negative edge, together with the register selectionsignal (one of the outputs from the latch15bnumber 2), generatesthe clock for the one of the writable registers. This will be explainedin the next sub-chapter.The second window in Figure 22 shows the waveforms for a read
instruction. This is similar with the writing, just the active internalsignal are different: nInhibitTand nRD(nRD1). The instruction codeis 20H. 2 means read instruction, and 0 is the address of the Statusregister. For the second byte of this instruction, the host has torelease the data lines, and the digital processor will put the data inthe accessed register on the lines. The data will be available on thedata lines only during the second internal nStrobelow pulse.
Write instruction timing (in control register)
Figure 21.a. Instruction decoder timing: write instruction
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The third window in Figure 22 shows the waveforms for a
command instruction. The instruction code is 30H. It is a one-byteinstruction. This instruction starts the irradiation process (opens theion beam, records and process the signal from the ion detector,counts the number of ions and shuts off the ion beam when thepreset number of ions is achieved). Internally, after receiving thiscode, the processor activates, for the internal nStrobe low pulseduration, the nIR signal. This is a low level active signal, and theirradiation state machine will be activated.
This was the description of how the three basic instructionworks. For a write or read operation the difference will be just theregister selection signal which will be different, and for commands
the internal active signal will be changed. The listing of instructions is
Read instruction timing (from status register)
Command instruction (Irradiate)
Figure 22.b Instruction decoder timing: read and commandinstruction
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presented in Appendix 1.
8.4. Registers
The registers bank consists of 7 writable registers (located inside thisblock) and 7 readable registers (spread in other blocks). This block ispresented in Figure 23.The writable registers are 8 bits wide and they can be loaded withdata (Load) and cleared (nrst). The seven writable registers are:
the control register (CR), internal address 1h, internalselection signal C. The bit significance:
D0=gain control bit 0 (G0); D1=gain control bit1 (G1); D2=gain control bit 2 (G2);
D0/G2 D1/G1 D2/G0 Amplifier gain
0 0 0 2
0 0 1 4
0 1 0 80 1 1 16
1 0 0 32
1 0 1 64
1 1 0 128
1 1 1 256
D3= ADC sampling frequency control bit: for D3=0 thesampling frequency is 10MHz and for D3=1 it is 5MHz
D4= accelerator line control: D4=0 the ion beam is OFF andfor D4=1 the ion beam is ON
D5=TV camera switch: D5=0 tape surveillance camera, D5=1fluorescent screen observer camera
D6= fluorescent screen switch: D6=10 screen out, D6=01 screen in
D7= Faraday cup switch: D7=10 cup out, D7=01 cup in the threshold register (TR), internal address 4h, internal
selection signal TH. It stores the threshold value for thepeak detector.
the FF motor register(MFFR), internal address 5h, internalselection signal GFL. Sets the speed of the FF and REWmotor. This value goes to one PWM generator that drivesthe h-bridges for both motors attached to the roles. Theyact like brakes. The value to be sent is 120
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the Preset number of ions registers (PNLR and PNHR).This two form a 16 bits register, their content beingcompared with the ion counter in order to detect the end ofthe irradiation. PNLR has the internal address Bh and
PNHR has the internal address Ch, and the internalselection signals PNIL and PNIH.
the Print register (PRNR), internal address 8h, internalselection signal PRN. The bits of this register directly drivethe needle of the printer head. The Print state machineapply the printing command word just for few hundredsmilliseconds.
the Pressure role motor register (MPRR), internal address7h, internal selection signal GFI. Sets the speed of the tapedriving motor. This value goes to motor controller (motors)
Figure 23 The registers block
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which apply a constant number of pulses (8192) to themotor through the h-bridge.
The readable registers are located in other blocks, here beinglocated just the multiplexer that selects their outputs to the data
lines. These registers are:
Frame counter register 1 (FCLR) internal address 9h,internal selection signal FCL
Frame counter register 2 (FCHR) internal address Ah,internal selection signal FCH. FCLR and FCHR are locatedin the Encreadblock (see Figure 31).
Peak data register (MEM) internal address Fh, internalselection signal PK. MEM register is located in theReadmemmachineblock (see 8.7)
Number of peaks register 1 (NPLR) internal address Dh,internal selection signal NPL.
Number of peaks register 2 (NPHR) internal address Eh,internal selection signal NPH. NPL and NPH registers arelocated in the Peakdetectorblock (see 0).
Input register(INR) internal address 2h, internal selectionsignal IN (not implemented; used for ion fluencemeasurements). Bits 3 to 0 of this register come from thefreqblock (see 8.13)
State register(SR) internal address 0h, internal selectionsignal S. The bit values are updated by different signals inthe circuit (State[x], x=0,17):
Bit 0=State[0] bit signals that the irradiation process is in progress(logic 1) or is ready (logic 0)
Bit 1= State[1] bit signals beam line state: logic 1 means beam onand logic 0 is beam off. This bit is the ACC output which drives thedeflection Faraday Cup.Bit 2= State[2] bit is the full flag signal of the external FIFOmemory.Bit 3= State[3] bit is the empty flag signal of the external FIFOmemory.Bit 4= State[4] bit signals the acquire process (logic 1 means thedata from the ADC is storing in the FIFO memory).Bit 5= State[5] bit signals that the digital processor is printing onthe film (logic 1).Bit 6= State[6] bit signals that the tape is advanced to a new frame(logic 1).
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Bit 7= State[7] bit signals the overflow of the ion flux measurement(logic1).
8.5. Irradiation machine
The irradiation machine is located in irradmachineblock. Its role is tocontrol the irradiation process. The schematic of the irradiationmachine is shown in Figure 24.
The negative edge of the nIRsignal will initiate the irradmachine. Theflip-flops DFF 35 and DFF 36 will set to logic 1: DFF 35 output is the
busy signal which is wired to STATE[0] bit. The output of DFF 36initiates the clearing of the ion counter in the peakdetector block(clearioncountersignal), but the flip-flop will be reset after half systemclock period(10MHz) by the circuit realized with DFF 40, DFF 49,AND 41, AND48, NOT 45 and NOT 50. The clearioncounter signalwill also open the ion beam. After it falls again in logic 0, theirradiation process is started and the ion counter will count the ionsrecorded by the peakdetector block. After reaching the presetnumber of ions, it will return to the irradmachine the endsignal. Thisis a high going pulse, which is the clock signal for DFF 17. Its outputenables a 12 bits counter (12bcount31), which will count 212 systemclocks until it will activate the carryout signal (cout). In order to detect
extra particles that can come in this period (until the beam will be
Figure 24 The irradiation machine
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switched off), the peakdetectormust be maintained enabled a largertime, and if some particles are recorded, than the frame is marked as
bad. The ion beam switching-off time is around 250 s (responsetime of the Faraday cup). The total counting time of the 12bcount is
212100ns=409.6s. This is period is located after the ion beamcommand is activated. The counters carryout signal is than passedthrough DFF 30 and DFF51, in order to avoid the hazard of coutcombinational logic, to generate the ready signal. Its activationmeans the end of the irradiation process. It will reset DFF 35, DFF 17and the 12bcount, leaving the irradmachine block in the same stateas it was at the beginning. The whole circuit is initialized at the powerup, or with an external reset signal via nReset. The following picture(Figure 25) presents the waveforms of this circuit.
The irradiation process timing
Figure 25.a. Waveforms for irradmachine
Detail at the beging
Figure 26.b. Waveforms for irradmachine
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8.6. Peak detector
The peak detector is one of the most important parts of thisprocessor. It makes the digital signal processing of signal comingfrom the detector, and counts the ions, which hit the detector. Itworks in tandem with the irradiation machine. This is a simple versionof the peak detector, but with good results. The algorithm is thefollowing: the noise background is extracted from the data, eachsample is than compared with a threshold and as long as they areabove the threshold the maximum is searched by storing the biggestsample found. When the values of the samples fall under thethreshold, the peak value is available. The threshold is setupaccording to the signal recorded in the calibration step.
The block diagram of the peak detector is presented in Figure28.
Detail at the end
Figure 27.c. Waveforms for irradmachine
COMP
M
COMPADCdata
Threshold
A>B
N
AB
MUX
0
0
1
C
Clk
A
B
A
B
FIFO
WR
RD
Read
F
No of peaks
Figure 28. Peak detector - derivative algorithm
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The algorithm is using the first derivative as peak detection method.The derivative of the signal is changing the sign when the signalpasses through a maximum or a minimum. Considering only thederivative change from positive to negative, only the peaks can be
detected. It is not necessary to compute the derivate values in everypoint
s
kkk
T
xx
dt
dx1=
(3)where xk are the signal samples and Ts is the sampling period,because not the value is important, but the sign. This simplifies theimplementation, because checking the sign is simply performed witha digital comparator.
After separating the pulse from the rest of the signal (MUX),the data stream is filtered with a digital low pass filter (F), in order to
smooth the signal. This is brings the benefit of integration and it isreally necessary because the derivative will detect every local peakin the signal. Then the derivative sign is checked (M and COMP). It isenough to compare consecutive samples in order to determine thesign of the derivative. Comparing with the previous algorithms, thisone ends with the first sample after the peak (the response time isthe pulse rise time).
The schematic diagram of the peak detector is presented inFigure 29. The acquired data is feed at 10MHz into this block throughADCdata[7..0]and it is compared with static data Thresold[7..0]fromthe TR register by the numerical comparator comp126. Its output isused to separate data above the threshold (separate the pulse data
from the rest of the signal). This is accomplished by the multiplexermux8x2to1, which replaces the data under the threshold value withzero. In order to avoid false peaks generated by noises, data shouldbe filtered first before processing. This is accomplished with twocascaded low pass recursive stages:
2
1+= kxk
yxy (4)
Each stage contains an 8 bit sum block (171 and 172) and memoryregister for delay (144 and 161), which compute the equation 4, andthe division by two is just a shift to right with one bit (consider onlythe most 8 significant bits). The register 5 creates a delayed sample(xk-1) at Dout70. The comparator 128 checks the sign of thederivative. Because the pulse can have sometime many consecutive
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samples with the same value, both a>b and a
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8.7. FIFO memory and interface
Due to the wide area that an internal FIFO memory will occupy, theuse of an external memory has been considered. It is a Cypress 32kdual access FIFO. Interfacing this memory asks for 21 pins: 8 datain, 8 data out, 2 for read and write, 1 for reset and 2 for signalingflags. Internally, they are many blocks which read or write from/intothis memory: the peakdetector, the readmemmachine and theacquire blocks. This sub-chapter will describe just the
readmemmachineand some other parts that are not included in any
2 local peaks 1 peak detectedsingle peak
after filtering
Figure 30 Waveforms associated with peakdetector
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block. The schematic of the readmemmachine is presented in Figure31.
According to the CY7C464 data sheet the data become available atthe data outputs at maximum 40ns from the negative edge of theread signal and last 3 ns after the positive edge. In order to read thedata from memory, the readmemmachineuses a register to store thedata and a sequential circuit for generating the read low pulse andthe high load pulse inside it. A Johnson counter (jonson1 4) starts tocount the system clocks when nM is activated. Its Q0 output sets aflip-flop (DFF 19) whos output is MemRd signal. The output Q1 isused to load the data, available on MEMDATIN[7..0] inputs, into theregister (reg1), The output Q3 will reset later the whole sequentialcircuit. After a read from memory instruction the data should be
transferred to computer. A new instruction will just overwrite the old
Figure 31 The readmemmachineblock
Figure 32 Waveforms associated to the readmemmachine
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data. The waveforms showing the functioning of this block arepresented in Figure 32.
8.8. Acquire state machine
In order to adjust the proper gain for the analog chain, the signal thatis acquired by the ADC must be visualized. The acquireblock readsdata coming from ADC and stores it into the FIFO memory. The startmoment of the acquiring process is triggered with a numericalcomparator. This block can be seen in Figure 33.
The comp 1 block compare the data coming from ADC(ADCData[7..0]) with the threshold value (Thresold[7..0]) and starts
the acquiring process. The output agebis masked by the busysignal.This is active (logic 1) after the processor has received the instructionC0h (acquire data to memory). The comp output ageb and busy,drive the set(PRN) input of a flip-flop (DFF4). As soon as nAcqhasbeen activated and the ADC data is exceeding the threshold value,this flip-flop is set to 1 and the logic gate AND28 will leave the clock(which is also the ADC clock) to increment the 32kcounter9. Always,the acquire stores 32k samples in the FIFO memory. The user canread how many he wants (usually 128 are more than enough forseeing a pulse). Transferring the data from chip to computer is quiteslow; it may take few minutes for 32678 samples. Coming back to thecounter, its clock is also the signal MemWr, and on the positive edge
the data is stored into memory. After completing the acquire
Figure 33 The acquireblock
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(32counterfull), its carry-out signal stops this process and reset the
entire machine (DFF18, DFF4 and 32counter9). The signal busyismapped into the state register (STATE[4]).
8.9. Printer state machine
This block has been designed to generate signals for the printerdrivers according to the information contained in the PRNR. Theschematic is in Figure 34. The block is organized around a 3 bits shiftregister (DFF8, 9, 10). It is initially loaded with 100, and at the endof printing process is loaded again with the same state. When theinstruction decoder receives the printing instruction (90h), it activatesthe nPRNsignal (logic 0). The flip-flop DFF4 will be set-up at the
falling edge of this signal, activating the busysignal and starting theprinting process. Printing means activating the needles once. Thishappens when the shift register is in the state 010. The clockfrequency of the register is around 4.76Hz. This means the printingpulse is 210 ms long. The outputs of the print register (PRNR) arechopped by the outputs 2 of the pulse register through 7 AND gates(16 to 21 and 23). When DFF 10 receives the logic 1 (state 001) theblock is returning again in the initial state (shift register and DFF 4are reset).
8.10. Encoder reader
This block is named encreadin the project and reads the data from
Figure 34 The print machine
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the angular encoder of the pressure role driving motor andtransforms it into frames count. The inputs are two quadrature squarewaves ChanelA and ChanelB in Figure 35. They are generated bythe angular encoder attached to the pressure role motor, and they
are processed by debouncer blocks before.
The main parts are the two 10bits up-down counters: the pulsecounter and the frame counter (counters 25 and 42). They are usedin the present design just as a indicator for the frame length.Because the number of pulses given by the encoder is 2520 perrotation, and the circumference of the driving role is 63 mm, thenumber of pulses per frame is about 800 for about 20 mm. Thismeans that the role will turn one third of turn for advancing the tapeto a new frame. The counter carry output cout is the clock signal for
the next counter. The signals q[8]and q[9]were used to generate asignal (slow) used by other block (Motors) to decide the speed of thetape. First the tape was pulled with low speed (according to the valuein MPRLR) then it runs with high speed (according to the value inMPRR), and in the end again with the low speed. This regime waschosen in order to avoid the pressure role slipping on the film, and toprevent long stopping time. Actual design does not use this, s lowbeing unused. The block Motors applies a constant number of pulsesto the PR motor.
In order to choose the right count direction the DFF 3 hasbeen used. ChanelA is the clock signal and ChanelB is the datainput. If the motor is turning forward, ChanelB has an advance of onequarter of period from ChanelA, and the rising edge of the ChanelA
Figure 35 The encreadblock
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will find ChanelB in logic 1 and DFF 3 will go to logic 1. The pulsecounter and the frame counter will count forward. If the motor isturning backward that ChanelB is delayed with a quarter of period,and the flip-flop will go to logic 0, determining the counters to count
backwards. The counters can be initialized (reset) with external resetsignal or when resetting the registers (instruction A0h). This featureis used only for monitoring the frame length.
8.11. PWM generators
In order to drive motors with variable power and speed, it isuniversally accepted that the most efficient way is to use H-bridgeand PWM (pulse-width-modulation) signals. What is an H-bridge?This is a bridge that has on its arms transistors, complementary onthe opposite arms. One diagonal is connected to the power supplyand on the other the load must be connected. More details can be
find in 10. What is pulse width modulation? It is a square wavesignal for which the ratio between the logic 1 period and the 0 logicperiod can be varied from 0 to 100%. The transistors act as switchesapplying to the load the power supply with different polarity and forvariable repetitive time. The load (motor) acts as a filter and thePWM signal is filtered and only the DC component will be extracted.
The idea to realize such generator in digital is coming fromanalog: a triangular wave generator and a comparator with variablethreshold. The same way can be followed for digital implementation.The triangular generator is an up-down counter and the comparatoris replaced with a numerical comparator. The counters output iscompared with a constant value or with a quasi-constant one
Figure 36 The PWM generator schematic
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(compared with the PWM frequency), and at the output of thecomparator the PWM signal is available. This is the general idea thatis used for the PWM in Figure 36.
The up-down counter 8bcount 1 is the triangle wave
generator. It is an 8 bits counter. It is incremented or decrementedwith a clock of 312.5 KHz (clkdiv4) this meaning that the PWMfrequency is about 312.5 KHz / 512=610Hz. Unfortunately this is anaudio frequency but the sound generated by the motors is anyhowcovered by the other sounds in the irradiation room. It counts up 256clocks until the carry-out signal signals that the counter is full. DFF 9is avoiding the false signals due to the combinational logic thatgenerates the carry signal, by sampling it on the falling edge of theclock. Using another flip-flop (DFF 2), the counting direction ischanged based on this carry signal. Thus the counter output islinearly grows from 0 to its maximum and then linearly decreaseagain to 0. Its outputs are compared with a constant threshold value,
val[7..0]), that is preset through registers (MFFR, MRR, MPRHR,MPRLR). As long as the counters output is smaller than thethreshold, the PWM signal is logic 0, and it switch to logic 1 when itbecomes greater than the threshold. The greater-than output (agb)sampled on the falling edge of the clock is the PWM output. It isavailable with both polarities because two transistors have to bedriven with one polarity and the others with the opposite polarity dueto their complementarity. Some simulation waveforms can be seen inFigure 37.
8.12. Motor control block
This block is dedicated for driving the pressure-role motor. In order toobtain stepped PWM driving (low-high-low) the threshold value at the
input of the PWM generator must be changed at precise times. This
Figure 37 PWM waveforms
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blocks schematic is presented in Figure 39.
When the device receives the instruction 80h, the signal nSF isactivated (see the top level design in Appendix 2) which is connectedto signal go. The flip-flop DFF2 is set and the busysignal toggle tologic 1. It is wired to STATE[6]bit in the status register. It signals thatthe tape is advanced to the next frame. It opens the gate AND 33and the PWM signal will flow to the h-bridge. The pulsecnt53 counts8192 PWM pulses until the cout output will reset the counter and
Figure 38 Simulation waveforms from the block motors
Figure 39 Pressure role motors control block
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DFF 2. The simulation waveforms can be studied in Figure 38. Using15KHz PWM, the frame length will be almost constant around 22 mm(between 20.5 and 23.5 mm).
8.13. Ion flux measurement
Flux measurement implies a frequency-meter. It must count thenumber of ions hitting the detector during one second. The result isavailable in 8 bits format on INR. The schematic of this block (namedfreq) is available in Figure 40.
Usually a frequency-meter is based on a dividing gate (AND21) andon one counter (fr8bcount65). The pulses to be counted pass to thecounter as long as the gate signal (DFF68 output) is in logic 1. In ourcase the gate signal is clkdiv16 divided by 76 (count75). Thefollowing flip-flop (DFF 74) makes a division by 2: this means thehigh state of this signal is almost 1.003 s, this being the countingtime. This time value has been chosen because of simplicity ofschematic (it is not necessary another dividing chain). During thistime any pulse which occurs is counted. The digitized signal istriggered by a digital comparator (8bcomp 71), its synchronizedoutput being the signal carrying the information about the ion flux tobe counted. The measured value of the flux (fr8bcount65) is just alittle bit different from the real value, but corrections can be operatedon computer or on the host processor if they are really necessary.The counter has a carry-out output which is signaling the overflow(STATE7 in state register). Its outputs are temporarily stored in an 8bits memory (8bitreg 66) in order to make it available till the next
measurement ends. Assuming that the flux is constant, the indicationwill be stable. In reality, due to the statistic occurrence of the ionpassing through the aperture, the value will change. The maximum
ion flux value that can be measured is 256 ions/1.003s256 ions/s.DFF42 andjonson1 53 generate two pulses for loading the result inmemory (Q0) and for resetting the counter for a new measurement(Q1). The associated waveforms for this block are presented inFigure 41.
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One can see the counting time, 996.1472s, and pulses are
very condensed at the beginning of the interval.There are 20 groups of two pulses each (a), this means 40 pulses(see Freq[7..0] in Figure 37).
Figure 40 The ion flux-meter schematic
Figure 41 Waveforms associated to the freqblock
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8.14. Driving flipping magnets
In order to drive the flipping magnets for Faraday cup and fluorescentscreen, pulse generators must be used (Figure 43). The signals fordriving these magnets are mapped in the control register (CR): bitsD6 and D7. As it is said before, logic one means IN and 0 meansOUT. Because the flipping magnets must be driven just with a shortpulse (small power dissipation) the edges must be detected. For thepositive edge will be a pulse acting one branch of the bridge, and forthe negative edge another pulse acting the other branch. In order toobtain these pulses the following schematic has been used. The ideais simple. An edge sensitive flip-flop is used to start the pulse (DFF1or DFF 14) on the desired edge (Signal). Its output is the pulseoutput. Also, it allows the clock to reach a counter (counter7 or 16)through a AND gate (AND2 5 or AND2 15). The counter counts 7
a) detail
b) detail of the detail
Figure 42 Waveforms associated to the freq block (detail)
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clock periods and then reset the flip-flop and itself through QD output.The pulse length is about 7 clock periods (CLKDIV[17]). This means
the pulse duration is about 267 s.The waveforms are available in Figure 44. Two such detectors areused: one for Faraday cup (bit D7) and one for the fluorescent screen(bit D6).
8.15. Digital circuit schematic
The entire schematic of digital processor is shown in thefollowing figure. The only parts left unexplained are the ADC clockmultiplexer (clkmux 10) and the ACC signal mixer, but they are
supposed to be very simple.
Figure 43 The edge detection circuit
Figure 44 Waveforms associated to the edge detector
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Digital processor schematic
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The pins assignment for the FPGA is shown in the Figure 45.It was done like this in order to achieve a simple PCB.
The external digital electronics around this processor isreduced to the FIFO memory and some gates. It also includes the
EEPROM (EPC2LC20) for configuring the FPGA at power-up, resetcircuit, connectors with other blocks, the JTAG programminginterface and a 20MHz oscillator. The connection with EPC2 memoryis the classic one for multi-device JTAG chain configuration. Someconnectors for debugging the hardware are available too. This partcan be found in Error! Reference source not found..
9. Communication interface
The digital processor must be driven by a host computer or byprocessor. It just receives instructions and executes them or sendsdata back. The interface is a parallel one, having 8 bits bidirectional
data lines and one strobe signal driven always by the host (computer
Figure 45 Pin assignments for FPGA
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or processor). The digital processor acts like a slave.The present setup uses a laptop computer as host, equipped
with a data acquisition board. For the communication interface theavailable on DAQ digital port and one counter output is used. The
interface is simple and fast enough.
9.1. Data acquisition board
The data acquisition is DAQ 6062E. It is PCMCIA card, withanalog inputs and outputs (12 bits), digital I/Os and counters. Itscharacteristics are described in appendix 4. Any other board basedon DAQ-STC device can be used, without changes in the software.The connection diagram is shown in Figure 46.They are some extra comments to make:
the GPCTR1OUT is connected to the reset switch contacts(SW1 on Error! Reference source not found.)
The digital processor and all the digital circuitry must besupplied from the computer power supply available at theDAQ connector. For unexplained reason (even fromspecialists from Altera) the communication does not workproperly if the power supply of the digital processor isdifferent. In this case very often the data that digitalprocessor receives or sends is FFh and not the proper one.
Digital processor
(FPGA FLEX10k10LC84)
Host computer
(DAQ 6062E)
DIO0
DIO1
DIO2
DIO3
DIO4
DIO5
DIO6
DIO7
nStrobe
Reset
+5V
DIO0
DIO1
DIO2
DIO3
DIO4
DIO5
DIO6
DIO7
+5V
GPCTR0OUT
52
17
49
47
19
51
16
48
40
8
2
16
17
18
19
21
22
23
24
to reset switch
to Vcc
25
GND DGND 44to ground
GPCTR1OUT
Figure 46 Connections for the communication interface
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It must be possible that some latch-up phenomenon canoccur because of tri-state circuits used inside the digitalprocessor.
9.2. Communication protocol
The communication protocol is a simple one. It must be amaster, which are a computer or another processor and a slave,which is the above described digital processor. The slave is alwayswaiting for instructions. The master puts the data on the data lines(instruction code) and then activates for short time the nStrobesignal(low going pulse). This pulse must not be shorter than 6 systemclocks (600ns) due to the debouncer circuit, which samples thenStrobe for 5 consecutive clock cycles. The digital processor usesthe falling edge of the nStrobe signal to store the signal in thereceiver latch. The data must be stable on the data lines at least 4 ns
after the negative edge of the IntStrobe. For safety, the data mustremain unchanged until the nStrobe returns to logic 1. If theinstruction is a command (codes greater than 30h) then this is asingle byte instruction. It ends after the releasing of nStrobe. Thehost must test afterwards the status register, to find out when theexecution of the started instruction will end, by testing thecorresponding bit. If the instruction is a read/write one, than after thefirst byte a second one should be transferred. If the instruction is awrite one (codes 1Xh), then the host must put the data on the lines(the value to be written) and activate the nStrobesignal longer than1.15s, time necessary for the data to be stored in the addressedregister. If the instruction is a read one, then the host must switch itslines direction to input and afterwards activate the nStrobe. Starting1.3us after the nStrobefalling edge the data will be available on thedata lines, and it stays there as long as the nStroberemains low.
The instructions codes and their description can be found inError! Reference source not found..
10. Power circuits
The power circuits are used for driving the motors and theprinter head. Also, driving the accelerator line asks a leveladaptation. All this circuits are subject for this chapter.
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10.1. Motors drivers
The irradiation system contains three motors. All motors are drivenusing the same schematic: galvanic separated H-bridge. The
schematic is presented in Figure 47.The driving signals are TTL level (pins 3 and 4 on J3
connector) and they are coming directly from the FPGA. The bridgeis optically coupled with the rest of circuit in order to protect the lowpower electronics. Two transistors were used as buffers to drivecommon type optocouplers (CNY17). The power transistors in thebridge are Tip102 for NPN and TIP105 for PNP. These are too big forthis purpose, but they were available from an old printer. Also, lesspowerful transistors can be used (BD 677 and BD678). The bridge issupplied at 12V DC.
Applying +5V to pin 3, Q6 will open to saturation, and theLEDs in optocouplers U3 and U1 will light. The phototransistors from
U3 and U1 will be saturated also (0.2-0.4V collector-emitter voltage).The current flowing through these transistors will generate a voltagedrop on the resistors R1 and R3, which will open the powertransistors Q1 and Q3 to saturation. Then the load, connected at J2will be supplied with around 10V, with plus on pin 1 and minus onpin2. If the driving signal is pulsed one, the load is connected to thepower supply just for short time during one period of the pulsed
+12V
GNDPOW
M-M+
+5V
U1
CNY17-4
16
2
5
4
U4
CNY17-4
1 6
2
5
4
U2
CNY17-4
16
2
5
4
U3
CNY17-4
1 6
2
5
4
R8
100k
R6
100k
R7
100k
Q5
Q2N2222
Q6
Q2N2222
R1
1k
R2
1k
R4
1k
R3
1k
J2 Motor
1 2 J1
12V
1
2
J3 TTL1234
R11
1k
R12
1k
R9
100
R10
100
R5
100k
Q2
TIP102
1
3
2
Q4
TIP105
1
2
3
Q3
TIP102
1
3
2
Q1
TIP105
1
2
3
Figure 47 H-bridge schematic
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signal. If the load is inductor or motor, it acts like a low pass filter,and only the DC component will be used. Varying the filling factor ofthe pulsed wave, the DC voltage can be changed. It results a niceand simple control of the DC on the load (from zero to maximum).
The same description is available for the other branch (Q5, U2, U4,Q2 and Q4). This time, the polarity applied to the load is minus on pin1 and plus on pin2 (reversed as in the previous). Some simulationwaveforms are presented in Figure 48. The bottom plots show thetwo driving signals at the J3 connector (V(V1:+) and V(V2:+)), andthe top one shows the voltage V(Q1:c,Q4:c), on the load (pureresistive). In this case, the DC component is zero, but it was chosento demonstrate both polarities.
The same schematics are used too for driving the magnetswhich switch in and out the Faraday cup and the fluorescent screen.The driving signal is just one short pulse, on one or the other input.How this is done is described above in paragraph 0.
10.2. Printer head drivers
The printer head consists of nine needles (only seven are used)actuated by 9 coils. They accept for short time voltage between 5and 12 V, and the needle will be advanced for about 1mm. The coilresistance is about 6 ohms. This means a quite high impulse current.
To drive the coils Darlington transistors like in Figure 49.
Time
0s 0.2ms 0.4ms 0.6ms 0.8ms 1.0ms 1.2ms 1.4ms 1.6ms 1.8ms 2.0ms
V(V1:+)
0V
2.5V
5.0V
V(V2:+)
0V
2.5V
5.0V
V(Q1:c,Q4:c)
0V
10V
-11V
SEL>>
Figure 48 Waveforms for H-bridge
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It consists of 9 optocouplers that drive 9 TIP102 transistors,acting like switches. No protection diodes are necessary becausethey are included in the transistors. The connector J3 brings TTLsignals from FPGA and J6 is attached to the printer head.
10.3. Driving TV cameras
In the irradiation system there are two video cameras available.One is inside the accelerator pipe, in vacuum, attached to the beamdiagnostic system. It is suited for observing the fluorescent screen.The second one is outside, and it is attached to the tape roller. The
Q16
TIP102
1
3
2
Q11
TIP102
1
3
2
U12
CNY17-4
1 6
2
5
4
U11
CNY17-4
1 6
2
5
4
U10
CNY17-4
1 6
2
5
4
U5
CNY17-4
1 6
2
5
4
U19
CNY17-4
1 6
2
5
4
U18
CNY17-4
1 6
2
5
4
U13
CNY17-4
1 6
2
5
4
U25
CNY17-4
1 6
2
5
4
J6
Print Head
1
3
5
7
9
11
13
15
17
2
4
6
8
10
12
14
16
18
R26
1k
R11
1k
Q5
TIP102
1
3
2
Q10
TIP102
1
3
2
R59
100k
R70
100k
R35
100k
R38
100k
R45
100k
R52
100k
R6
100k
R17
100k
R28
100k
R75
1k
R68
1k
R57
1k
R50
1k
R43
1k
R36
1k
R33
1k
R34
330
R27
330
R16
330
R5
330
R58
330
R51
330
R44
330
R37
330
R69
330
J3
CON12
1
2
3
4
5
6
7
8
9
10
11
12
U24
CNY17-4
1 6
2
5
4
Q33
TIP102
1
3
2
Q28
TIP102
1
3
2
Q23
TIP102
1
3
2
Q22
TIP102
1
3
2
J32
+12V
1
Q17
TIP102
1
3
2
J33
-12V
1
Figure 49 Printer head driver
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operator can observe the tape movement and if something does notwork. Because the system is thought to be mobile, only one image isavailable at a time through the Hauppage video capture device. Thispart has the role to switch both, the video signal and the power
supply signal to one or the other video camera.Figure 51 shows this circuit. It is driven from FPGA (pin 79 from
Flex10k10) through an optocoupler CNY17-4. It drives two TTLcompatible relays. One switches the video signals (K1) and thesecond switches the power supply (K2). Switching the power supplyis necessary because the video camera is getting hot and it cannotbe cooled in vacuum.
10.4. Interfacing the beam shutter
The beam shutter needs a voltage greater than 5V in order tocompletely shut off the ion beam. The previous experiments with TTLlevel drivers were unsuccessful. A continuous track of holes has
been obtained after etching the polymer. The electrostatic beamshutter is driven through an optocoupler in order to insulate thedevice and to ensure proper protection. The adapter schematic ispresented in Figure 50. It consists of a 6.4 V stabilizer (7805 + 2 x1N4148), a switch transistor (BD190) and an optocoupler (CNY-17).Applying TTL logic H (around 3.5V) on ACC input will open theswitch transistor (BD190). Its saturation voltage is around 0.4V. Thecollector is connected to the shutter and delivers around 6V, which ismore than enough for completely shutting the ion beam (specificationfrom Uppsala is 5V for completely switch off the beam).
D2
1N4148
D1
1N4148
+C2
10uF
+ C110uF
J1
+5V
1
2
R1100kR2
330
J3
Out
1
2
3
4
5
J2
IN
1
2
3
4
5
Q1BD190 1
3
2
R3
10k
U3LM7805C/TO220
1 3
2
IN OUT
GND
U2 CNY17-1
16
2
5
4
Figure 50 Beam shutter interface schematic
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11. LabView program
The LabView programs are designed for driving the cameravia the 8 bits interface ( 8.1). Two programs are available: one foracquiring pulses in order to establish the gain and the threshold andthe other for performing the irradiation. Both of them are described inthis chapter. Before starting the experiment, all VI's should bepublished on the Web. For this the operator must go in Tools, WebPublishing Tool, and there do "Save to Disk" and "Start Web Server".The operator must note the web addresses by clicking "Preview inBrowser". Then the VI's can be operated from other computer viaInternet Explorer. The computer used for remote must have LabViewRun Time Engine installed. Right mouse button must be clicked andselect "Request Control" in order to operate via html. The addressesare like:http://computername.domainname/Main.htm,http://computername.domainname/Irradiation.htm,http://computername.domainname/Acquire.htm,http://computername.domainname/BeamDiagControl.htm.
11.1. Main control program
For easyness of operation the VI's which operates the camera can be
+12V
-12V
-12V
J16
12V Cam1
1
2
3
4
5
J17
12V Cam2
1
2
3
4
5
R78
270
U26
CNY17-4
1 6
2
5
4
R79
100k
K1
VIDEO
8
16
1
314
K2
CAM POWER
8
16
1
314
R90
100
D1
1n4148
J12
TVCam
1
2
3
4
5
J11
Video1
1
2
3
4
5
J14
Video2
1
2
3
45
J15
Video Out
1
2
3
4
5
Figure 51 Schematic for switching the video camera
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started from the main control panel. This instrument is called Main.vi.It allows to open and close other applications and to reset the digitalprocessor in the FPGA. The main panel is presented in Figure 52.
On the panel there are three butons (Beam trimming, Acquireand Irradiate) with arrows between them. The arrows show the orderthe operator should follow. First the beam must be trimmed. After thisis accomplished, the next operation is to check the quality of thesignal and trimm the gain of the preamplifier. For this the "Acquire"button must be pressed. This action will close the previousapplication and open Acquire.vi. "GO" button will start the acquiringprocedure. After accomplishing the gain trimming, one can start theirradiation procedure. By pressing the "Irradiate" button, any other VIwill be shut down and Irradiation.vi will be activated. After setting upthe irradiation parameters, the operator has to press GO button tostart the procedure.
On the panel there is also "Reset FPGA", which will reset tehdigital processor, and the "Stop" button that closes the Main.vi.Warning: "Reset FPGA" must not be pressed when acquire or
irradiation processes are running. It is available only for extremecases, when the system is not responding.
Figure 52 Main.vi front panel Figure 53 BeamDiagControl
front panel
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11.2. Beam diagnostic VI
The process of trimming the ion beam is achieved at the
beginning. The instrument available for this operation isBeamDiagControl.vi. Its Panel is shown in the next figure.
This instrument can control the beam diagnostic system(Faraday cup magnet, fluorescent screen magnet, TV camera switchand the beam line and the gain and sampling frequency. Also itdisplays the ion flux measured by the digital processor and theoverflow signal for the flux meter.
11.3. Acquire VI
In principle this VI activate the acquire block inside the FPGA.This action must be preceded by settings and succeeded by reading
the acquired data from FIFO. The front panel of this VI is presentedin Figure 54. In the top left part the operator can find somecontrollers:
Gain control pointer slide button - for adjusting the gain of thepreamplifier. Four steps are available (20, 40 80 and 160). Thesewere the gains for the previous version. For the current version 4more steps must be introduced.
ADC Clk control - adjust the ADC clock frequency. Also fourvalues are available: 10, 5, 2.5 and 1.25 MHz
The threshold controller - for setting-up the threshold for startingthe acquisition. When a pulse occurs and the signal level is goingabove this threshold, the data is then routed to FIFO memory. On
its right is an indicator that points the same threshold value but inADC counts.In the top-left there are some indicators:
Info field- gives information about the current process: Waiting foracquire to finish, Downloading data
Progress bar - shows the progress of the data downloadingprocess from FIFO to computer
Status register indicator- shows with LEDs the states of every bitin the status register
Sample- shows the value of current read sample when transferredfrom memory to computer
The Peaks data graph- shows the acquired waveform
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The path dialog- located at the bottom of the screen, correspondsto the path where the file with recorded data will be stored oncomputerThe diagram of this VI, described in the following, is shown
detailed in Error! Reference source not found.. It consists of asequence structure with 7 frames.
The first frame (frame 0) reset the digital processor. For this,GPCTR 1 is used in order to generate an about 200ms positivepulse.
The second frame (frame 1) creates the file for saving the data,
adding in the title AcqData, the time (hours, minutes and seconds)
Figure 54 Acquire.vi front panel
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and the extension .txt. The file is spreadsheet type (ASCII).The frame 2 writes in the control register. The gain and the
sampling frequency will be programmed and also the ion beam isbeing open. A sub-vi, called Write data to register is used. The
delay of 100ms is not so important and can miss. The instructioncode is 17d=11h.
The fourth frame (frame 3) is setting up the threshold (the value ofthe signal which starts the acquisition process). The thresholdsdecimal value must be converted in ADC counts and using theinstruction 20d=14h this is sent to the register in FPGA.
The following frame (frame 4) is clearing the FIFO memory. Theinstruction code is 176d=B0h.
Frame 5 reads the state register (instruction 32d=20h) anddisplays this on the front panel.
Frame number 6 includes another sequence structure, also with 7frames. Subframe 0 reads the state register and displays its status.
Subframe 1 resets the memory again. Subframe 2 starts the acquireprocess (instruction 192d=C0h). Subframe 3 reads the state registerand verifies if acquiring is end (bit 4=0) in a while loop. If thecondition is accomplished, then (subframe 4) the ion beam is cut off(write in control register and reset the bit 4) and the programm quitsthe while loop. Subframe 5 brings data from FIFO to computer,converts into voltage values and stores them in a vector (SampleData). This is done in a for loop, executing a sequence that loads asample value from FIFO into FPGA (64d=40h), reads the stateregister and displays it, brings the sample value into the computer(47d=2Fh) using the subvi Read Data from Register and convertsthe data to voltage. Subframe 6 reads and displays again the stateregister (operator can check if FIFO is empty) and subframe 7 savesthe data to disk.
Frame number 7 closes the file and the program ends. It has to berestarted for a new acquire.
The subvis will be described in the following paragraph.Downloading more than 128 samples takes too long time and no
additional information will be obtained. This is necessary for high flux,but it takes long time for all 32k of data.
11.4. Irradiation VI
This is instrument is the main one. It operates the whole systemduring irradiation. It allows setting up the parameters, running the
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process and recording data. The main panel is shown in Figure 55. Itcontains controls, info field, graphs and digital displays. Theirfunctionality is described in the following.
Gain controls slide for the preamplifier gain. This value goes in
bits 0 and 1 in control register. F sample control slide button for the ADC sampling frequency.
Four sampling frequencies are available: 10MHz, 5MHz, 2.5MHzand 1.25MHz. This value goes in bits 2 and 3 in control register.
Threshold digital control for the threshold value (above whichthe digital processor inside FPGA considers that a pulse starts). Itis displayed in ADC counts too. This value goes in TR.
No of Ions/Frame control for programming the number ofdesired ions per frame. This value goes in PNILR and PNIHR inFPGA.
No of Frames program the desired number of frames for thecurrent irradiation.
Fluorescent screen this button flips in and out the fluorescentscreen. This is bit D6 in control register.
Faraday Cup this button flips in and out the Faraday cup forbeam intensity measurements. This is bit D7 in control register.
Video it switch the images from video cameras: Beam Camerafor looking o fluorescent screen or Tape Camera to survey thetape motion.
Minimum energy control the minimum value for accepting goodpeaks
Maximum energy- control the maximum value for accepting goodpeaks
Good Frame is a digital indicator. Green light for this indicatormeans that the current frame had fulfilled the tests and isconsidered good one.
Comments character field in which the user can introduce somecomments about the irradiation that he wants to be saved in thefile.
Info Field for displaying messages about the current action. Frame Counter - displays the frame counter value (the software
counter)
No of Ions Detected- Displays the number of ions detected in thecurrent frame.
Peak- the value of the peak that is currently brought from FPGA. Peaks Data Graph - displays the amplitude of peaks detected
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versus the frame number (the history of irradiation process)
Channels- displays the results of the multichannel analyzer. Folder- the folder where the data file will be saved.
12. Mechanics
The mechanical part includes the beam diagnostic system and thetape roller. The first one is located inside the beam line, in vacuum,and the second one is attached through a flange by the first and islocated outside the vacuum. Both will be described in the followingparagraphs.
Figure 55 Front panel of main.vi
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12.1. Beam diagnostics
The beam diagnostic system has been designed to fit in a standard
accelerator pipe, in order to adjust the ion beam for the desired flux.As it was briefly described in the paragraph 2.1, it contains a Faradaycup, a fluorescent screen actuated by flipping magnets and a TVcamera. All are mounted in a metallic structure, like shown in Figure56 and Figure 57.
On the mounting flange are fixed four metallic cylinders whichsupport two plates (black and yellow in the figures above). The blackplate is metallic and supports the TV camera. In the middle it has ahole to allow the ion beam to pass forward. Under the first plate it is aflipping magnet and the fluorescent screen. This can be flipped inand out for diagnosing the ion beam. When it is flipped in, it blockedthe ion beam, the ions being stopped in the screen. No beam will be
recorded at the detector level. Under the fluorescent screen the
TV camera
Fluorescent
screen
Flipping magnet for Faraday cup
Flipping magnet for
fluorescent screenMounting
flange
BNC connector
BNC connector
Figure 56 Beam diagnostic system
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Faraday cup is located together with its flipping magnet. A betterview is in Figure 57, where the Faraday cup is colored with blue.
After this level, the vacuum ends. A metallic plate closes the beamline. In its center there is a hole and a nozzle on top (blue in the left
side of Figure 57, with a very fine hole (50 300 m) covered with atitanium foil (6 m thick) for vacuum separation. In accordance withthe irradiation angle, the nozzle has to be changed. Two types wheredesigned, one for 90 degrees and another for 35.26 degrees, thesebeing the angles of interest.
12.2. Tape roller
The tape roller is dedicated for polymer tape transport in front of theion beam. A 3D view is presented in both Figure 58 and Figure 55.
TV camera
Fluorescent
screen
Flipping magnet for Faraday cup
Flipping magnet for
fluorescent screen
Mountingflange
C connector
BNC connector
Faraday cup
O ring
Figure 57 Beam diagnostic system
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Base plate
Tape role
TV camera
Ion
detector
Rubber
pressure
role
Needle printer head
DC motor
with
encoder
for tape
advance
Role
Role
DC motors
Metallic
role
Figure 58 Tape roller (bottom view)
Base plate
Tape rolesTV camera
Polymer
tape
Ion
detector
Rubber
pressure
role
Needle printer head
DC motor
with
encoder
for tape
advance
Guiding
role
Guiding
role
y
x
z
Figure 59 Tape roller
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Everything is hosted by an aluminum plate with four metallic legs.The polymer tape is supplied from the right tape role and it iscollected on the left tape role. Each role has attached one DC motor(Figure 58), which can act as a break or pull, or can role the tape
from one role to the other (FF and REW). The tape is guided by twoguiding roles and pulled by the metallic role an
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