introduction to vlsi asic design and...
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Paulo Moreira Introduction 1
Introduction to VLSI ASIC Design Introduction to VLSI ASIC Design and Technologyand Technology
Paulo Moreira
CERN - Geneva, Switzerland
Paulo Moreira Introduction 2
Outline
• Introduction – “Is there a limit?”• Transistors – “CMOS building blocks”• Parasitics – “The [un]desirables”• The CMOS inverter – “A masterpiece”• Gates – “Just like LEGO”• Sequential circuits – “Time also counts!”• Storage elements – “A bit in memory”• Technology scaling – “…, faster”• Technology – “Building an inverter”
Paulo Moreira Introduction 3
Introduction
First point contact transistor (germanium), 1947John Bardeen and Walter Brattain
Bell Laboratories
Audion (Triode), 1906Lee De Forest
1906 1947
Paulo Moreira Introduction 4
Introduction
Intel Pentium II, 1997Clock: 233MHz
Number of transistors: 7.5 MGate Length: 0.35
First integrated circuit (germanium), 1958Jack S. Kilby, Texas Instruments
Contained five components, three types:transistors resistors and capacitors
1958 1997
Paulo Moreira Introduction 5
“The world is digital…”
• Analogue looses terrain:– Computing– Instrumentation– Control systems– Telecommunications– Consumer electronics
Paulo Moreira Introduction 6
“…analogue, alive and kicking”
• Amplification of very week signals• A/D and D/A conversion• RF communications• Very high frequency amplification and signal
processing• As digital systems become faster and
faster and circuit densities increase:– “Analogue” phenomena are becoming
important in digital systems
Paulo Moreira Introduction 7
“Moore’s Law”
The number of transistors that can be integrated on a single IC grows exponentially with time.
“Integration complexity doubles every three years”Gordon MooreFairchild Corporation - 1965
Paulo Moreira Introduction 8
Trends in transistor count
(From: http://www.intel.com)
Number of transistors doubles every 2.3 years(acceleration over the last 4 years: 1.5 years)
42 M transistors
2.25 K transistors
Increase: ~20K
Paulo Moreira Introduction 9
Trends in clock frequency
2 GHz
Intel LabsSub-ps switching transistorµP clock > 20 GHzGate length: 20nmGate oxide: 3 atomic layersIn production: 2007 !
Paulo Moreira Introduction 10
Trends in feature size
0.13 µm inproduction
Intel LabsSub-ps switching transistorµP clock > 20 GHzGate length: 20nmGate oxide: 3 atomic layersIn production: 2007 !
Paulo Moreira Introduction 11
Driving force: Economics (1)
• Traditionally, the cost/function in an IC is reduced by 25% to 30% a year.
• To achieve this, the number of functions/IC has to be increased. This demands for:– Increase of the transistor count– Decrease of the feature size (contains the
area increase and improves performance)– Increase of the clock speed
Paulo Moreira Introduction 12
Driving force: Economics (2)
• Increase productivity:– Increase equipment throughput– Increase manufacturing yields– Increase the number of chips on a wafer:
• reduce the area of the chip: smaller feature size & redesign
– Use the largest wafer size available
Example of a cost effective product (typically DRAM): the initial IC area is reduced to 50% after 3 years and to 35% after 6 years.
Paulo Moreira Introduction 13
2002 and beyond ?
Semiconductor Industry Association (SIA) Road Map, 1998 Update
1999 2002 2014Technology (nm) 180 130 35Minimum mask count 22/24 24 29/30Wafer diameter (mm) 300 300 450Memory-samples (bits) 1G 4G 1TTransistors/cm2 (µP) 6.2M 18M 390MWiring levels (maximum) 6-7 7 10Clock, local (MHz) 1250 2100 10000Chip size: DRAM (mm2) 400 560 2240Chip size: µP (mm2) 340 430 901Power supply (V) 1.5-1.8 1.2-1.5 0.37-0.42Maximum Power (W) 90 130 183Number of pins (µP) 700 957 3350
IEEE Spectrum, July 1999
Special report: “The 100-million transistor IC”
These scaling trends will allow the electronics market to growth at 15% / year
Paulo Moreira Introduction 14
“Is there a limit?”
Silicon lattice constant: 5.42 AGate oxide: 1.2 nm≈ 3 Si atomic layers!
Paulo Moreira Introduction 15
“Is there a limit?”
Source: D. Frank et al., Proceedings of the IEEE, 3/2001
Paulo Moreira Introduction 16
“Is there a limit?”• High volume factory:
– Total capacity: 40K Wafer Starts Per Month (WSPM) (180 nm)– Total capital cost: $2.7B
• Production equipment: 80%• Facilities: 15%• Material handling systems: 3%• Factory information & control: 2%
• Worldwide semiconductor market revenues in 2000: ~$180B– Semiconductor market growth rate: ~15% / year– Equipment market growth rate: ~19.4% / year– By 2010 equipment spending will exceed 30% of the semiconductor
market revenues!
• HEP, where are we:– Total LHC production: less than two production days for #10 world
wide semiconductor manufacturer in terms of volume.
Paulo Moreira Introduction 17
How to cope with complexity?
• By applying:– Rigid design
methodologies– Design automation
Rigid DesignMethodologies
Design Automation(CAE Tools)
SuccessfulDesign
Paulo Moreira Introduction 18
Design abstraction levels
System Specification
System
Functional Module
Gate
Circuit
Device SG
D
+
Leve
l of A
bstra
ctio
n
Low
High
Paulo Moreira Transistors 19
Outline
• Introduction – “Is there a limit?”• Transistors – “CMOS building blocks”• Parasitics – “The [un]desirables”• The CMOS inverter – “A masterpiece”• Gates – “Just like LEGO”• Sequential circuits – “Time also counts!”• Storage elements – “A bit in memory”• Technology scaling – “…, faster!”• Technology – “Building an inverter”
Paulo Moreira Transistors 20
“CMOS building blocks”
• “Making Logic”• Silicon switches:
– The NMOS– Its mirror image, the PMOS
• Electrical behavior:– Strong inversion
• Model• How good is the approximation?
– Weak inversion– Gain and inversion
Paulo Moreira Transistors 21
“Making Logic”• Logic circuit “ingredients”:
– Power source– Switches– Power gain– Inversion
• Power always comes from some form of external EMF generator.
• NMOS and PMOS transistors:– Can perform the last three
functions– They are the building blocks
of CMOS technologies!
Paulo Moreira Transistors 22
Silicon switches: the NMOS
Paulo Moreira Transistors 23
Silicon switches: the NMOS
Above silicon:• Thin oxide (SiO2) under the gate areas;• Thick oxide everywhere else;
Paulo Moreira Transistors 24
Silicon switches: the PMOS
Paulo Moreira Transistors 25
MOSFET equations• Cut-off region
• Linear region
• Saturation
• Oxide capacitance
• Process “transconductance”
Ids Vgs VT= − <0 0 for
( ) ( )Ids CoxW
LVgs VT Vds
Vds Vds Vds Vgs VT= ⋅ ⋅ ⋅ − ⋅ − ⋅ + ⋅ < < −
µ λ2
21 0 for
( ) ( )IdsCox W
LVgs VT Vds Vds Vgs VT=
⋅⋅ ⋅ − ⋅ + ⋅ > −
µλ
2
21 for
( )Coxox
tox=
ε F / m2
( )µµ ε
⋅ =⋅
Coxox
tox A / V2
0.24µm process
tox = 5nm (~10 atomic layers)
Cox = 5.6fF/µm2
Paulo Moreira Transistors 26
MOS output characteristics• Linear region:
Vds<Vgs-VT
– Voltage controlled resistor
• Saturation region:Vds>Vgs-VT
– Voltage controlled current source
• Curves deviate from the ideal current source behavior due to:– Channel modulation
effects
Paulo Moreira Transistors 27
MOS output characteristicsL = 240nm, W = 480nm
0
50
100
150
200
250
0 0.5 1 1.5 2 2.5Vds [V]
Ids
[uA
]
Vgs = 0.7V (< Vt)Vgs = 1.3VVgs = 1.9VVgs = 2.5V
Paulo Moreira Transistors 28
MOS output characteristicsL = 24um, W = 48um
0
50
100
150
200
250
300
350
400
0 0.5 1 1.5 2 2.5
Vds [V]
Ids
[uA
]
Vgs = 0.7V (<Vt)Vgs = 1.3VVgs = 1.9VVgs = 2.5V
Paulo Moreira Transistors 29
Bulk effect• The threshold depends on:
– Gate oxide thickness– Doping levels– Source-to-bulk voltage
• When the semiconductor surface inverts to n-type the channel is in “strong inversion”
• Vsb = 0 ⇒ strong inversion for:– surface potential > -2φF
• Vsb > 0 ⇒ strong inversion for:– surface potential > -2φF + Vsb
n+ n+p+
V>0 V>VT0
n+ n+p+
V=0 V=VT0
Paulo Moreira Transistors 30
Bulk effect
0
100
200
300
400
500
600
0 0.5 1 1.5 2 2.5
Vgs [V]
Ids
[uA
]
L = 24um, W = 48um, Vbs = 1
L = 24um, W = 48um, Vbs = -1V
W = 24µm
L = 48µm
Vsb = 0V
Vsb = 1 V
Paulo Moreira Transistors 31
Mobility
( )µµ ε
⋅ =⋅
Coxox
tox A / V2
The current driving capabilitycan be improved by using materialswith higher electron mobility
Paulo Moreira Transistors 32
Is the quadratic law valid?
Ids - Vgs (Vds = 2.5V, Vbs = 0V)
0
100
200
300
400
500
600
0 0.5 1 1.5 2 2.5
Vgs [V]
Ids
[uA
]
L = 24um, W = 48um
L = 2.4um, W = 4.8um
L = 240nm, W = 480nm
Quadratic “law” valid for long channel devices only!
Paulo Moreira Transistors 33
Weak inversion• Is Id=0 when Vgs<VT?• For Vgs<VT the drain current
depends exponentially on Vgs
• In weak inversion and saturation (Vds > ~150mV):
where
• Used in very low power designs
• Slow operation
I WL
I ed do
qV
n k Tgs
≅ ⋅ ⋅⋅
⋅ ⋅
TknVq
do
T
eI ⋅⋅⋅
−=
Paulo Moreira Transistors 34
Gain & Inversion• Gain:
– Signal regeneration at every logic operation
– “Static” flip-flops– “Static” RW memory cells
• Inversion:– Intrinsic to the common-
source configuration
• The gain cell load can be:– Resistor– Current source– Another gain device
(PMOS)
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