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14 May 2009 Department of Computer Science, University of Potsdam, Germany

1

SS2009

Introduction to Hardware design and VHDL

Kevin Cheng, Felix Mühlbauer and Philipp Mahr

University of Potsdam, Germany

14 May 2009 Department of Computer Science, University of Potsdam, Germany

2

generate

begin

  <label>: for <name> in <range> generate

      <deklaration, statement, ...>

    end generate;

  <label>: if <condition> generate

      <deklaration, statement, ...>

    end generate;

end architecture example;

14 May 2009 Department of Computer Science, University of Potsdam, Germany

3

MSB / LSB

architecture behaviour of example is

  signal down : std_logic_vector(7 downto 0);

  signal up : std_logic_vector(0 to 7);

begin

  up <= "11110000";

  down <= up;

  down(7) = ?

end architecture example;

14 May 2009 Department of Computer Science, University of Potsdam, Germany

4

ZahlenkonvertierungenSynopsys/Viewlogic

package std_logic_arith is

type UNSIGNED is array (NATURAL range <>) of STD_LOGIC;type SIGNED is array (NATURAL range <>) of STD_LOGIC;

function CONV_INTEGER(ARG: INTEGER) return INTEGER;function CONV_INTEGER(ARG: UNSIGNED) return INTEGER;function CONV_INTEGER(ARG: SIGNED) return INTEGER;

function CONV_UNSIGNED(ARG: INTEGER; SIZE: INTEGER) return UNSIGNED;function CONV_UNSIGNED(ARG: UNSIGNED; SIZE: INTEGER) return UNSIGNED;function CONV_UNSIGNED(ARG: SIGNED; SIZE: INTEGER) return UNSIGNED;

function CONV_SIGNED(ARG: INTEGER; SIZE: INTEGER) return SIGNED;function CONV_SIGNED(ARG: UNSIGNED; SIZE: INTEGER) return SIGNED;function CONV_SIGNED(ARG: SIGNED; SIZE: INTEGER) return SIGNED;

function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR;function CONV_STD_LOGIC_VECTOR(ARG: UNSIGNED; SIZE: INTEGER) return STD_LOGIC_VECTOR;function CONV_STD_LOGIC_VECTOR(ARG: SIGNED; SIZE: INTEGER) return STD_LOGIC_VECTOR;...

end std_logic_arith;

14 May 2009 Department of Computer Science, University of Potsdam, Germany

5

ZahlenkonvertierungenSynopsys/Viewlogic

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

...

architecture behaviour of example is

  signal slv : std_logic_vector(3 downto 0);

  signal x, int : integer range ­16 to 15;

  signal uint : natural range 0 to 15;

begin

  x <= ­2;

  slv <= conv_std_logic_vector(x, slv'length);

  uint <= conv_integer(unsigned(slv));

  int <= conv_integer(signed(slv));

end architecture example;

14 May 2009 Department of Computer Science, University of Potsdam, Germany

6

ZahlenkonvertierungenIEEE 1076.3 numeric_std

package numeric_std is

type UNSIGNED is array (NATURAL range <>) of STD_LOGIC;type SIGNED is array (NATURAL range <>) of STD_LOGIC;

function TO_INTEGER (ARG: UNSIGNED) return NATURAL;function TO_INTEGER (ARG: SIGNED) return INTEGER;function TO_UNSIGNED (ARG, SIZE: NATURAL) return UNSIGNED;function TO_SIGNED (ARG: INTEGER; SIZE: NATURAL) return SIGNED;

...

end numeric_std;

14 May 2009 Department of Computer Science, University of Potsdam, Germany

7

ZahlenkonvertierungenIEEE 1076.3 numeric_std

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

...

architecture behaviour of example is

  signal slv : std_logic_vector(3 downto 0);

  signal int : integer range ­16 to 15 := ­2;

  signal sig : signed(3 downto 0);

begin

  sig <= to_signed(int, slv'length);

  slv <= std_logic_vector(sig);

  int <= to_integer(sig);

  int <= to_integer(signed(slv));

end architecture example;

14 May 2009 Department of Computer Science, University of Potsdam, Germany

8

Schnittstelle

entity ports_example is

  port (

    input : in std_logic;

    output : out std_logic;

    bus : inout std_logic;

    buffered_output1 : buffer std_logic;   ­­ don't use it

    buffered_output2 : out std_logic );    ­­ alternative

end portsexample;

architecture behaviour of ports_example is

  signal buffered_output2_i : std_logic;

begin

  buffered_output2 <= buffered_output2_i;

  <use buffered_output2_i for read and write access>

end architecture behaviour;

14 May 2009 Department of Computer Science, University of Potsdam, Germany

9

with select / when else

architecture behaviour of coder is  ...begin

  with X select                    ­­ encoder example  Y <= "00" when X = "0001",       "01" when X = "0010",       "10" when X = "0100",       "11" when others;

  Z <= "0001" when X = "00" else   ­­ decoder example       "0010" when X = "01" else       "0100" when X = "10" else       "1000";

end behaviour;

14 May 2009 Department of Computer Science, University of Potsdam, Germany

10

Latch

entity RSLatch is  port ( R, S : in std_logic;         Y : out : std_logic );end RSLatch;

architecture behaviour of RSLatch issignal Q : std_logic;begin  process (R, S)  begin    if R = '1' and S = '0' then      Q <= '0';    elsif R = '0' and S = '1' then      Q <= '1';    elsif R = '1' and S = '1' then   ­­ for simulation only !!!      Q <= 'X';    end if;  end process;  Y <= Q;end behaviour;

14 May 2009 Department of Computer Science, University of Potsdam, Germany

11

Synchrone Prozesse

clk : std_logic;...

process (clk)  ­­ often usedbegin  if clk'event and clk = '1' then    ...  end if;end process;

process (clk)  ­­ simpler and more complete begin  if rising_edge(clk) then    ...  end if;end process;

14 May 2009 Department of Computer Science, University of Potsdam, Germany

12

Reset in synchronen Prozessen

ASYNC: process (rst, clk)  ­­ asynchronous reset

begin

  if rst = '1' then

    ...

  elsif rising_edge(clk) then

    ...

  end if;

end process;

14 May 2009 Department of Computer Science, University of Potsdam, Germany

13

Reset in synchronen Prozessen

SYNC: process (rst, clk)  ­­ synchronous reset

begin

  if rising_edge(clk) then

    if rst = '1' then

      ...

    else

      ...

    end if;

  end if;

end process;

14 May 2009 Department of Computer Science, University of Potsdam, Germany

14

Beispiel: Zähler

entity counter is  port( clk, rst : in std_logic;        Q : out std_logic_vector(3 downto 0) );end counter;

architecture behaviour of counter is  signal Q_i : std_logic_vector(3 downto 0);begin  process (clk, rst)  begin    if (rst = '1') then      Q_i <= (others <= '0');    elsif (rising_edge(clk)) then      Q_i <= Q_i + 1;    end if;  end process;  Q <= Q_i;end behaviour;

14 May 2009 Department of Computer Science, University of Potsdam, Germany

15

signal vs variable

signal innerhalb von Prozessen gilt die letzte

Zuweisung variable

nur in Prozessen definierbar (Gültigkeitsbereich)

innerhalb von Prozessen erfolgt eine Zuweisung sofort (kombinatorische Logik)

14 May 2009 Department of Computer Science, University of Potsdam, Germany

16

ISE template library

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