interrupt driven i/o. mips risc exception mechanism the processor operates in the processor operates...

Interrupt driven Interrupt driven I/OI/O

MIPS RISC Exception MIPS RISC Exception MechanismMechanism

The processor operates inThe processor operates in user modeuser mode kernel modekernel mode

Access to additional set of registers and to Access to additional set of registers and to user-mode restricted memory space user-mode restricted memory space available when the processor operates in available when the processor operates in kernel modekernel mode..

The MIPS RISC architecture includes the The MIPS RISC architecture includes the notion of notion of co-processorsco-processors. If the floating point . If the floating point co-processor is not present it can be co-processor is not present it can be emulated by a software. emulated by a software.

Co-processorsCo-processors

The co-processor C1 execute floating point The co-processor C1 execute floating point instructions and contain floating point registers. instructions and contain floating point registers.

If the coprocessor C1 does not exist and an If the coprocessor C1 does not exist and an instruction specifies a floating point register, a instruction specifies a floating point register, a trap occurs. The exception handler can identify trap occurs. The exception handler can identify the operation specified and may invoke software the operation specified and may invoke software routines to achieve the effect of the specified routines to achieve the effect of the specified operation.operation.

The co-processor C0 is always present and The co-processor C0 is always present and contains registers useful for handling contains registers useful for handling exceptions but is not accessible in user mode. exceptions but is not accessible in user mode. C0 includes the status register, cause register, C0 includes the status register, cause register, BadVaddr, and EPC (exception program BadVaddr, and EPC (exception program counter).counter).

Co-processor 0Co-processor 0

BadVaddr 8 memory address at which addressexception occurred

Status 12 interrupt mask and enable bitsCause 13 exception type and pending interruptsEPC 14 address of instruction that caused

exception

name number information

Cause RegisterCause Register

The cause register contains information about The cause register contains information about pending interrupts and the kinds of exception pending interrupts and the kinds of exception that occurs.that occurs.

The contents of the cause register can be copied The contents of the cause register can be copied into an ordinary register and have the individual into an ordinary register and have the individual bits tested to determine what caused an bits tested to determine what caused an exception to occur.exception to occur.

mfc0 $26, $13mfc0 $26, $13 The above instruction moves data from The above instruction moves data from coprocessor 0coprocessor 0 registerregister $13$13(cause register) to (cause register) to general purpose register general purpose register $26$26

Cause RegisterCause Register

0126815

exception codepending interrupts

exception code meaning0 interrupt4 load from illegal address5 store to illegal address6 bus error on instruction fetch7 bus error on data reference12 arithmetic overflow15 floating point exception

Status RegisterStatus Register

The status register contains The status register contains information about the status of information about the status of features of the computer that can be features of the computer that can be set by the processor while in kernel set by the processor while in kernel modemode

indicates whethercurrent status is kernel or user

indicates whether theprocessor was in kernel oruser mode when the lastexception occurred

Status RegisterStatus Register

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Mod

e

En

able

Mod

e

En

able

Mod

e

En

able

Mode: 1=user, 0=kernelEnable: 1=on, 0=off

Old Prev Cur

EPC (exception program EPC (exception program counter)counter)

Contains the address of the instruction that Contains the address of the instruction that was executing when the exception was was executing when the exception was generated.generated.

Control can be made to return to this Control can be made to return to this location to continue the program.location to continue the program.

The contents of EPC can be transferred to a The contents of EPC can be transferred to a general register via the following general register via the following instructioninstruction

mfc0 Rmfc0 Rtt, $14, $14

Exception HandlerException Handler

The MIPS R32 architecture fixes the starting address of The MIPS R32 architecture fixes the starting address of the exception handler to the exception handler to 0x8000 01800x8000 0180..

A jump table consists of a list of procedure addresses to A jump table consists of a list of procedure addresses to be called to deal with the various exception conditions.be called to deal with the various exception conditions.

In an interrupt, the PC had already been incremented In an interrupt, the PC had already been incremented and EPC would contain the correct return address.and EPC would contain the correct return address.

In a In a syscallsyscall, the EPC contains the address of the , the EPC contains the address of the syscall itself, thus the exception handler syscall itself, thus the exception handler must first must first incrementincrement the return address by one before the return. the return address by one before the return.

Handling an exceptionHandling an exception

An exception has occurred. What An exception has occurred. What happens?happens? The hardware The hardware

copies PC into EPC ($14 on cop0) and puts copies PC into EPC ($14 on cop0) and puts correct code into Cause Reg ($13 on cop0)correct code into Cause Reg ($13 on cop0)

Sets PC to 0x80000180, process Sets PC to 0x80000180, process enters enters kernel modekernel mode

Exception handler (software)Exception handler (software) Checks cause register (bits 5 to 2 of $13 in cp0)Checks cause register (bits 5 to 2 of $13 in cp0) jumps to exception service routine for the jumps to exception service routine for the

current exceptioncurrent exception

OS IssuesOS Issues

When an interrupt is serviced the processor must be When an interrupt is serviced the processor must be able to execute without being interrupted. It must able to execute without being interrupted. It must have the capability of temporarily disabling the have the capability of temporarily disabling the interrupt atomically.interrupt atomically.

If an interrupt occurs while an interrupt service is If an interrupt occurs while an interrupt service is ongoing, it is simply deferred and considered a ongoing, it is simply deferred and considered a pending interrupt. It is serviced after the current pending interrupt. It is serviced after the current request terminates.request terminates.

The MIPS RISC architecture does not allow user The MIPS RISC architecture does not allow user programs to access beyond programs to access beyond 0x8000 00000x8000 0000 (the upper (the upper half of the memory). The exception handler is in this half of the memory). The exception handler is in this part of memory and only executed in kernel mode.part of memory and only executed in kernel mode.

OS IssuesOS Issues

Changing the mode back to the Changing the mode back to the mode before the exception occurs is mode before the exception occurs is accomplished via the instruction accomplished via the instruction ereteret

Old Old Previous Previous Current Current The mode information is stored in The mode information is stored in

the Status Register and can only be the Status Register and can only be written in the kernel mode. It can be written in the kernel mode. It can be read in user mode.read in user mode.

OS IssuesOS Issues

Enabling and disabling of interrupts Enabling and disabling of interrupts can be done either by applying an can be done either by applying an interrupt mask (IPM) to bits 10-15, interrupt mask (IPM) to bits 10-15, or the enable bit of the Status or the enable bit of the Status Register.Register.

The execution of The execution of ereteret enables enables interruptsinterrupts

OS IssuesOS Issues

A reentrant exception handler is written A reentrant exception handler is written such that it is itself interruptible.such that it is itself interruptible.

Interrupts and traps are assigned Interrupts and traps are assigned priorities.priorities.

A check is made for pending interrupt A check is made for pending interrupt requests after every instruction.requests after every instruction.

If there is a pending interrupt request, the If there is a pending interrupt request, the priority is checked. If it has a higher priority is checked. If it has a higher priority than the currently running code, priority than the currently running code, it serviced first, otherwise it is ignored.it serviced first, otherwise it is ignored.

Enabling interruptsEnabling interrupts

By default, interrupts are disabled in SPIMBy default, interrupts are disabled in SPIM To use respond to interrupts, a program To use respond to interrupts, a program

mustmust Enable interruptsEnable interrupts

Status registerStatus register Enable the interrupt for the specific deviceEnable the interrupt for the specific device

Status registerStatus register Instruction the device controller to cause Instruction the device controller to cause

interruptsinterrupts Device control memory mapped addressDevice control memory mapped address

Exceptions come in two varietiesExceptions come in two varieties Interrupts are generated by hardwareInterrupts are generated by hardware

I/O deviceI/O device ClockClock Power downPower down

Traps are generated by code executionTraps are generated by code execution Division by zeroDivision by zero Illegal memory addressIllegal memory address System call System call

Software: Interrupt Software: Interrupt Driven I/ODriven I/O

Interrupt driven I/O Interrupt driven I/O structurestructure

Our programs have all Our programs have all run in kernel mode onlyrun in kernel mode only

Code to service an Code to service an interrupt must be called interrupt must be called from location from location 0x80001800x8000180

We must return to the We must return to the address at which the address at which the interrupt occurredinterrupt occurred

kernel

0xffffffff

0x800000800x80000000

0x10000000

0x004000000x00000000

stack

code

Interrupt driven I/O Interrupt driven I/O structurestructure

A queue is needed for both input and outputA queue is needed for both input and output InputInput

Characters are added when a keyboard interrupt occursCharacters are added when a keyboard interrupt occurs Characters are removed when the input function is calledCharacters are removed when the input function is called

Output Output Characters are removed when a display interrupt occursCharacters are removed when a display interrupt occurs Characters are added when a keyboard interrupt occursCharacters are added when a keyboard interrupt occurs

EchoingEchoing Characters are added when the output function is calledCharacters are added when the output function is called

The output function must initiate the first display handler callThe output function must initiate the first display handler call Thereafter, interrupts occur when the display becomes readyThereafter, interrupts occur when the display becomes ready

Interrupt driven I/O Interrupt driven I/O structurestructure

input

output

echo

Userdata

input function(syscall 8)

output function(syscall 4)

Protecting the buffersProtecting the buffers

The input and output buffers may be modified The input and output buffers may be modified in response to an interruptin response to an interrupt

This could occur while the CPU is in the This could occur while the CPU is in the middle of executing user code which reads middle of executing user code which reads from the input buffer or writes to the output from the input buffer or writes to the output bufferbuffer

To prevent this destructive concurrent To prevent this destructive concurrent access, we must disable interrupt while access, we must disable interrupt while accessing the buffersaccessing the buffers Explicitly Explicitly andand status with 0xfffffffe status with 0xfffffffe Implement I/O functions as system callsImplement I/O functions as system calls