interfacing a microprocessor chip with memory chips and io...

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Interfacing a Microprocessor Chip with Memory Chips and

IO Controller Chips

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• Two aspects:1. Physical connection between devices• Connecting two or more devices through a channel

– Wires– Wireless

• Adapting voltage and current levels– Logic 0 → 0V; Logic 1 → 5V– Logic 0 → 5V; Logic 1 → 0V– Logic 0 → 15V, Logic 1 → -15V

2. Procedural connection between devices• Software to implement a set of rules that control and

communicate with devices for a particular function.

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• Set of rules (the Protocol) used to communicate between two or more devices

• Microprocessor Control of RAM/ROM Memory– RAM: read/write operations– ROM: read only– Supply address and control; then data may be accessed

• Microprocessor Control of FLASH Memory– Read/write operations more complex• higher voltages/currents• Required delay between accesses much longer than RAM

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• Microprocessor Control of I/O Controllers of Devices– Device dependent/specific– Control, Status, and Data Registers• Control registers for configuring operation of device• Status register for obtaining status for the device• Data register fro writing to or reading from the device

– General Protocol• Write to control registers to configure desired operation• Read status register to obtain operation status• Read data register, or write to data register

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MEMORY

IO CONTROLLERS

PERIPHERAL DEVICES

MIC

ROCO

MPU

TER

MICROPROCESSOR– Bus Master– Controls the Slaves• Procedural Interface– ABUS, CBUS Signals

PCIASCIA

MIC

ROCO

NTR

OLL

ER (S

ingl

e Ch

ip)

USB

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CHIP SELECT

PCIASCIA

USB

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6800 Micro-

processorPIN Diagram

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Example 15.4: RAM: 128 words by 8-bit

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Example 15.1: Physical Connection to μP and Internal Logic

A0A1A2A3A4A5A6

A0A1A2A3A4A5A6

128x8

D1…D7

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EXAMPLE 15.4: ROM Memory

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SYNCHRONOUS BUS CONTROL

φ1

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Latching into μPregister.

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Latching into memory.

To Memory

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ASYNCHRONOUS BUS CONTROL