interconnects in 50-100 ghz integrated circuits m.j.w rodwell, s. krishnan, m. urteaga, z. griffith,...

Interconnects in 50-100 GHz Integrated Circuits

M.J.W Rodwell, S. Krishnan, M. Urteaga, Z. Griffith, M. Dahlström, Y. Wei, D. Scott,

N. Parthasarathy, Y-M Kim, S. Lee

University of California, Santa Barbara

urteaga@ece.ucsb.edu 805-893-8044, 805-893-3262 fax

Outline

• Introduction

• Transmission line characterization for on-wafer device measurements

• Monolithic millimeter-wave ICs

• Mixed-signal medium-scale ICs

Apply scaling approaches of Si-devices with material advantages of III-V systems to realise ultra-fast transistors

Previous research: Transferred-substrate HBT technology

Current research: Highly scaled mesa-HBT technology

Why is the wiring environment important to us?

Accurate device measurements require controlled ZO

Monolithic Millimeter-wave IC design

Ultra-high frequency mixed-signal IC design

High-speed InP Heterojunction Bipolar Transistors

• Substrate transfer process permits simultaneous scaling of emitter-base and collector-base junction widths

• Maximum frequency of oscillation

• Record values of measured transistor power gain at 110 GHz, record values of extrapolated fmax (> 1 THz)

• Process provides mirostrip wiring environment with thin (5 m) low loss

BCB dielectric (r= 2.7)

cbbbCRff 8/max

Transferred-substrate HBTs

0

5

10

15

20

25

30

10 100 1000

Ga

ins

, dB

Frequency,GHz

H21

U

MSG

Vce = 1.2 V Ic=6 mA

0.4 m x 6 m emitter, 0.7 m x 9 m collector,

• Highly Carbon-doped InGaAs base enables low base contact resistance, short Ohmic transfer length Lt ~ 0.1 m

• Allows aggressive scaling of base-mesa width in traditional mesa-HBT structure

• Record fmax (> 400 GHz) for mesa-HBT device

• Incorporate coplanar waveguide (CPW) or microstrip wiring environment with backend processing

Ultra Wideband mesa-HBTs Mattias Dahlstrom (UCSB) Amy Liu (IQE)

UCSB / IQE

0

5

10

15

20

25

30

1010 1011 1012

Gai

n (

dB

) H

21,

U

frequency (GHz)

ft=282 GHz

fmax

=480 GHz

On-wafer Device Measurements

• Commercial vector network analyzers available to 350 GHz

• UCSB capabilities: DC-50 GHz, 75-110 GHz, 140-220 GHz

• Accurate S-parameter measurements require accurate on-wafer calibration

• Line-Reflect-Line calibration is preferred for submicron device measurements

High-frequency Device Measurements

UCSB 140-220 GHz VNA Measurement Set-up

0

5

10

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35

1 10 100Frequency, GHz

MSG

h21

Mason'sGain, U

• Submicron HBTs have very low Ccb (< 5 fF)

• Characterization requires accurate measure of very small S12

• Standard 12-term VNA calibrations do not correct S12 background error due to probe-to-probe coupling

SolutionEmbed transistors in sufficient length of on-wafer transmission line to reduce coupling

Line-Reflect-Line calibration to place measurement reference planes at device terminals

On-wafer Device Measurements

Transistor Embedded in LRL Test Structure

230 m 230 m

Corrupted 75-110 GHz measurements due toexcessive probe-to-probe coupling

• LRL does not require accurate characterization of Open or Short calibration standards

• LRL does require accurate characterization of transmission line characteristic impedance

• LRL does require single-mode propagation environment

Transferred-substrate process provides ideal wiring environment for on-wafer device measurements

Mesa-HBT technology presents challenges to realizing single-mode environment to 220 GHz

Line-Reflect-Line Calibration

• Substrate-transfer provides well-modeled microstrip wiring environment with thin dielectric (5 m)

• Conductors must be narrow for ZO = 50 : high resisistive losses

• LRL calibration is referenced to Line standard ZO

• Must correct for complex ZO, particularly at low frequencies

Transferred-substrate HBT Measurements

Transistor S-parameters with (red) and without (blue) complex ZO correction

CG

LRZO

j

jfreq (6.000GHz to 40.00GHz)

S11 S22

freq (75.00GHz to 110.0GHz)

• CPW wiring is incorporated with minimal backend processing

•Must avoid coupling to parasitic modes

Mesa-HBT Measurements

Mesa-HBT measurement corrupted from CPW excitation of parasitic modes in 75-110 GHz band

S11

S22

+V +V +V

0V

-V 0V +V

0V

kz

Microstrip mode Slot mode

Substrate modes

Monolithic mm-Wave ICs

MIMICs have applications in

• Point-to-point mm-wave links (60 GHz, 90 GHz…)

• Automotive radar (46 GHz, 77 GHz…)

• Planetary exploration, atmospheric sensing (140-220 GHz)

Transmission line tuning networks require low-loss interconnects with precisely controlled impedance and velocity

Transmission Line Options

• Microstrip with semiconductor substrate dielectric

• Coplanar Waveguide (CPW)

• Thin-film dielectric Microstrip

Monolithic mm-Wave Integrated Circuits

Microstrip wiring with semiconductor dielectric is extensively used in MIMICs

Requires thinning of substrate thickness to minimize through-wafer via inductance Via inductance 12 pH for

100 m substrate, j7.5@ 100 GHz

Substrate mode couplingSynchronous coupling into TM0 mode at

“Handbook of Microwave Integrated Circuits”

R. Hoffman, Artech House, 1987

Microstrip Wiring with Semiconductor Dielectric

kz

1

106min,0,

r

TMSh

f

Frequently used for high frequency MIMIC designs

Substrate must still be thinned to avoid coupling to substrate modes, h < 0.12d .

Reference: Riaziat, M. et al. “ Propagation Modes and Dispersion Characteristics of Coplanar Waveguide” IEEE MTT, March 1990 .

Through-wafer vias or multiple-wire bonds are necessary in packaged ICs to prevent parallel plate waveguide modes for L > d /2

CPW Wiring

L

Wiring and Ground planes on IC top surface separated by a few microns of thin dielectric

Planarising spin-on-polymers offer low dielectric constant, low microwave loss

Low ground access inductance, low dispersion, low mode coupling, due to thin substrate thickness

… but thin dielectrics result in narrow conductor widths and high resistive losses

Thin-dielectric Microstrip Wiring

Low r

S.I. Substrate

Via Via

Ground Plane

Cross-section of Transferred-substrate HBTThin-dielectric Wiring Environment

freq (140.0GHz to 220.0GHz)

Properties

• 5 m BCB substrate r = 2.7

• 50 line W = 12.5 m, Loss 1 dB/mm @100 GHz

• 4m x 4m vias allows dense integration

Excellent agreement between measurement and CAD simulations of microstrip matching networks seen to 200 GHz

Passive Element Matching Networkfor Single-stage Amplifier

S21

S22

S11

Red- SimulationBlue- Measurement

Transferred-substrate Microstrip Wiring

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-2

0

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6

8

140 150 160 170 180 190 200 210 220

dB

frequency, GHz

-10

-5

0

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15

140 150 160 170 180 190 200 210 220

dB

frequency (GHz)

IC Results: 140-220 GHz Small-Signal Amplifiers

Three-transistor amplifier8.5 dB gain @ 195 GHz

Single-transistor amplifier6.3 dB gain @ 175 GHz

Cell Dimensions: 1.6mm x 0.59 mm

Cell Dimensions: 0.69mm x 0.35 mm

IC Results: W-band Power Amplifiers UCSBYun Wei

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Po

ut,

dB

m GT , d

B

Pin, dBm

GT Pout

Common-base PA

Psat=16 dBm @ 85 GHz

P1dB=14.5 dBm

GT=8.5 dB

Total Emitter Area AE = 128 m2

Cell Dimensions: 0.5mm x 0.4 mm

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15

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Po

ut, d

Bm G

T , dB

Pin, dBm

GT Pout

Cascode PA

Psat=12.5 dBm @ 90 GHz

P1dB=9.5 dBm

GT=8.2 dB

Total Emitter Area AE = 64 m2

Cell Dimensions: 0.5mm x 0.4 mm

Mixed-Signal ICs

Applications• Long haul fiber optic transmission ICs (40 Gb/s, 80 Gb/s. 160 Gb/s ??)

• Digital radio: ADCs, DACs, etc… > 10 Gb/s sampling rates

Medium scales of integration (1000-10,000 transistors)

Wiring requirements for mixed-signal ICs

• Low common-lead ground-return inductance

• Controlled characteristic impedance for CAD simulation

• Low line-to-line coupling in densely packed ICs

• Low eff for time-delay sensitive circuits

High Frequency Mixed-Signal ICs

CPW for long interconnects onlyUnknown ZO for most wires CAD modeling difficult Implement circuit design techniques to minimize effects

Circuit Cross-talkDensely packed internal wires with large large fringing fieldsExcitation of surface wave or parallel-plate modes couple circuits CAD modeling difficult

Ground InductanceDiscontinuous ground planesWire bonds to package ground~0.3 pH/m inductance Signal distortion, Ground Bounce, Ringing

Problems with top-side CPW Wiring for 100 GHz Digital

Bond wire inductance resonates with through-wafer capacitance at

Peripheral grounding allows parallel plate mode resonanceInP die dimensions must be <0.4mm at 100GHz

…or thin wafer and add Vias

Problems with Coplanar Waveguide Packaged ICs

Lbond/n Csub

nLC bondsub

o/

1

Via Inductance too big12 pH for 100 um substratej7.5@ 100 GHz must thin substrate

Via spacing too large~100 um for 100 um substrate not dense enough for digital must thin substrate

Line Spacing too largefringing fields line couplingW> 3h typically required not dense enough for digital must thin substrate

Problems with Substrate Microstrip Wiring for 100 GHz Digital

Thin semiconductor substrates: breakage, lapping to 35 um ?!Best solution: microstrip on spin-on polymer dielectrics.

Low via inductance0.6 pH for 5 m substratej0.4@ 100 GHz

Small Via dimensions4 m x 4 mm; dense integration

Low line-to-line couplingDense integration

Low eff, high wave velocityLow time-of flight delays

Well-controlled ZO

Good for CAD modeling

Top-side Thin-dielectric Microstrip Wiring for 100 GHz digital

Low r

S.I. Substrate

Via Via

Drawbacks• Added process complexity/cost• Capacitive low impedance lines• Lower current carrying capacity with narrow conductors• Substrate and parallel plate modes still present for packaged ICs

Ground Plane

Packaging Thin-dielectric Microstrip Circuits

Thinned wafer with substrate Vias: Kills ground bounce & substrate modesWafer lapped & thinned to 75 umVias to backside ground plane & package ground200 m via spacing suppresses all DC-200 GHz substrate resonant modes

thinned (75 um)semi-insulatingInP substrate

BCB (5 um thick)

plated top-surface ground plane

circuits

plated back-surface ground plane

via

circuits

via

package ground

solder bond

< d /2

IC Results: 87 GHz HBT Master-Slave Latch

Static frequency division to 87 GHz

InP /InGaAs/InP mesa-DHBT Technology

Wiring Process Flow

Two-levels of topside interconnects, NiCr resistors, MIM capacitors

Spin 6 m BCB dielectric

Via etch/planarization etchback to 5 m

Patterned Au electroplating of IC ground planes, and probe pads.

PK Sundararajan, Zach Griffith

-0.2

-0.18

-0.16

-0.14

-0.12

-0.1

-0.08

-0.06

22 22.02 22.04 22.06 22.08 22.1 22.12 22.14

87 GHz input, 43.5 GHz output

Vo

ut (

Vol

ts)

time (nsec)

UCSB

IC photograph before and after plating ground plane

TechnologyInP /InGaAs/InP mesa-DHBT 400 Å base, 2000 Å collector, 9 V BVCEO, 200 GHz ft, 180 GHz fmax2.5 x 105 A/cm2 operationThin-dielectric microstrip wiring

Designsimple 2nd-order gm-C topologycomparator is 87 GHz MSS latchintegration by capacitive loads 3-stage comparator, RTZ gated DAC

Results133 dB (1 Hz) SNR at 74 MHzequivalent to ~8.8 bits at 200 MS/s

UCSBPK Sundararajan, Zach Griffith

975 kHz FFT bin size8 GHz clock rate65.5 MHz signal64:1 oversampling ratio

IC Results: 8 GHz ADC

IC photograph before and after plating ground plane

High performance III-V devices require high performance wiring environments

Accurate on-wafer device measurements require known ZO with single-mode propagation

MIMIC designs require well-modeled wiring with low ground access inductance

Mixed-signal ICs require high-levels of integration and a low eff wiring environment

Wafer thinning is required to avoid substrate and parallel-plate modes in packaged ICs

Conclusions