integrity-driven power and signal network codesign · integrity-driven power and signal network...

Integrity-driven Power and Signal Network Codesign

Jinjun Xiong and Lei HeElectrical Engineering Department

University of California, Los Angeles

Sponsors: Fujitsu, IBM, Intel, LSI, NSF

Agenda

!Motivation!Modeling!GSPR problem formulation

ñ Global Signal and Power co-Routing

!GSPR algorithm!Experiment results!Conclusion

Introduction & Motivation

!DSM era is wire-limitedñ Power distribution networkñ Signal routing

!Conventional physical design flowñ Power network is designed first w/o knowledge of signal

routing

ñ Signal routing is done within the remaining resource budgets

!Problems: design closure suffers!

Introduction & Motivation

! Signal integrity is critical for DSM designñ Increasing capacitive coupling due to closer proximityñ Increasing inductive coupling due to higher frequency

! Shielding has been proven to be effective to improve signal integrityñ Shields are connected to power network through viasñ Twisted bundle layout [Zhang et. al., ICCAD00]ñ Simultaneous shield insertion and net ordering [He et. al., ISPD99 ]

! But, shields also contend for the very scant routing resourcesñ Even harder to complete routing under the remaining resource

budgets in conventional separated design flow! Note: shields are part of the power network

ñ It makes sense to account shields into power networkñ Accurate shield information only known after routing!ñ How can we consider shielding in conventional physical design flow?

Introduction & Motivation

!Power and signal networks co-designñ Unified approach to manage routing resource

!However, the co-design problem has very high complexityñ Computational intensiveñ Methodology issues

!Two possible approaches:ñ Let the power network design be aware of the signal

routingñ Let the signal routing be aware of the power network

design

Introduction & Motivation

!Few have attempted this unified design approachñ Su et. al. DAC 02ñ Saxena et. al. TCAD03

!Adding a feedback loopñ Locally changing power network

topology and sizing power network

ñ Very slow because of the full-chip transient simulation embedded in the loop

ñ Not considered shielding during routing yet.

GlobalRouter

PowerGrid

CongestionMap

Local Power NetRemoval & Sizing

Agenda

!Motivation!Modeling!GSPR problem formulation!GSPR algorithm!Experiment results!Conclusion

Modeling

!Both power and signal integrity are closely related to timing and noise problemsñ Hence, they are generally defined in electrical domainñ To obtain accurate timing/noise info, SPICE/numerical

simulation is requiredï Computation intensive, slow, not-scalable

!Do we really need that kind of accuracy in such a high level design?

!Solutions: employ high abstract level modelsñ Computational efficient, with reasonable accuracyñ ì Wiring rulesî , which transform electrical constraints

into physical layout constraints

Wire Rule #1: Power Pitch Constraint

! Power network is usually designed as a meshñ Power pitch is the separation between two adjacent power nets in

terms of the # of tracks ! Smaller power pitch is very helpful

ñ Better signal integrityï Reduces capacitive couplingï Provides closer current return paths

ñ Reduced power supply noise:ï On-chip power network inductance reduces (Ldi/dt)ï Grid resistance is reduced (IR-drop)

! Balance between pitch size and routing areañ Maximum power pitch model: the pitch size is properly

constrainedñ Not only guarantees power integrity, and but also helps for signal

integrityñ Been used successfully for modern CPU designs [Saxena et. al.]

pitch

Wire Rule #2: Signal Shielding Constraints

! Accurate shielding requirement for signal nets is hard to obtainñ Layout dependentñ Computational infeasible

! Still, at the high level, timing/noise optimization engine might help [Saxena et. al. TCAD]ñ Identify sensitive/critical signals netsñ Shielding according to their criticality w.r.t. other nets

ï S2-nets: require two adjacent shieldsï S1-nets: require one adjacent shieldsï S0-nets: require no adjacent shields

Agenda

!Motivation!Modeling!GSPR problem formulation!GSPR algorithm!Experiment results!Conclusion

GSPR Problem Formulation

!GSPR formulations:ñ Given: a placement solutionñ Synthesize: power network and signal networkñ Satisfy: max power pitch and shielding constraintsñ Such that: the total power network area is minimized

!The total power network area is given by:

area tt

P S∀

=∑

Agenda

!Motivation!Modeling!GSPR problem formulation!GSPR algorithm

ñ Power net estimationñ Multi-level routing frameworkñ Power integrity aware routingñ Power network synthesis and track assignment

!Experiment results!Conclusion

GSPR Algorithm

!Proposed a novel design methodologyñ A simple yet accurate power net estimation

Global RoutingWith Shield Estimation

Power GridSynthesis

TrackAssignment

Timing & NoiseOptimization

Signal ShieldingConstraints

High-level PowerGrid Analysis

Maximum PowerPitch Constraints

GSPR

Power Net Estimation

! Lemma 1: Given a routing region with capacity Ct, in order to satisfy the maximum power pitch constraints, the minimum number of power nets required is given by:

tt

CpP G P

=

10, 510 25

t

t

C PGP

p

= =

= =

Power Net Estimation

! Lemma 2: Given a routing region, in order to satisfy the signal shielding constraints, the minimum number of power nets required is given by:

12 2 2( ) ( 1)

2sit

mS b m b = − + + ⋅

s 2 - n e ts s 1 - n e ts

1 2 24, 2 ( 1)4( 1) (2 1) 1 42

sit

m m b

S

= = =

= − + + × =

Power Net Estimation

! Valid track assignment solution in a routing regionñ Track assignment for both signal nets and power netsñ Satisfies both power pitch and signal shielding constraints

! Theorem1: For a given routing region with two edge power nets, then among all valid track assignment solutions, the minimum power net number is given as follows:

12 2 2

2

2

1

( ) ( 1)2

1

2

t

t t

t

m b m b

p mS p m

m

p

− + + ⋅ + += +

1

2 1

2 1

2 1

2 1

2 ( 1)

1, 2 ( 1)1, 2 ( 1)0, 2

0, 2

t

t

t

t

t

m p

b m pb m pb m p

b m p

≥ +

= ≥ += < += ≥

= <

Agenda

!Motivation!Modeling!GSPR problem formulation!GSPR algorithm

ñ Power net estimationñ Multi-level routing frameworkñ Power integrity aware routingñ Power network synthesis and track assignment

!Experiment results!Conclusion

Multilevel Routing Framework

! Multi-grid/multi-level methodñ Originally used to accelerate the solution of partial differential

equations.ñ Later used in other fields

ï Image processing, combinatorial optimization,control theory, statistical mechanics, quantum electrodynamics, and linear algebra.

! Applications in VLSI CADñ Partitioning: hMETIS, HPMñ Placement: mPLñ Routing: MRS

ï Conventional Routing = GR + Detailed Routing (Two-level)

Multilevel Routing Framework

! Hierarchical routingñ Address conventional

routingís scalability problem

ñ Decide routing solution from the coarsest level to the finest level

ñ However, because local netsí effects are not considered, earlier decision might be wrong

Finest Routing Graph

Refinement

Coarsest Routing Graph

Gk

G0

G1

Multilevel Routing Framework

Courtesy cong et. al. ICCAD01

Finest routing graph

G1

ïCoarsening

G0

Refinement

Coarsest routing graph with local congestion information

Gk

G0

G1

! Multilevel routing:ñ Accurately account for the local nets effects by introducing an extra

coarsening procedure

Finest routing graph

Initial Routing

Multilevel Routing Framework

!Key to multilevel routing: how to obtain the local netsí congestion informationñ Net count based approximation [Cong 01, 02]: Too rough!ñ Exact routing resource estimation model via detailed

routing [Chang 02, 03]: too restrictive

!We propose: ñ Accurate routing resource estimation model via global

routing: efficient yet accurate

Agenda

!Motivation!Modeling!GSPR problem formulation!GSPR algorithm

ñ Power net estimationñ Multi-level routing frameworkñ Power integrity aware routingñ Power network synthesis and track assignment

!Experiment results!Conclusion

Power integrity aware routing! Coarsening:

ñ Fine routing tiles are recursively merged into coarser tilesñ Routing congestion computation takes the power net estimation into

consideration

ñ Estimate routing resource by a quick pattern routing of s2-nets and s1-nets: ï L-shaped and Z-shaped onlyï Path cost function

! Uncoarsening:ñ Rout local nets just appeared in current levelñ Refine failed nets in previous level

! Rip-up and rerouteñ Further improves routing solution

c o s ( ) ( )e

e t t t tt P

t P G S Cα∈

= + −∑

e t t tC G S C= + −

Agenda

!Motivation!Modeling!GSPR problem formulation!GSPR algorithm

ñ Power net estimationñ Multi-level routing frameworkñ Power integrity aware routingñ Power network synthesis and track assignment

!Experiment results!Conclusion

Power network synthesis and track assignment

! Synthesize a global power network ñ Such that there are two power nets along each routing tilesñ Satisfy the precondition of Theorem 1ñ Decouple the requirements of power nets between different

routing tiles

! Synthesize track assignment solution within each routing region

Agenda

!Motivation!Modeling!GSPR problem formulation!GSPR algorithm

ñ Power net estimationñ Multi-level routing frameworkñ Power integrity aware routingñ Power network synthesis and track assignment

!Experiment results!Conclusion

Experiment

! ISPDí98 IBM benchmark suite [Alpert et al. ]employedñ Assume 10% s2-nets and 10% s1-netsñ Maximum power pitch constraints = 10

256 * 6426900072760IBM10

256 * 6418787259454IBM09

192 * 6419818049228IBM08

192 * 6424436946885IBM07

128 * 6412439934935IBM06

128 * 6412443829647IBM05

Grid# Pin# NetCKTs

Comparison Algorithms

! Three step approach: 1. Route s2-nets and s1-nets along with their shielding requirements2. Synthesize power network3. Route remaining netsñ Similar to Saxena et. al. TCAD 03

! Key differences between GSPR and the three-step algorithmñ GSPR first route signal nets with power nets estimation and

minimizationñ GSPR then synthesize power network with simultaneous track

assignment of both signal nets and power nets

Figure-of-merits

!Figure-of-merits:ñ Power network areañ Max density ñ Total # of routing bends (vias)ñ Total # of routing edges (length)ñ Runtime

max max{ }

t tt

t

tt

G SDenC

Den Den∀

+=

=# E d g e = 4

# B e n d = 2area tt

P S∀

=∑

Experiment results

0.81198729 (-17.2%)0.79240002IBM10

0.92147738 (-22.4%)0.82190499IBM09

0.94122825 (-20.3%)0.9154048IBM08

0.92116095 (-21.5%)0.86147832IBM07

0.8892965 (-17.5%)0.82112642IBM06

0.82167198 (-12.8%)0.83191661IBM05

maxDenPower NetmaxDenPower Net

GSPR Alg.Three-step Alg.CKTs

! Experiments are based upon solutions that satisfy both power pitch and signal shielding constraints.

! Because all maxDen are less than 1, no routing overflow.! Because GSPR estimates power nets while routing, it can use routing resource

more sensible than three-step alg.ñ On average, 19.4% power network area reduction is observed.

Experiment results

305568 (-6.5%)

241648 (-6.3%)

214366 (-6.5%)

202349 (-6.6%)

163990 (-6.1%)

381037 (-6.9%)

BendGSPR Alg.Three-step Alg.CKTs

255.7

197.3

207.9

173.2

177.1

451.6

Time

326648

257902

229288

216602

174652

409305

Bend TimeEdgeEdge

150.6597621 (-1.7%)607843IBM10

115.8427519 (-2.4%)437863IBM09

123.3421483 (-1.4%)427669IBM08

102.9378045 (-1.8%)385113IBM07

102.8289980 (-1.8%)295150IBM06

246.7646994 (-1.0%)653752IBM05

! More power network area means more restrictive routing environmentñ More routing bends: 6.7% savings for GSPRñ More routing lengths: 1.7% savings for GSPR

! About 2X speed up for GSPR over three step alg.ñ Because of multi-level routing framework

Conclusion & Future Work

! Conclusionñ Presented a novel one-pass design methodology for power network

and signal network co-designñ GSPR on average

ï Save power network area by 19.4%ï Reduce routing bends by 6.7%ï Reduce routing detour by 1.7%ï 2X speedup over three-step alg.

ñ Manuscript to appear in DATE 2004

! Future work:ñ Develop new power integrity model ñ Extend signal integrity model to consider partial shieldingñ Both have to be computational efficient for co-design