inf2270 — spring 2011 · von neumann architecture in 1945 john von neumann published his...

INF2270 — Spring 2011

Lecture 5: Von Neumann Architecture

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Von Neumann Architecture

Execution UnitALU

MemorySRAMDRAM

Control UnitRegister Transfer LanguageExecution of InstructionsMicroarchitecture

Lecture 5: Von Neumann Architecture 2

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Von Neumann Architecture

Execution UnitALU

MemorySRAMDRAM

Control UnitRegister Transfer LanguageExecution of InstructionsMicroarchitecture

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Von Neumann Architecture

In 1945 John von Neumann published his reference modelof a computer architecture that is still the basis of mostcomputer architectures today. The main novelty was thata single memory was used for both, program and data.

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Von Neumann Architecture Block Diagram

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Typical Registers(1/3)

PC: (program counter, also called instructionpointer (IP)) the register holding the memoryaddress of the next machine code instruction.

IR: (instruction register) the register holding themachine code of the instruction that isexecuted.

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Typical Registers(2/3)

MAR: (memory address register) half of the registersdedicated as interface of the memory with theCPU, holding the memory address to be reador written to.

MBR: (memory buffer register) the other half of theCPU-memory interface, a buffer holding thedata just read from the memory or to bewritten to the memory. Typically the MBR canbe connected as one of the inputs to the ALU.

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Typical Registers(2/3)

accumulator: a dedicated register that stores one operandand the result of the ALU. Severalaccumulators (or general purpose registers inthe CPU) allow for storing of intermediateresults, avoiding (costly) memory accesses.

flag/status register: a register where each single bitstands for a specific property of the resultfrom (or the input to) the ALU, like carryin/out, equal to zero, even/uneven ...

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Data and Instruction Bus

Buses are connections between registers, the functionalunits (such as the ALU), the memory, and I/O units. Theyare often shared by several of those units and usually onlyone unit sends data on the bus to one other at a time.Since there is only one bus between the memory and theCPU for both instruction and data transfer in a vonNeumann architecture (actually two: one for the addressand one for the data), this bus can be a main speedlimiting factor (von Neumann bottleneck). Internally in theCPU there is one or several buses for data exchange amongthe registers.

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content

Von Neumann Architecture

Execution UnitALU

MemorySRAMDRAM

Control UnitRegister Transfer LanguageExecution of InstructionsMicroarchitecture

Lecture 5: Von Neumann Architecture 10

content

Von Neumann Architecture

Execution UnitALU

MemorySRAMDRAM

Control UnitRegister Transfer LanguageExecution of InstructionsMicroarchitecture

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A 1-bit Arithmetic Logic Unit (ALU) Example

Symbol:

inst computation

000 a^ b

001 a^ b

010 a_ b

011 a_ b

100 a� b

101 a� b

110 a� b

111 a� b�!�

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n-bit ALU example

Symbol:

More complicated ALUswill have more flags,e.g. overflow, divide byzero ...

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ALUs in CPUs

Modern CPUs contain several ALUs, e.g. one dedicated tomemory pointer operations and one for data operations.ALUs can be much more complex and perform many morefunctions in a single step than the example shown here,but note that even a simple ALU can compute complexoperations in several steps, controlled by the software.Thus, there is always a trade-off of where to put thecomplexity: either in the hardware or in the software.Complex hardware can be expensive in powerconsumption, chip area and cost. Furthermore, the mostcomplex operation may determine the maximal clockspeed. The design of the ALU is a major factor indetermining the CPU performance!

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content

Von Neumann Architecture

Execution UnitALU

MemorySRAMDRAM

Control UnitRegister Transfer LanguageExecution of InstructionsMicroarchitecture

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Static Random Access Memory Principle

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RAM terminology

address space: the number of addressable units (eitherwords or bytes) in a RAM. In the previousexample its equivalent to the number of rows.

word length: The number of bits that can be accessed in asingle read/write operation, i.e. the number ofbits addressed with a single address. In theprevious example the number of columns.

memory size: adressable unit multiplied with addressspace or equivalent the number of wordsmultiplied with word size.

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Most Typical RAM Signals (1/3)

WE, write enable (often active low): This signaldistinguishes a read from a write access. Ifthere is no RAS/CAS input to the RAM, WEgoing low directly causes D to be stored intothe RAM at address A.

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Most Typical RAM Signals (2/3)

RAS/CAS, row/column access strobe: appears in DRAMthat actually has a 3-D structure: one decoderfor the row address, one for the columnaddress and the word (conceptually) extendsinto the third dimension. The address bus isreused for both row and column address. Firstthe row address is asserted on the address busA and RAS is pulsed low, then the columnaddress is asserted on the address bus andCAS is pulsed low. CAS is the final signal thattriggers the either read or write. The othersignals are asserted before. Several columnaccesses can be made for a single row accessfor faster access times.Lecture 5: Von Neumann Architecture 19

Most Typical RAM Signals (3/3)

OE, output enable: A signal that regulates the access ifthere are several devices using the bus. Onlyone of them should be allowed to drive thebus at anyone time.

CS, chip select: A control line that allows to use severalRAMs instead of just one on the same addressbus and sharing all other control signals. If CSis not asserted all other signals are ignoredand the output is not enabled. Extra addressbits are used to address one specific RAM anda decoder issues the appropriate CS to just oneRAM at a time. This extends the address space.

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Dynamic Random Access Memory Principle

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DRAM refresh

Capacitive storage is not self maintaining like flip flops.Memory content is lost over time. Thus, the senseamplifier has to be connected to every memory cell withina given time period, while the memory is idle. In modernDRAM internal state machines take care of this refreshcycle.

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Static vs. Dynamic RAM

SRAM DRAM

access speed + -

memory density - +

no refresh needed + -

simple internal control + -

price per bit - +

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content

Von Neumann Architecture

Execution UnitALU

MemorySRAMDRAM

Control UnitRegister Transfer LanguageExecution of InstructionsMicroarchitecture

Lecture 5: Von Neumann Architecture 24

content

Von Neumann Architecture

Execution UnitALU

MemorySRAMDRAM

Control UnitRegister Transfer LanguageExecution of InstructionsMicroarchitecture

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Register Transfer Language (RTL)

expression meaning

X register X or unit X

�X� the content of X

replace/insert or execute code

M() memory M

�M(�X�)] memory content at address �X�

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RTL Examples

�IR� �MBR� transfer the content of the MBR tothe IR

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content

Von Neumann Architecture

Execution UnitALU

MemorySRAMDRAM

Control UnitRegister Transfer LanguageExecution of InstructionsMicroarchitecture

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A Simple Example CPU Executing MachineCode

At start-up of the CPU the programcounter is initialized to a specificmemory address. Here to address0. The memory content is asfollows:

mem adr content

0 move 4

1 add 5

2 store 6

3 stop

4 1

5 2

6 0...

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Fetch

At the beginning of a instruction cycle a new instruction isfetched from the memory. A finite state machine in thecontrol unit generates the right sequence of controlsignals. Actually the CU is nothing but a finite statemachine controlled by the instructions.

�MAR� �PC��PC� �PC�� 1�MBR� �M��MAR����IR� �MBR�

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Decode

As a last stage of the fetch phase the operation code(’move’) of the instruction is decoded by the control unit(CU).

CU �IR�opcode��

and triggers a cycle of the finite state machine with theappropriate signals to execute a sequence of operationsspecific to the instruction. The order, type and number ofthe individual operations may vary among differentinstructions and the set of instructions is specific to aparticular CPU.

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Machine Code

The other part of the ’machine code’ instruction in our(16-bit) processor is the ’operand’ 4. What we have writtenas ’move 4’ is actually a bit pattern:

10110010| {z } 00000100| {z }opcode: move operand: 4

As mentioned before, the set of instructions and themachine codes are specific to a CPU. Machine code is notportable between different CPUs.

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Execute

The data from memory location 4 (1) is moved to theaccumulator A (often the accumulator is the implicit targetof instructions without being explicitly defined):�MAR� �IR�operand���MBR� �M��MAR����A� �MBR�

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2nd Instruction (1/2)

A fetch and decode exactly like before:�MAR� �PC� (now �PC�=1)�PC� �PC�� 1�MBR� M��MAR���IR� �MBR�The instruction in the IR is now ’add 5’.CU �IR�opcode��

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2nd Instruction (2/2)

Again the accumulator is the implicit target of theinstruction:�MAR� �IR�operand���MBR� �M��MAR���The ALU receives the appropriate instruction from thestate machine triggered by the opcode, or sometimesparts of the opcode are the instruction for the ALU.ALU �A�;ALU �MBR��A� ALUThe number from memory location 5 (2) has been addedand the result (3) is stored in the accumulator.

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3rd Instruction

Fetch and decode like before (not shown)....and then executing a write operation to the memory:�MBR� �A��MAR� �IR�operand���M��MAR��� �MBR�

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4th Instruction

The forth instruction is a stopinstruction which halts theexecution of the program. Thememory content is now changedto:

mem adr content

0 move 4

1 add 5

2 store 6

3 stop

4 1

5 2

6 3...

...

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content

Von Neumann Architecture

Execution UnitALU

MemorySRAMDRAM

Control UnitRegister Transfer LanguageExecution of InstructionsMicroarchitecture

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Microarchitecture

æ So far we have considered a so called hardwired CUarchitecture, where a hardwired FSM issues the rightsequence of control signals in response to a machinecode in the IR.

æ A more flexible alternative is to use microcode and asimple ’processor’ within the processor that simplyissues a sequence of control signals stored asmicroinstructions in the microprogram memory,typically a fast read only memory (ROM) butsometimes also a flash memory (i.e. electricallyerasable programmable read only memory (EEPROM)).

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Hardwired and Microprogrammed CU

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Pros and ConsMicroarchitecture Hardwired

Occurrence CISC RISC

Flexibility + -

Design Cycle + -

Speed - +

Compactness - +

Power - +

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