ic mask design - ic layout acceleration tool - dac conference, june 2010

Acceleration of Analog Physical Design

HiPerDevGen™ - Structure Generation

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Shorter Product Development Times1

Shrinking Process Geometries

EDA advancement on other areas of M/S Design

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Factors Driving the need for Analog Acceleration

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Shorter Product Development Times

Shorter Product Development Times Faster Time to Market

Average IC Product Development Times

0 6 12 18 24 30

0 6 12 18 24 30

Early 1990’s cycle times

Today’s average cycle times

“We need to re-assess design tools and practices to ensure we can achieve right first time design in a reasonable timeframe, and thus reach profitability sooner.”

Douglas Pattullo, Director Field Technical Support, TSMC Europe

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Effects of Shrinking Geometries

Companies are most concerned about the challenges of higher mask costs, greater design complexity, IP costs and availability, and inadequate EDA tools.

Source: Kalypso Semiconductor Analysis 2009.

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Effects of Shrinking Process Geometries

Technology Cost Pressures– As geometries shrink, mask and design costs go up

0 1 2 3 4 5 6 7 8 9 10$0

$20,000

$40,000

$60,000

$80,000

$100,000

$120,000

$0

$1,000,000

$2,000,000

$3,000,000

$4,000,000

$5,000,000

$6,000,000

Design & Mask Costs

Design Cost Mask Costs

Geometry nm

Source: EETimes

350nm 90nm 22nm

TSMC’s wafer forecast shows a 40% CAGR (4x in 5 years) due to new designs in 90nm, 65nm and smaller

First pass silicon is an essential target for all semiconductor

companies regardless of geometry

Des

ign

Co

sts

($k)

Mask C

osts ($M

)

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Effects of Shrinking Process Geometries

EDA Trends– Development and support of Design Kits– Hierarchical Verification– Successful deployment of P&R Tools

• Can handle multi-million gate designs

– Use of greater processing power

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Effects of Shrinking Process Geometries

Design cycle times at 90nm are increasing!! Why??– Analog Layout Design IS now a bottleneck!!– Acceleration of this process is key

Transistor Count

Design Time

250nm 90nm 45nm

Transistor Count v Design Cycle Time

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Analog Design – Bottleneck

Full automation approach has not gained traction

Analog Automation has been a disappointment Difficult to set up Schematics need to be generated in defined formats Complicated to Constrain

Analog designers like to retain control

Very difficult to automate analog layout due to the ‘artistic’ nature of the process

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Analog Physical Design Automation

What do users want?– Create efficient device placements from user-provided

constraints– Do this in a matter of minutes– Easy to set-up and use – Compliments existing user environments– Closely resemble handcrafted layout– Allow designers to apply constraints to groups of

devices

Source: Jim Solomon, Founder Cadence

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Our Approach

Recognition and Generation of Common Structures

Correct by Construction

Consistent High Quality

Is “Silicon Aware”

Differential Pairs Current Mirrors Resistor Dividers

Closely aligned to handcrafted layout DRC & LVS Clean

Guarantees design standards are the same across the whole organisation

Understands functionality & process artefacts

Analog Designers can easily tune the design

Rapid generation and simulation loop for optimal solution

Our Approach

Acceleration

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Our Solution

Automatic generation of design primitives– Using only set of DRC rules as base input – Reduces manual tasks and accelerates full custom layout

No change in design flow methodology Understands design and process requirements

associated with each structure– Matching, Parasitics

Technology node aware– Devices and structures scale with design rules– WPE, STI/LOD effects on nanometer technologies

HiPerDevGen™HiPerDevGen™

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Quick & Easy Set-up

Manufacturing Rules User friendly GUI for set-up of

new technologies No CAD development required Instant generation of

parameterized devices and structures

20 minutes for any new process

Note: Tanner will provide technology set-ups free of charge

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Features of HiPerDevGen™

FloorplanEstimationsFloorplan

EstimationsGuarantees

MatchingGuarantees

Matching

Layout Optimization

Layout Optimization

Parasitic Aware

Parasitic Aware

UserTuningUser

Tuning

FunctionallyAware

FunctionallyAware

HiPerDevGen™HiPerDevGen™

Linear Process Gradients Mask Misalignment Implant Shadowing Photolithographic Invariance Current Flow Direction Antenna / VT Shift WPE

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Features of HiPerDevGen™

Guarantees Matching

Guarantees Matching

FloorplanEstimationsFloorplan

Estimations

Parasitic Aware

Parasitic Aware

UserTuningUser

Tuning

FunctionallyAware

FunctionallyAware

HiPerDevGen™HiPerDevGen™

Accelerates Layout timeOptimized for YieldDouble Contacts / ViasSupport for DFM

Layout Optimization

Layout Optimization

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Features of HiPerDevGen™

FloorplanEstimationsFloorplan

Estimations Guarantees Matching

Guarantees Matching

Parasitic Aware

Parasitic Aware

UserTuningUser

Tuning

FunctionallyAware

FunctionallyAware

HiPerDevGen™HiPerDevGen™

Considers device and interconnect parasitics

Optimal solution based on user specific parasitic requirements Layout

Optimization

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Features of HiPerDevGen™

Floorplan EstimationsFloorplan

EstimationsGuarantees

MatchingGuarantees

Matching

Layout Optimization

Layout Optimization

Parasitic Aware

Parasitic Aware

UserTuningUser

Tuning

FunctionallyAware

FunctionallyAware

HiPerDevGen™HiPerDevGen™ Ensures user defined matching, parasitic and performance requirements Reduced Simulation Cycle

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Features of HiPerDevGen™

FloorplanEstimationsFloorplan

EstimationsGuarantees

MatchingGuarantees

Matching

Layout Optimizatons

Layout Optimizatons

Parasitic Aware

Parasitic Aware

UserTuningUser

Tuning

FunctionallyAware

FunctionallyAware

HiPerDevGen™HiPerDevGen™

Understands functional differences between structures

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Features of HiPerDevGen™

Layout Optimization

Layout Optimization

Guarantees Matching

Guarantees Matching

FloorplanEstimationsFloorplan

Estimations

Parasitic Aware

Parasitic Aware

UserTuningUser

Tuning

FunctionallyAware

FunctionallyAware

HiPerDevGen™HiPerDevGen™Prompt Floorplan Estimation

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Features of HiPerDevGen™

FloorplanEstimations

FloorplanEstimations

Guarantees Matching

Guarantees Matching

LayoutOptimization

LayoutOptimization

Parasitic Aware

Parasitic Aware

UserTuningUser

Tuning

FunctionallyAware

FunctionallyAware

HiPerDevGen™HiPerDevGen™

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Current Mirror Generation

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Current Mirror Generation

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Current Mirror Generation

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Current Mirror Generation

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Current Mirror Generation

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Current Mirror Generation

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Current Mirror Generation

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Differential Pair Generation

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Differential Pair Generation

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Differential Pair Generation

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Differential Pair Generation

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Differential Pair Generation

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Differential Pair Generation

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Differential Pair Generation

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Typical Op Amp Schematic

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Typical SDL Flow– Op Amp

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HiPerDevGen: Structure Recognition

Recognition of Differential Pairs

Recognition of Current Mirrors

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HiPerDevGen Generation

Generation of Current Mirrors

Generation of Differential Pairs

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Completed Op-Amp

Total Layout time <1 hr !!

Total Layout time <1 hr !!

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Summary

Analog Layout is now a bottleneck Automation attempts have not gained traction

HiPerDevGen adopts an acceleration approach

Generates high quality “first time right” layout Is “Silicon Aware” and understands process artefacts Gives the user complete control over the design Simple to set-up and use No change in design flow methodology

Problem

Solution

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View a HiPerDevGen™ Demo

Tanner – Booth #1342

Tanner EDA User Event Thursday 17th June 2010

For more information visit www.tannnereda.com

Come See for Yourself!