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28.11.2016
1
Fundamentals of Computer EngineeringFundamentals of Computer EngineeringChapter 4: Combinational Circuits
Dr.-Ing. Stefan Werner
Wintersemester 2016/17
Table of content
Chapter 1: Switching AlgebraChapter 2: Logical Levels, Timing & DelaysChapter 3: Karnaugh-Veitch-Maps • Design of combinationalChapter 3: Karnaugh Veitch MapsChapter 4: Combinational Circuit DesignChapter 5: Latches and Flip FlopsChapter 6: Finite State MachinesChapter 7: Basic Sequential CircuitsChapter 9: Number Systems
• Design of combinationalcircuits in 3-Steps
• Multiplexer• Demultiplexer• Comparator• Incrementer• Arithmetic-Logic Unit
Fachgebiet Technische InformatikProf. Dr.‐Ing. Axel Hunger
Fundamentals of Computer EngineeringWintersemester 2016/17
Lecturer: Dr. Ing. Stefan Werner2 of 26
p yChapter 9: Binary ArithmeticChapter 10: Binary Codes
Arithmetic Logic Unit• Half Adder• Full Adder• Parallel Adder
28.11.2016
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Design of combinational circuits in 3 steps
↔( )A f E=ur ur
1 2( , ... )i nA f E E E= E1 E2
A1A2
mod
elm
inim
ize
Basic steps:
1. Formulate the problem
…
E2
E n
Am
Combinational Circuit
Fachgebiet Technische InformatikProf. Dr.‐Ing. Axel Hunger
Fundamentals of Computer EngineeringWintersemester 2016/17
Lecturer: Dr. Ing. Stefan Werner3 of 26
2. Minimise the output functions
3. Draw the circuit
Example: 4:1- Multiplexer
I0 I1 I2 I3 C0 C1 O
0 X X X 0 0 0
I0 I1 I2 I3 C0 C1 OI0 I1 I2 I3 C0 C1 O
1 X X X 0 0 1
X 0 X X 0 1 0
X 1 X X 0 1 1
X X 0 X 1 0 0
Fachgebiet Technische InformatikProf. Dr.‐Ing. Axel Hunger
Fundamentals of Computer EngineeringWintersemester 2016/17
Lecturer: Dr. Ing. Stefan Werner4 of 26
X X 1 X 1 0 1
X X X 0 1 1 0
X X X 1 1 1 1
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8:1 Multiplexer
Fachgebiet Technische InformatikProf. Dr.‐Ing. Axel Hunger
Fundamentals of Computer EngineeringWintersemester 2016/17
Lecturer: Dr. Ing. Stefan Werner5 of 26
Source: Dirk. W. Hoffmann: Grundlagen der technischen Informatik, Hanser Verlag
Multiplexer ApplicationsExample 1Control of Dataflow
Fachgebiet Technische InformatikProf. Dr.‐Ing. Axel Hunger
Fundamentals of Computer EngineeringWintersemester 2016/17
Lecturer: Dr. Ing. Stefan Werner6 of 26
MUX controls wetherAccumulator will load Data fromcache or memory
Analogue: Rail trafficMUX corresponds to switchcontrol.
Source: Dirk. W. Hoffmann: Grundlagen der technischen Informatik, Hanser Verlag
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Demultiplexer
C0 C1 I O0 O1 O2 O3
0 0 0 0 0 0 0
0 0 1 1 0 0 0
0 1 0 0 0 0 0
0 1 1 0 1 0 0
1 0 0 0 0 0 0
1 0 1 0 0 1 0
Fachgebiet Technische InformatikProf. Dr.‐Ing. Axel Hunger
Fundamentals of Computer EngineeringWintersemester 2016/17
Lecturer: Dr. Ing. Stefan Werner7 of 26
1 0 1 0 0 1 0
1 1 0 0 0 0 0
1 1 1 0 0 0 1
Comparator
Logic device that– checks two dual numbers regarding „=“, „>“„<“– Input: (an a0) and (bn b0) represent the digits of a dual numberInput: (an, …, a0) and (bn, …, b0) represent the digits of a dual number– Output: „A>B“, „A=B“, „A<B“
A B X=A>B Y= A=B Z=A<B0 00 I
Example: 1-Bit Comparator
Fachgebiet Technische InformatikProf. Dr.‐Ing. Axel Hunger
Fundamentals of Computer EngineeringWintersemester 2016/17
Lecturer: Dr. Ing. Stefan Werner8 of 26
0 II 0I I
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One-Bit Comparator with Enable lineComparision shall start only at defined points in time
Special input line needed that triggers the beginning
E bl li⇒Enable line
E=I: comparator active
E=0: comparator inactive
Fachgebiet Technische InformatikProf. Dr.‐Ing. Axel Hunger
Fundamentals of Computer EngineeringWintersemester 2016/17
Lecturer: Dr. Ing. Stefan Werner9 of 26
4-Bit Comparator
a3 a2 a1a0 b3 b2 b1 b0 X Y Z0 0 0 0 0 0 0 0 0 I 00 0 0 0 0 0 0 I 0 0 I
withX=A>B
.................................................................
.................................................................I I I I I I I I 0 I 0
X=A>BY= A=BZ=A<B
For a full truth table 28 possible input combinations
Fachgebiet Technische InformatikProf. Dr.‐Ing. Axel Hunger
Fundamentals of Computer EngineeringWintersemester 2016/17
Lecturer: Dr. Ing. Stefan Werner10 of 26
For a full truth table 2 possible input combinations
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4-Bit Comparator
Fachgebiet Technische InformatikProf. Dr.‐Ing. Axel Hunger
Fundamentals of Computer EngineeringWintersemester 2016/17
Lecturer: Dr. Ing. Stefan Werner11 of 26
Source: Dirk. W. Hoffmann: Grundlagen der technischen Informatik, Hanser Verlag
4-Bit Comparator
a3 a2 a1a0 b3 b2 b1 b0 X Y ZI 0 0 0 0 0 0 0 I 0 0I 0 0 I 0 0 0 I I 0 0I 0 I 0 0 0 I 0 I 0 0I 0 0 I 0 0 0 I I 0 0I 0 I I 0 0 I I I 0 0I I 0 0 0 I 0 0 I 0 0I I 0 I 0 I 0 I I 0 0I I I 0 0 I I 0 I 0 0
Fachgebiet Technische InformatikProf. Dr.‐Ing. Axel Hunger
Fundamentals of Computer EngineeringWintersemester 2016/17
Lecturer: Dr. Ing. Stefan Werner12 of 26
I I I 0 0 I I 0 I 0 0I I I I 0 I I I I 0 0
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4-Bit Comparator
Fachgebiet Technische InformatikProf. Dr.‐Ing. Axel Hunger
Fundamentals of Computer EngineeringWintersemester 2016/17
Lecturer: Dr. Ing. Stefan Werner13 of 26
4-Bit Comparator
Fachgebiet Technische InformatikProf. Dr.‐Ing. Axel Hunger
Fundamentals of Computer EngineeringWintersemester 2016/17
Lecturer: Dr. Ing. Stefan Werner14 of 26
28.11.2016
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Full Adder
A S
Full adder(FA)
B
CinCout
Fachgebiet Technische InformatikProf. Dr.‐Ing. Axel Hunger
Fundamentals of Computer EngineeringWintersemester 2016/17
Lecturer: Dr. Ing. Stefan Werner15 of 26
Full AdderCircuit Design
A B C1 S C2 0 0 0 0 0
FA-Truth Table
0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 0 0 1 0 0 1 1 0 0 1 1 0 1 1 0 1 0 1
Fachgebiet Technische InformatikProf. Dr.‐Ing. Axel Hunger
Fundamentals of Computer EngineeringWintersemester 2016/17
Lecturer: Dr. Ing. Stefan Werner16 of 26
1 1 1 1 1
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Parallel AdderCarry-Ripple Adder
• half adder and full adder are basic devices to build “real” calculation machines.
• to realise n bit adders we can use a parallel approach
FA FAFA HA
A3 A0A1A2
to realise n bit adders we can use a parallel approach
one basic adder for every bit.• for the LSB: half adder
• for all other digits: one full adder per digit.
Fachgebiet Technische InformatikProf. Dr.‐Ing. Axel Hunger
Fundamentals of Computer EngineeringWintersemester 2016/17
Lecturer: Dr. Ing. Stefan Werner17 of 26
B3 B0B1B2
S3 S0S2 S1C
Carry-look-ahead-adder
Fachgebiet Technische InformatikProf. Dr.‐Ing. Axel Hunger
Fundamentals of Computer EngineeringWintersemester 2016/17
Lecturer: Dr. Ing. Stefan Werner18 of 26
28.11.2016
10
Carry-look-ahead-adder
Fachgebiet Technische InformatikProf. Dr.‐Ing. Axel Hunger
Fundamentals of Computer EngineeringWintersemester 2016/17
Lecturer: Dr. Ing. Stefan Werner19 of 26
Incrementer• increment building is one of the most used arithmetic operations
in a microprocessor (e.g. increase addresscounter)
• incrementer is a special case of an adder(a one is added to a number B)
Fachgebiet Technische InformatikProf. Dr.‐Ing. Axel Hunger
Fundamentals of Computer EngineeringWintersemester 2016/17
Lecturer: Dr. Ing. Stefan Werner20 of 26
28.11.2016
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Arithmetic-Logic Unit (ALU)The ALU
• performs many different arithmetic and e c dlogic operations.
• is the “heart” of a processor
Fachgebiet Technische InformatikProf. Dr.‐Ing. Axel Hunger
Fundamentals of Computer EngineeringWintersemester 2016/17
Lecturer: Dr. Ing. Stefan Werner21 of 26
ALUExample: Design of a simple but complete ALU
• Problem description:– arithmetic unit shall be able to compute eight functions on 4-bit p g
inputs. – logic unit shall be able to perform four functions on 4-bit inputs.
• x,y: input words of 4-bit length each• G: Output word of 4-bit length• S: control word to select 1-out of 12-4
4
4
Fachgebiet Technische InformatikProf. Dr.‐Ing. Axel Hunger
Fundamentals of Computer EngineeringWintersemester 2016/17
Lecturer: Dr. Ing. Stefan Werner22 of 26
possible functions44
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ALUExample of a function table
S3 S2 S1 S0 Operation 0 0 0 0 G = X 0 0 0 1 G = X + 1
• all arithmetic operations have S3=0, and all of the logical operations have S =1
0 0 1 0 G = X + Y 0 0 1 1 G = X + Y + 1 0 1 0 0 G = X + Y’ 0 1 0 1 G = X + Y’ + 1 0 1 1 0 G = X – 1 0 1 1 1 G = X 1 x 0 0 G = X and Y
operations have S3=1.• since our ALU only has 4
logical operations, we don’t need S2. The operation done by the logic unit depends only on S1 and S0.
Fachgebiet Technische InformatikProf. Dr.‐Ing. Axel Hunger
Fundamentals of Computer EngineeringWintersemester 2016/17
Lecturer: Dr. Ing. Stefan Werner23 of 26
1 x 0 0 G = X and Y 1 x 0 1 G = X or Y 1 x 1 0 G = X ⊕ Y 1 x 1 1 G = X’
ALUComments on the MUX
• Both the arithmetic unit and the logic unit are “active” and produce outputs.
– The mux determines whether the final result comes from the arithmetic or logic unit.
– The output of the other one is effectively ignored.
– Signal S3 can be used to select wether output comes from arithmetic unit or logic unit
Fachgebiet Technische InformatikProf. Dr.‐Ing. Axel Hunger
Fundamentals of Computer EngineeringWintersemester 2016/17
Lecturer: Dr. Ing. Stefan Werner24 of 26
28.11.2016
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ALUBlock diagramm of a complete ALU Circuit
Cout should be ignored when logic operations
The / and 4 on a line indicate that it’s actually four lines.4
4
G is the final ALU output.• When S3 = 0, the final
output comes from the i h i i
when logic operations are performed (when S3=1).4
4 4
Fachgebiet Technische InformatikProf. Dr.‐Ing. Axel Hunger
Fundamentals of Computer EngineeringWintersemester 2016/17
Lecturer: Dr. Ing. Stefan Werner25 of 26
arithmetic unit.• When S3 = 1, the output
comes from the logic unit.
The arithmetic and logic units share the select inputs S1 and S0, but only the arithmetic unit uses S2.
ALUSummary
• ALU is a good example of hierarchical design.
– With the 12 inputs, the truth table would have had p ,212 = 4096 lines. That’s an awful lot of paper.
– Instead, components can be used and the ALU can be constructed from a couple of easy-to-understand components.
Fachgebiet Technische InformatikProf. Dr.‐Ing. Axel Hunger
Fundamentals of Computer EngineeringWintersemester 2016/17
Lecturer: Dr. Ing. Stefan Werner26 of 26
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