freebsd on freescale qoriq data path acceleration architecture devices · 2015-12-16 · freebsd on...

FreeBSD on Freescale QorIQ Data Path Acceleration Architecture Devices

FreeBSD on Freescale QorIQ Data PathAcceleration Architecture Devices

Piotr Zięcikkosmo@semihalf.com

BSDCan 2012 9-13 May, 2012

Presentation outline

I Introduction,

I Hardware description:

I Data Path Acceleration Architecture.

I Software description:

I Porting process.

I Current state,I Future work.

I Introduction,I Hardware description:

I Data Path Acceleration Architecture.I Software description:

I Porting process.

I Software description:

I Porting process.

I Porting process.I Current state,I Future work.

I Porting process.

I Porting process.I Current state,

I Future work.

I Porting process.I Current state,I Future work.

Introduction

Networks are too fast!

I High packet rate:

I Fast Ethernet: 182 kpps.I Gigabit Ethernet: 1.46 Mpps

(4k ring buffer full in 2.8 ms).

I Problems:

I High interrupt rate and/or latency,I DMA memory management overhead,I Lock congestion,I Packet parsing/inspection overhead.

Introduction

I High packet rate:

I Fast Ethernet: 182 kpps.I Gigabit Ethernet: 1.46 Mpps

I Problems:

Introduction

I High packet rate:I Fast Ethernet: 182 kpps.

I Gigabit Ethernet: 1.46 Mpps

I Problems:

Introduction

I High packet rate:I Fast Ethernet: 182 kpps.I Gigabit Ethernet: 1.46 Mpps

(4k ring buffer full in 2.8 ms).I Problems:

Introduction

I High packet rate:I Fast Ethernet: 182 kpps.I Gigabit Ethernet: 1.46 Mpps (4k ring buffer full in 2.8 ms).

I Problems:

Introduction

I Problems:

Introduction

I Problems:I High interrupt rate and/or latency,

I DMA memory management overhead,I Lock congestion,I Packet parsing/inspection overhead.

Introduction

I Problems:I High interrupt rate and/or latency,I DMA memory management overhead,

I Lock congestion,I Packet parsing/inspection overhead.

Introduction

I Problems:I High interrupt rate and/or latency,I DMA memory management overhead,I Lock congestion,

I Packet parsing/inspection overhead.

Introduction

I Problems:I High interrupt rate and/or latency,I DMA memory management overhead,I Lock congestion,I Packet parsing/inspection overhead.

Freescale QoriQ DPAA Family

I Most recent Freescale Communication SoCs,

I Successor of the PowerQUICC family,I Up to 8 e500mc Cores,I Up to 2x 10GbE + 8x 1GbE,I Hardware Virtualization Support,I Data Path Acceleration Architecture.

I Most recent Freescale Communication SoCs,I Successor of the PowerQUICC family,

I Up to 8 e500mc Cores,I Up to 2x 10GbE + 8x 1GbE,I Hardware Virtualization Support,I Data Path Acceleration Architecture.

I Most recent Freescale Communication SoCs,I Successor of the PowerQUICC family,I Up to 8 e500mc Cores,

I Up to 2x 10GbE + 8x 1GbE,I Hardware Virtualization Support,I Data Path Acceleration Architecture.

I Most recent Freescale Communication SoCs,I Successor of the PowerQUICC family,I Up to 8 e500mc Cores,I Up to 2x 10GbE + 8x 1GbE,

I Hardware Virtualization Support,I Data Path Acceleration Architecture.

I Most recent Freescale Communication SoCs,I Successor of the PowerQUICC family,I Up to 8 e500mc Cores,I Up to 2x 10GbE + 8x 1GbE,I Hardware Virtualization Support,

I Most recent Freescale Communication SoCs,I Successor of the PowerQUICC family,I Up to 8 e500mc Cores,I Up to 2x 10GbE + 8x 1GbE,I Hardware Virtualization Support,I Data Path Acceleration Architecture.

QorIQ P3041 Communication Processor (source: P3041 Fact Sheet)

Data Path Acceleration Architecture

Components

I Buffer Manager,I Queue Manager,I Frame Manager (NICs),I Others:

I Security Accelerator,I Pattern Matching Engine.

Components

I Buffer Manager,

I Queue Manager,I Frame Manager (NICs),I Others:

Components

I Buffer Manager,I Queue Manager,

I Frame Manager (NICs),I Others:

Components

I Buffer Manager,I Queue Manager,I Frame Manager (NICs),

I Others:

Components

I Security Accelerator,

I Pattern Matching Engine.

Components

Components: Buffer Manager

I Maintains Buffers,I Pools = Set of Buffers,I Pools are managed by software,I Software and hardware may directly allocate/free buffer.

I Maintains Buffers,

I Pools = Set of Buffers,I Pools are managed by software,I Software and hardware may directly allocate/free buffer.

I Maintains Buffers,I Pools = Set of Buffers,

I Pools are managed by software,I Software and hardware may directly allocate/free buffer.

I Maintains Buffers,I Pools = Set of Buffers,I Pools are managed by software,

I Software and hardware may directly allocate/free buffer.

I Maintains Buffers,I Pools = Set of Buffers,I Pools are managed by software,I Software and hardware may directly allocate/free buffer.

Components: Queue Manager

I Maintains Frames,I Frame Queue = Linked list of Frames,I Work Queue = Linked list of Frame Queues,I Channel = 8 ∗ (Work Queue + Priority).

I Maintains Frames,

I Frame Queue = Linked list of Frames,I Work Queue = Linked list of Frame Queues,I Channel = 8 ∗ (Work Queue + Priority).

I Maintains Frames,I Frame Queue = Linked list of Frames,

I Work Queue = Linked list of Frame Queues,I Channel = 8 ∗ (Work Queue + Priority).

I Maintains Frames,I Frame Queue = Linked list of Frames,I Work Queue = Linked list of Frame Queues,

I Channel = 8 ∗ (Work Queue + Priority).

I Maintains Frames,I Frame Queue = Linked list of Frames,I Work Queue = Linked list of Frame Queues,I Channel = 8 ∗ (Work Queue + Priority).

I Frames are enqueued to Frame Queues,

I Frames are dequeued from Channels,I Channels are attached to SoC components:

I Dedicated Channel: Connected to single device,I Poll Channel: Connected to group of devices.

I Other Queue Manager features:

I Congestion Management (Tail drop, RED/WRED),I Frame order restoration.

I Frames are enqueued to Frame Queues,I Frames are dequeued from Channels,

I Channels are attached to SoC components:

I Frames are enqueued to Frame Queues,I Frames are dequeued from Channels,I Channels are attached to SoC components:

I Dedicated Channel: Connected to single device,

I Poll Channel: Connected to group of devices.I Other Queue Manager features:

I Other Queue Manager features:I Congestion Management (Tail drop, RED/WRED),

I Frame order restoration.

I Other Queue Manager features:I Congestion Management (Tail drop, RED/WRED),I Frame order restoration.

Data Path Acceleration ArchitectureComponents: Frame Manager

I MACs:

I 1x 10Gb Ethernet + 5x 1Gb Ethernet.

I DMA:

I Buffer Manager Interface (QMI).I Queue Manager Interface (BMI),I DMA Engine,

I Frame Processor:

I Parser,I Key Generator,I Policer,I Frame Processing Module.

I MACs:

I 1x 10Gb Ethernet + 5x 1Gb Ethernet.I DMA:

I Frame Processor:

I MACs:I 1x 10Gb Ethernet + 5x 1Gb Ethernet.

I DMA:

I Frame Processor:

I DMA:

I Frame Processor:

I DMA:I Buffer Manager Interface (QMI).

I Queue Manager Interface (BMI),I DMA Engine,

I Frame Processor:

I DMA:I Buffer Manager Interface (QMI).I Queue Manager Interface (BMI),

I DMA Engine,I Frame Processor:

I DMA:I Buffer Manager Interface (QMI).I Queue Manager Interface (BMI),I DMA Engine,

I Frame Processor:

I Frame Processor:I Parser,

I Key Generator,I Policer,I Frame Processing Module.

I Frame Processor:I Parser,I Key Generator,

I Policer,I Frame Processing Module.

I Frame Processor:I Parser,I Key Generator,I Policer,

I Frame Processing Module.

I Frame Processor:I Parser,I Key Generator,I Policer,I Frame Processing Module.

Software Portals

I CPU↔ DPAA communication channels,I Portal = Cache Enabled + Cache Inhibited registers,I Transaction oriented,I Efficient SoC Bus usage.

Software PortalsI CPU↔ DPAA communication channels,

I Portal = Cache Enabled + Cache Inhibited registers,I Transaction oriented,I Efficient SoC Bus usage.

Software PortalsI CPU↔ DPAA communication channels,I Portal = Cache Enabled + Cache Inhibited registers,

I Transaction oriented,I Efficient SoC Bus usage.

Software PortalsI CPU↔ DPAA communication channels,I Portal = Cache Enabled + Cache Inhibited registers,I Transaction oriented,

I Efficient SoC Bus usage.

Software PortalsI CPU↔ DPAA communication channels,I Portal = Cache Enabled + Cache Inhibited registers,I Transaction oriented,I Efficient SoC Bus usage.

Hardware: Other selected features

I Cache Stashing,I Virtualization:

I Additional privilege level in e500mc core,I Peripheral Access Management Units,

I Logical I/O Device Number,

I Cache Stashing,

I Virtualization:

I Additional privilege level in e500mc core,

I Peripheral Access Management Units,

I Logical I/O Device Number,I Data Path Acceleration Architecture.

Software

I Toolchain,I Early kernel initialization,I Data Path Acceleration Architecture bring-up,I SMP,

I DPAA in SMP environment,I Other peripherals.

Software

I Toolchain,

I Early kernel initialization,I Data Path Acceleration Architecture bring-up,I SMP,

Software

I Toolchain,I Early kernel initialization,

I Data Path Acceleration Architecture bring-up,I SMP,

Software

I Toolchain,I Early kernel initialization,I Data Path Acceleration Architecture bring-up,

I SMP,I DPAA in SMP environment,

I Other peripherals.

Software

I DPAA in SMP environment,

I Other peripherals.

Software

Toolchain

I Support for e500v2 (predecessor of the e500mc) hadbeen already present,

I Only minor changes were required in binutils and gcc,I All patches were available from the community andFreescale.

Toolchain

I Only minor changes were required in binutils and gcc,

I All patches were available from the community andFreescale.

Toolchain

Early kernel initialization

locore.S

I First code executed in FreeBSD kernel,I Architecture depended assembly,I Prepares environment for C.

PowerPC locore.S

I TLB initialization,I Kernel stack initialization.

locore.SI First code executed in FreeBSD kernel,

I Architecture depended assembly,I Prepares environment for C.

PowerPC locore.S

locore.SI First code executed in FreeBSD kernel,I Architecture depended assembly,

I Prepares environment for C.

PowerPC locore.S

locore.SI First code executed in FreeBSD kernel,I Architecture depended assembly,I Prepares environment for C.

PowerPC locore.S

PowerPC locore.SI TLB initialization,

I Kernel stack initialization.

PowerPC locore.SI TLB initialization,I Kernel stack initialization.

e500mc features in locore.S

I Bigger TLB,I Hypervisor privilege level,I Hardware Implementation-Dependent Registers (HIDs).

New TLB also affects pmap(9).

e500mc features in locore.SI Bigger TLB,

I Hypervisor privilege level,I Hardware Implementation-Dependent Registers (HIDs).

e500mc features in locore.SI Bigger TLB,I Hypervisor privilege level,

I Hardware Implementation-Dependent Registers (HIDs).

e500mc features in locore.SI Bigger TLB,I Hypervisor privilege level,I Hardware Implementation-Dependent Registers (HIDs).

DPAA Bring-up

NetCommSw

I A packet processing framework,I OS Agnostic,I Greatly reduces development time,I Propertiary licensed.

Thanks to Freescale!Buffer, Queue and Frame Manager drivers are now availableunder the BSD license.

DPAA Bring-up

NetCommSw

I A packet processing framework,I OS Agnostic,I Greatly reduces development time,I Propertiary licensed.

DPAA Bring-up

NetCommSwI A packet processing framework,

I OS Agnostic,I Greatly reduces development time,I Propertiary licensed.

DPAA Bring-up

NetCommSwI A packet processing framework,I OS Agnostic,

I Greatly reduces development time,I Propertiary licensed.

DPAA Bring-up

NetCommSwI A packet processing framework,I OS Agnostic,I Greatly reduces development time,

I Propertiary licensed.

DPAA Bring-up

NetCommSwI A packet processing framework,I OS Agnostic,I Greatly reduces development time,I Propertiary licensed.

DPAA Bring-up

NetCommSwI A packet processing framework,I OS Agnostic,I Greatly reduces development time,I Propertiary licensed.

NetCommSw Driver Model

XX Routines

I Simple routines for basic OS functions:

I void *XX_Malloc(unsigned int size)

I Physical to Virtual translation is required:

I Not supported by the FreeBSD kernel,I Ambiguous,

I Solution:

I Keep list of all active mappings in vm_page structure,I pmap_enter() and pmap_remove() manages the list,I XX Routines: PA→ vm_page→ the mappings list→ VA.

XX Routines

I Simple routines for basic OS functions:

I void *XX_Malloc(unsigned int size)I Physical to Virtual translation is required:

I Solution:

XX Routines

I Simple routines for basic OS functions:I void *XX_Malloc(unsigned int size)

I Solution:

XX Routines

I Solution:

XX Routines

I Physical to Virtual translation is required:I Not supported by the FreeBSD kernel,

I Ambiguous,I Solution:

XX Routines

I Physical to Virtual translation is required:I Not supported by the FreeBSD kernel,I Ambiguous,

I Solution:

XX Routines

I Solution:

XX Routines

I Solution:I Keep list of all active mappings in vm_page structure,

I pmap_enter() and pmap_remove() manages the list,I XX Routines: PA→ vm_page→ the mappings list→ VA.

XX Routines

I Solution:I Keep list of all active mappings in vm_page structure,I pmap_enter() and pmap_remove() manages the list,

I XX Routines: PA→ vm_page→ the mappings list→ VA.

XX Routines

I Solution:I Keep list of all active mappings in vm_page structure,I pmap_enter() and pmap_remove() manages the list,I XX Routines: PA→ vm_page→ the mappings list→ VA.

Wrapper Drivers

I OS↔ NetCommSw API translation layer,I Access serialization layer,I Written as simple newbus attachments,I Export own API.

Wrapper Drivers

I OS↔ NetCommSw API translation layer,

I Access serialization layer,I Written as simple newbus attachments,I Export own API.

Wrapper Drivers

I OS↔ NetCommSw API translation layer,I Access serialization layer,

I Written as simple newbus attachments,I Export own API.

Wrapper Drivers

I OS↔ NetCommSw API translation layer,I Access serialization layer,I Written as simple newbus attachments,

I Export own API.

Wrapper Drivers

I OS↔ NetCommSw API translation layer,I Access serialization layer,I Written as simple newbus attachments,I Export own API.

Frame Manager Wrapper Driver

I Consists of several NetCommSw submodules,I Each submodule have own API,I A single Frame Manger Wrapper Driver:

I Performs initialization of common parts,I Manages internal FMan resources,I Exports single, simplified API.

I Consists of several NetCommSw submodules,

I Each submodule have own API,I A single Frame Manger Wrapper Driver:

I Consists of several NetCommSw submodules,I Each submodule have own API,

I A single Frame Manger Wrapper Driver:

I Performs initialization of common parts,

I Manages internal FMan resources,I Exports single, simplified API.

I Performs initialization of common parts,I Manages internal FMan resources,

I Exports single, simplified API.

dTSEC Driver

I Classic NIC driver from OS perspective,I Uses BMan, QMan and FMan wrapper drivers,I Binds DPAA parts together.

dTSEC Driver

I Classic NIC driver from OS perspective,

I Uses BMan, QMan and FMan wrapper drivers,I Binds DPAA parts together.

dTSEC Driver

I Classic NIC driver from OS perspective,I Uses BMan, QMan and FMan wrapper drivers,

I Binds DPAA parts together.

dTSEC Driver

I Classic NIC driver from OS perspective,I Uses BMan, QMan and FMan wrapper drivers,I Binds DPAA parts together.

dTSEC Driver: DPAA Usage

I Buffer Manager:

I RX buffer pool management.

I Queue Manager:

I Reads/Writes frames from/to queues (associated withMACs).

I Frame Manager:

I MAC abstraction,I Data flow configuration.

I Buffer Manager:

I RX buffer pool management.I Queue Manager:

I Frame Manager:

I Buffer Manager:I RX buffer pool management.

I Queue Manager:

I Frame Manager:

I Queue Manager:

I Frame Manager:

I Queue Manager:I Reads/Writes frames from/to queues (associated withMACs).

I Frame Manager:

I Frame Manager:I MAC abstraction,

I Data flow configuration.

I Frame Manager:I MAC abstraction,I Data flow configuration.

dTSEC Driver: TX Path

dTSEC Driver: RX Path

SMP Bring-Up

I Based on existing e500v2 implementation,I Issues with more than 2 cores:

I IPI Multicasting

I DPAA-related issues.

SMP Bring-Up

I Based on existing e500v2 implementation,

I Issues with more than 2 cores:

I IPI Multicasting

SMP Bring-Up

I IPI MulticastingI DPAA-related issues.

SMP Bring-Up

I IPI Multicasting

SMP Bring-Up

I IPI MulticastingI DPAA-related issues.

SMP vs DPAA: Issues

Portal Mapping

I Dedicated portal for each CPU,I Same portal address on each CPU,I Such device mapping was not supported:

I Introduction of "shared" bit,I Implemented using user-defined bits in TLB entry,I Only marked entries are propagated to other cores,I Private are set on each CPU.

SMP vs DPAA: Issues

Portal Mapping

I Dedicated portal for each CPU,

I Same portal address on each CPU,I Such device mapping was not supported:

SMP vs DPAA: Issues

Portal Mapping

I Dedicated portal for each CPU,I Same portal address on each CPU,

I Such device mapping was not supported:

SMP vs DPAA: Issues

Portal Mapping

SMP vs DPAA: Issues

Portal Mapping

I Introduction of "shared" bit,

I Implemented using user-defined bits in TLB entry,I Only marked entries are propagated to other cores,I Private are set on each CPU.

SMP vs DPAA: Issues

Portal Mapping

I Introduction of "shared" bit,I Implemented using user-defined bits in TLB entry,

I Only marked entries are propagated to other cores,I Private are set on each CPU.

SMP vs DPAA: Issues

Portal Mapping

I Introduction of "shared" bit,I Implemented using user-defined bits in TLB entry,I Only marked entries are propagated to other cores,

I Private are set on each CPU.

SMP vs DPAA: Issues

Portal Mapping

SMP vs DPAA: Issues

Portal Configuration

I Has to be performed on each portal (CPU),I Only boot CPU can execute configuration during boot,I Other cores must initialize portals on demand:

I This may happen any time,I Portal configuration includes IRQ request,I But intr_event_create() may sleep!I Solution: Interrupt preallocation in XX Routines.

SMP vs DPAA: Issues

I Has to be performed on each portal (CPU),

I Only boot CPU can execute configuration during boot,I Other cores must initialize portals on demand:

SMP vs DPAA: Issues

I Has to be performed on each portal (CPU),I Only boot CPU can execute configuration during boot,

I Other cores must initialize portals on demand:

SMP vs DPAA: Issues

I This may happen any time,

I Portal configuration includes IRQ request,I But intr_event_create() may sleep!I Solution: Interrupt preallocation in XX Routines.

SMP vs DPAA: Issues

I This may happen any time,I Portal configuration includes IRQ request,

I But intr_event_create() may sleep!I Solution: Interrupt preallocation in XX Routines.

SMP vs DPAA: Issues

I This may happen any time,I Portal configuration includes IRQ request,I But intr_event_create() may sleep!

I Solution: Interrupt preallocation in XX Routines.

SMP vs DPAA: Issues

Portal Interrupts

I Portal Interrupts must be bound to particular CPU,I Solution: Interrupt thread binding layer in XX Routines.

SMP vs DPAA: Issues

Portal Interrupts

I Portal Interrupts must be bound to particular CPU,

I Solution: Interrupt thread binding layer in XX Routines.

SMP vs DPAA: Issues

Portal Interrupts

I Portal Interrupts must be bound to particular CPU,I Solution: Interrupt thread binding layer in XX Routines.

Other Peripherals

I PCI Express Bus,I USB Controller (EHCI compliant),I SD/MMC Controller,I I2C Controller,I IDMA Controller.

Other Peripherals

I PCI Express Bus,

I USB Controller (EHCI compliant),I SD/MMC Controller,I I2C Controller,I IDMA Controller.

Other Peripherals

I PCI Express Bus,I USB Controller (EHCI compliant),

I SD/MMC Controller,I I2C Controller,I IDMA Controller.

Other Peripherals

I PCI Express Bus,I USB Controller (EHCI compliant),I SD/MMC Controller,

I I2C Controller,I IDMA Controller.

Other Peripherals

I PCI Express Bus,I USB Controller (EHCI compliant),I SD/MMC Controller,I I2C Controller,

I IDMA Controller.

Other Peripherals

I PCI Express Bus,I USB Controller (EHCI compliant),I SD/MMC Controller,I I2C Controller,I IDMA Controller.

Current State and Results

I Supported chips: P2041, P3041 and P5020 (in 32-bitmode),

I Simple iperf test:

I Speed: 897 Mbit/sI CPU Utilization: 30%,I Of which 90% was interrupt servicing.

I Simple iperf test:I Speed: 897 Mbit/s

I CPU Utilization: 30%,I Of which 90% was interrupt servicing.

I Simple iperf test:I Speed: 897 Mbit/sI CPU Utilization: 30%,

I Of which 90% was interrupt servicing.

I Simple iperf test:I Speed: 897 Mbit/sI CPU Utilization: 30%,I Of which 90% was interrupt servicing.

p3041# vmstat -iinterrupt total rateirq121: bman0 1 0irq120: qman0 2784930 3584irq122: qman0 2194130 2823irq124: qman0 2263079 2912irq126: qman0 2148167 2764(...)

Future work

I More networking features:

I Pooling Mode,I Hardware Checksumming,I Jumbo Frames,

I More peripherals:

I Pattern Matching Engine,I Security Engine,I SATA Controller.

Future work

I More networking features:

I Pooling Mode,I Hardware Checksumming,I Jumbo Frames,

I More peripherals:

Future work

I More networking features:I Pooling Mode,

I Hardware Checksumming,I Jumbo Frames,

I More peripherals:

Future work

I More networking features:I Pooling Mode,I Hardware Checksumming,

I Jumbo Frames,I More peripherals:

Future work

I More networking features:I Pooling Mode,I Hardware Checksumming,I Jumbo Frames,

I More peripherals:

Future work

I More peripherals:

Future work

I More peripherals:I Pattern Matching Engine,

I Security Engine,I SATA Controller.

Future work

I More peripherals:I Pattern Matching Engine,I Security Engine,

I SATA Controller.

Future work

I More peripherals:I Pattern Matching Engine,I Security Engine,I SATA Controller.

Acknowledgments

I Michał Dubiel (Semihalf),I Rafał Jaworowski (Semihalf, The FreeBSD Project),I Phil Brownfield (Freescale)I Zbigniew Bodek, Piotr Nowak, Tomasz Nowicki, JanSięka, Łukasz Wójcik (all Semihalf).

Acknowledgments

I Michał Dubiel (Semihalf),

I Rafał Jaworowski (Semihalf, The FreeBSD Project),I Phil Brownfield (Freescale)I Zbigniew Bodek, Piotr Nowak, Tomasz Nowicki, JanSięka, Łukasz Wójcik (all Semihalf).

Acknowledgments

I Michał Dubiel (Semihalf),I Rafał Jaworowski (Semihalf, The FreeBSD Project),

I Phil Brownfield (Freescale)I Zbigniew Bodek, Piotr Nowak, Tomasz Nowicki, JanSięka, Łukasz Wójcik (all Semihalf).

Acknowledgments

I Michał Dubiel (Semihalf),I Rafał Jaworowski (Semihalf, The FreeBSD Project),I Phil Brownfield (Freescale)

I Zbigniew Bodek, Piotr Nowak, Tomasz Nowicki, JanSięka, Łukasz Wójcik (all Semihalf).

Acknowledgments

I Michał Dubiel (Semihalf),I Rafał Jaworowski (Semihalf, The FreeBSD Project),I Phil Brownfield (Freescale)I Zbigniew Bodek, Piotr Nowak, Tomasz Nowicki, JanSięka, Łukasz Wójcik (all Semihalf).

The End

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freebsd on freescale qoriq data path acceleration architecture devices · 2015-12-16 · freebsd on...

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