finite state machines - web02web02.gonzaga.edu/faculty/talarico/cp430/lec/fsm.pdf ·  ·...

FiniteStateMachines

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FSM

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nextstatestate

GenericStateMachineModel

GuidelinesforcodingFSMsinVHDL:

*Useseparateprocessesforsequentiallogicandcombinationallogic

*Useenumerateddatatypetolistallpossiblestates

(optional)(state registers)

StateMachine:keyidea

• StatemachinesareaneffectivemathematicalMoC thatallowtocharacterizeinanun-ambiguousandformalwaythebehaviorofasystem

• Goal:givenasetofexternalstimuliwewanttodesignasystemthatexhibitadesiredbehavior,i.e.thesystemmustbeabletoprocessthestimuli providedatitsinputstoproducecertainactions atitsoutputs

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SYSTEMinputs outputs

StateMachine:keyidea

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STATE,ACTIONS

checkstimuli

IfnecessarychangeSTATEandACTIONS

SystemBehavior:

stimuli inputs

actions outputs

actionsdependsonstimuli&state

Insummary:1. atanygiventimeyouare

inacertainstate,andperformcertainactions

2. monitorexternalstimuliand“decide”whatnextstateandactionsshouldbe

MoorestyleFSM

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NextstateC.L.

OutputC.L.

StateRegistersS.L.

clock reset(optional)

nextstate state outputsinputs

Theremaybeglitchesontheoutputs

MealystyleFSM

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NextstateC.L.

OutputC.L.StateRegisters

S.L.

clock reset(optional)

nextstatestate outputs

inputs

Theremaybeglitchesontheoutputsandtheoutputsmaylastlessthanonecycle

RegisteredOutputsFSMs

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PipelinedMealy

Noglitchesandtheoutputslastone cycle

NextstateC.L.

OutputC.L.StateRegisters

S.L.

clock reset(optional)

nextstatestateinputs

OutputRegistersS.L.

storedoutputs

RegisteredOutputsFSMs

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NextstateC.L.

OutputC.L.

StateRegistersS.L.

clock reset(optional)

nextstate statestoredoutputsinputs

OutputRegistersS.L.

Noglitchesandtheoutputslastoneclockcycle

Ifwewant,wecandefinitelypipeline“Moore”…

Registered(a.k.a stored)outputsFSMs

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NextstateC.L.

OutputCodedStateRegisters

clock reset(optional)

nextstatestate/outputs

inputs

Noglitches+outputsarefaster

Solution1:outputcodedMoore

Solution2:output“forecasting”

Usuallysolution2requireslessthinking

NOTE:withMooreFSMsispossibletogetregisteredoutputswithouthavingtoaddapipelinestageà outputsgetspeedupbyoneclockcycle!!!

DesignExample:EdgeDetector

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EdgeDetector• Designastatemachinetoimplementanedgedetector

Intuitivesolution:

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SYSTEMDIN

CLKPULSE

MoorestyleASM

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SYSTEMDIN

CLKPULSE

K.MapsforMoore’sFSM

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MealystyleASM

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SYSTEMDIN

CLKPULSE

K.MapsforMealy’s FSM

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MealyImplementation

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pulse~0

Mooreimplementation

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Mux0~0

Moorewithregisteredoutput

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Mux0~0

InthissimpleexampletheMoore’soutputregisteredFSMandthe“pipelined”MealyFSMhappentocoincides!

DesignExample:EdgeDetectorVHDLcoding

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Mealy’s FSM

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Moore’sFSM

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Moore’sstoredoutputFSM

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EdgeDetector:FunctionalSimulation

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FunctionalSimulation

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Mealy:

Moore:

Moorewithstoredoutput:

EdgeDetector:Testbench VHDLcode

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Testbench

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