finding the flow
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Finding the Flow
Planning and Executing
Verification Environments using
James Keithan
Convergence Verification
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Agenda
Introduction
DV Factors DV Tools
Flowchart Planning
Task Assignment xecu on
Checkpoints
Summary
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Introduction
Landscape
A lot of material written about this subject Most of which I agree with
Bio
First simulator language CAPS X
First HLV language Specman as first U.S. InSpec AE
Currently Sr. contributor in AVM, VMM, and OVM projects
usin Questa, VCS, and IncisiveIncisive
Goal
ProvideActionable steps for planning and execution
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DV Factors
To be in, lets look at the roblem
What about the design is important? Collect the specs, and read them
oo or unc ons, usses, an reg s ers
Talk to all stakeholders
Take notes
My pressure points follow
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DV Factors
What are the ma or factors?
Design size Design type
Model maturity
State space Resources
Other factors, important, but secondary from above
Prediction
Reuse
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DV Factors
What are the factors to consider?
Design size Simple isnt it? How big is the design?
ASICs and FPGAs both can exceed
practical simulations size constraints
Here we look for aspects in the design
Repetition
# and size of FIFOS Memory
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DV Factors
What are the factors to consider?
Design type Always the classic
a a over or a a runc er
Telecom etal. Mover
NOT TRUE Anymore
Most modern designs have aspects of both
This implies Multiple Layers of Checking
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DV Factors
What are the factors to consider?
Design type Therefore we consider - Number and Percentage
Number - How many different types of blocks
Note all IP, new, reused, and purchased
the classic split?
More Mover, generally easier
More Cruncher, harder prediction
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DV Factors
What are the factors to consider?
Interface Maturity Here the DV rubber meets the road
cqu r ng ransac or mo e s o en e ar es par
Do you have common interfaces?
PCIe DDR etc.
Or are you dealing with the next big thing? PLB6, New DRAM, etc.
These can increases factors of complexity,up to 10X
.
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DV Factors
What are the factors to consider?
Model Maturity Similar to Transactors with these differences:
They involve Prediction (vs. protocol)
Correctness model sources vary widely , ,
In the end you may have to write it yourself
Another whole project!
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DV Factors
What are the factors to consider? State Space Size
No This is where the DV rubber meets . .
- verification practice manager
This issues invades all areas of TB planning What stimulus do we need? Generate state space
Have we checked everything? Check state space
Are we done? Cover state space
Reg model becomes most important deliverable Every block should share one model
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DV Factors
What are the factors to consider?
Resources Human and Infrastructure
What is the comfort level of my people?
Do I have enough _______________ ? ,
Training
Technology
Consultants
Todays Verification challenges requires that
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DV Tools
We dont need more tools we need better automation
Gary Smith, DVCon 2008 Yes and No
u oma on s a rea y poss e you o yourse
I would add,
we need to know What tool to use How and When
Step back:
look at what kind of automation we want
Look at what tools we have Make practical decisions
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DV Tools
What do we do the most of?
Run simulations Debug simulations
Where can automation best help?
Running and Interpreting simulations
Given that, lets look at what is out there
vManagervManager
Runs tests, displays results
Highly customizable
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DV Tools
Simulators & Lan ua es
Certain assumptions for this paper; Use an Object Oriented Language -
os e y ys em er og
Testing through Random Generation of TLMs
Assertion coverage also key
Formal Verification
Use early, best on data Mover designs
Here, in my experience, the tools are ready,
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DV Tools
Simulators & Lan ua es
I use Incisive Enterprise Manager With OVM base library,
vPlan regression runner
OVM base class
SVA SystemVerilog Assertions
OOP
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Phases
Althou h not terribl ri id, each with si nificant overla ,
here is a list of recommended development phases: Plan & document
Basic monitors
Basic checks Advanced stimulus
Advanced monitors
Advanced checks
Regressions to closure
We will concentrate on
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Flowchart Planning
Flowchart Planning is:Defining testbench components, environments,
init ialization, and tests, through structured analysis ofthe designs block diagram
It does not directly produce thorough requirements Although it contributes to this effort
And Temporal Assertions
Flowchart Planning produces the Environment
- Planning provides a flow that quantifies effort
Starts with a High Level block diagram of the design
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Flowchart Planning
Ste s in the rocess, with an exam le to follow;
1. Make a block diagram of the design Keep it high level, include all external and major internal blocks
2. Flowchart Data flow in one copy
In, through and out of design
.
What directs data flow?
4. Flowchart Initialization sequence in yet another copy
Setup comes from where? Goes to where? How?
5. Identify locations for assertions
, ,
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Flowchart Planning
Ste s continued;
6. Cull data types from Data flow chart Group as much together as possible
7. Cull Device models from Control flow chart
This reveals the Interfaces [Transactors] needed
Also look for Data/Control overla
8. Cull State models from Initialization flow chart
Normally a full Register Model is needed
Helps define initialization sequences9. List all assertions, by functional block
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Flowchart Planning
Step 1: DCR Bus Interconnect example
block diagram
lBus
(OPB)
On-ChipPeripher
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Flowchart Planning
Ste s in the rocess
2. Flowchart Data flow in one copy Avoid too much detail
a or oc s on y
We want a sense where the data comes and goes
That is enough for now
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Flowchart Planning
Step 2: Data Flow
lBus(OPB)
On-ChipPeripher
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Flowchart Planning
Ste s in the rocess
3. Flowchart Control flow in another copy Control is that which starts, stops, or throttles Data
o n a za on a s o come
External factors that effect the design
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Flowchart Planning
Step 3: Control Flow
lBus(OPB)
On-ChipPeripher
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Flowchart Planning
Ste s in the rocess, with an exam le to follow;
4. Flowchart Initialization sequence in yet another copy How is the DUT setup to run?
ys ca rese an o ware eg s er oa s
In this case more detail Is better
Start looking for overlaps, data & control Keep separate for now
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Flowchart Planning
Step 4: Initialization Flow
lBus(OPB)
On-ChipPeripher
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Flowchart Planning
Ste s in the rocess
5. Identify locations for assertions These are temporal check over time
us pro oco s
Internal State Machines
Latency parameters
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Flowchart Planning
Step 5: Assertion Density
lBu
s(OPB)
On-ChipPeripher
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Flowchart Planning
Step 6: Cull Data types,eripheralBus(OPB)
From data flow,
to Define TransactionsPLB Transactions
On-Chip
Memory
Peripheral
Look to form larger groups Here we can group PLB & OPB
Instructions to Processor
OPB Transactions
different types
DCR Separate, quit different
Note: Re isters hold State
Bridge Data
DCR Transactions
Re ister Setu Data
Data/Control overlap
Peripheral data is ignored
Consider this environment partitioning
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Flowchart Planning
Step 7: Device ModelseripheralBus(OPB)
From Control Flow
ROM Model
On-Chip
PLB Transactors
OPB Transactors Check for other models;
needed but not directly in
Register Setup Data
PLB Arbiter prediction
Memory models
Peripherals are ignored to simplify
r ter pre ct on u o en severa o ese
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Flowchart Planning
Step 8: State ModelseripheralBus(OPB)
From Initialization Flow
Block Re ister Mirror
On-Chip
A class of regs for each block
Same Base Register Class
Here we are looking for two, often
overlapping state types
Cache State
Memory State
n a za on we ave o se up
before a test can run
Results device state updates
Form one or two state containers
depending on degree of overlap
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Task Assigning
From the revious exercise we list the tasks
Pull from each step the items that need building
Data flow gives Stimulus
ransac ons
Control flow gives models to exercise the design
Transactors Initialization flow gives State Model
Register Abstraction Layer
Assertion flow gives, . . . assertions!
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Task Assigning
From the revious exercise we Do Not et:
Requirements: Too high level
This Must be done & turned into Coverage
es s s: xcep n a za on
These still need to be done, in parallel with
testbench creation
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Task Assigning
Task and Effort estimates
Some general rules of thumb
Stimulus Classes man month each
Transactors 1 man month each internal
Transactors man month each vendor
Assertions ongoing but man month per
functional block
Functional coverage 1-2 man months perfunctional block
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Task Assigning
Tasks and Effort estimates
Pulling from flow chart
Transaction Level Models (TLMs)
rocessor a a
DCR Data
Transactors / Monitors ROM
PLB
DCR
Memory
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Task Assigning
Tasks and Effort estimates
Pulling from flow chart
State Containers
rocessor
Cache
Memory Each Blocks State space
Most likely register models
CPU
Arbiters
Bridges
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Task Assigning
Example Resource Allocation
. . . .
Ana Processor TLM CPU Prediction CPU Prediction CPU Test Writing
.
Claudette DCR TLM DCR Transactor DCR Transactor DCR Test Writing
anny ac e a e ransac or ransac or es r ng
Erika Mem. State PLB Transactor PLB Transactor PLB Test Writing
Fred OPB Transactor OPB Transactor Arbiter Prediction OPB Test Writing
Grace MEM Transactor MEM Transactor Bridge Prediction MEM Test Writing
Henri Blk n State Space Blk n State Space Assertion Writing ARB Test Writing
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Task Assigning
Other blocks that need assi nin
Our standard environment blocks
Starting, logging, stopping
ese are nc u e n ase c asses
Test running, Data collection
vMana er vMana er rovides this
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Execution
Tasks are assi ned, lets et to work
Now we use Carters Metric Based Verification Requirements entered into vPlan
Employ this, use phases, and checkpoints
As team arrives at them, fill out checklist
Becoming part of sign off deliverables
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Execution
Check oints are Ke to trackin ro ress
However, more checkpoints do not mean more visibality
Keep to logical milestones
My suggestions :
Modeling completion
Coverages > 90%
Closure
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Execution
Modeling completion checkpoint
This early checkpoint confirms development environment is
installed, approach is documented, and stimulus models compile
Checklist Item Details Date
Simulator Installed Version :Classes and calls documented Attach Doc.
Code Reviews completed Attach Doc.
Core constraints done Revision tag:All consumers acceptance Signoffs:
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Execution
Initialization running checkpoint
At this point simulations run and pass, code coverage is used as
the metric to measure progress. There are very few assertions orfunctional coverage yet
Checklist Item Details Date
Device initialization test passes Attach Log File:Code coverage report generated Attach Report:
Assertion list documented Attach Doc:
Functional coverage documented Attach Doc:
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Execution
Coverage > 90% checkpoint
At this point several simulations run, random generation is solid,
checks and assertions are all installed and all functional coverage
Checklist Item Details Date
Code coverage reviewed Report, waivers:Assertions implemented Report, Assertion Cov:
Functional coverage implement Report, Functional Cov:
Tests run with multiple seedsAll regressions pass all seeds
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Execution
Closure checkpoint
All coverpoints at 100% or waivered, Functional, Code and
Assertions. All tests pass with multiple random seeds.
Checklist Item Details Date
Functional coverage reviewed Attach Report, waivers:Assertions trigger and pass
Review all docs
Archive EnvironmentPost Mortem
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Summary
A Lot of material covered
Planning
Task Identification
Execution
Checkpointing Closure
Not Covered
Prediction Details
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2009 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, 1st Silicon Success Allegro Accelerating Mixed Signal Design Assura BuildGates Cadence Cadence
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