final presentation may 6, 2004 justin akagi - ee 396 marcus suzuki - ee 496 brent uyehara - ee 496...
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Final PresentationMay 6, 2004
Justin Akagi - EE 396Marcus Suzuki - EE 496Brent Uyehara - EE 496
TURFPro
Overview Background Information Overview of Project Project Objective What is TURFPro? Design Implementation and Testing Final Status Problems Encountered Future Goals
Background Information - ANITA
The ANITA project will examine an important quantum particle: the neutrino, the only known ultra-high-energy particle that can reach the earth with very little interaction with matter.
Background Information - Neutrinos It is one of the fundamental
particles (such as: e-) which make up our universe.
Understanding neutrinos will provide us with a better understanding of natural phenomena (ie: radioactive decays).
Neutrinos may provide the key to many mysteries of the cosmos.
General Overview of Project 256 channels of sampled data Major problem – massive amounts of data
data rates on the order of terabytes/second for continuous sampling
Achieve feasible data rates by: only recording samples during actual neutrino
events. adjusting the trigger threshold to filter out
noise/non-events.
What is TURFPro?
Trigger Unit for RF Prototype
Primary Objective: utilize the STRAW3 chip to create a servo-loop which will adjust the trigger thresholds dynamically.
Technical Overview of STRAW3 chip
Self-Triggered Recorder for Analog Waveforms ver. 3
CMOS full-custom integrated circuit Serves two functions:
triggering on fast bipolar pulses high-speed waveform sampling
Approach Implement and Test STRAW3 triggering
capabilities Load and successfully test the trigger with a
parallel to serial readout Measure trigger threshold curves
Design a servo-loop (feedback loop) Load DAC values from Linux machine Read DAC values and corresponding voltages Evaluate effectiveness of dynamic threshold
settings for recording neutrino events
The DAC Each of 64 channels has an
individually adjustable threshold voltage value
A two-stage 20 bit DAC is used to adjust this voltage level
12 bit main stage – LSB ~ 0.6 mV 8 bit trim – LSB ~ 80 uV
How the Thresholds work
Four levels: High-High, Low-High, Low-Low, High-Low
Reasoning: When an event occurs, the input signal, Vin, will exceed one or more of the trigger thresholds.
Loading DAC Values
Testing the serial transfer of data (from the CPLD to the STRAW3): Loaded a Parallel-to-Serial Converter
into the CPLD firmware Hardcoded values to be sent to the
STRAW3 chip Read out values from STRAW3 Evaluated input/output differences
Loading DAC Values Testing the serial transfer of data
(from the CPLD to the STRAW3): Loaded a Parallel-to-Serial Converter
into the CPLD firmware Hardcoded values to be sent to the
STRAW3 chip Read out values from STRAW3 Evaluated differences between input
and output values
CPLD DAC to Voltage MapBits Voltage
All Low 0.324 V
Bit 0 High 0.517 V
Bit 1 High 0.370 V
Bit 2 High 0.337 V
Bit 3 High 0.324 V
Bit 4 High 0.324 V
Bit 5 High 0.324 V
Bit 6 High 0.324 V
Bit 7 High 0.324 V
Bit 8 High 0.324 V
Bit 9 High 0.324 V
Bit 10 High 0.324 V
Bit 11 High 0.324 V
Bit 12 High 0.324 V
Bit 13 High 0.324 V
Bit 14 High 0.324 V
Bit 15 High 0.324 V
Bit 16 High 0.324 V
Bit 17 High 0.324 V
Bit 18 High 1.670 V
Bit 19 High 0.818 V
Bit Combinations
Voltage delta
Bit 18 + 19 2.094 0.424 V
Bit 18 + 0 1.818 0.148 V
Bit 18 + 1 1.715 0.045 V
Bit 18 + 2 1.694 0.024 V
Bit 18 + 3 1.686 0.013 V
Bit 18 + 4 1.673 0.003 V
Bit 18 + 5 1.672 0.001 V
Bit 18 + 6 1.673 -0.001 V
Pattern Target Voltage Actual
All Low 0.323 0.424 V
Bit 1-17 High 0.4 0.148 V
Bit 0 High 0.5 0.045 V
Bit 0-4 High 0.6 0.024 V
Bit 19 High 0.7 0.013 V
Control Lines from CPU
GPIO 0 – Trigger GPIO 1 – SIN GPIO 7 – SCLK GPIO 8 – DCLK
GPIO0 PASS1
GPIO1 PASS3
GPIO7 PASS5
GPIO8 PASS6
CTRL_TOP
GPIO0 PASS1
GPIO1 PASS3
GPIO7 PASS5
GPIO8 PASS6
CTRL_SW
GPIO0 PASS1
GPIO1 PASS3
GPIO7 PASS5
GPIO8 PASS6
STRAW3_TOP
Main DAC Mapping
DAC Value Voltage16 0.4132 0.41148 0.41164 0.41380 0.41496 0.415
112 0.415128 0.421144 0.421160 0.422176 0.423192 0.425208 0.425224 0.426240 0.426256 0.445272 0.446288 0.447304 0.447320 0.449336 0.45352 0.451368 0.452384 0.457400 0.459416 0.46432 0.46
DAC Value vs. Voltage
0
0.1
0.2
0.3
0.4
0.5
0.6
0 100 200 300 400 500 600
DAC Value
Vo
ltag
e
Series1
Main DAC Complete MapDAC Value vs. Analog Voltage
0
0.5
1
1.5
2
2.5
0 500 1000 1500 2000 2500 3000 3500 4000 4500
DAC Value
Vo
ltag
e
Series1
R-2R Mismatch
840 mV
Fine-adjust DAC MapFine-adjust DAC Map
800
820
840
860
880
900
920
940
960
0 50 100 150 200 250 300
Fine Adjust DAC Value
Vo
ltag
e (m
V)
Series1
15mV
Measurement of Noise on a Single Channel
815
820
825
830
835
840
845
850
855
0 200 400 600 800 1000 1200 1400
Series1
15 mV
Final Status Loaded and successfully tested the
trigger with a parallel to serial readout Measured trigger threshold curves Designed a servo-loop (feedback loop)
Loaded DAC values from Linux machine Read DAC values and corresponding
voltages Made a DAC to voltage Map.
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