figure 2.1. a binary switch. x1=x0= (a) two states of a switch s x (b) symbol for a switch

Figure 2.1. A binary switch.

x 1 = x 0 =

(a) Two states of a switch

S

x

(b) Symbol for a switch

Figure 2.2. A light controlled by a switch.

(a) Simple connection to a battery

S

x

(b) Using a ground connection as the return path

L Battery Light

x Power supply

S L

Figure 2.3. Two basic functions.

(a) The logical AND function (series connection)

S

x 1 LPowersupply

S

x 2

S

x 1

LPowersupply S

x 2

(b) The logical OR function (parallel connection)

Light

Light

Figure 2.4. A series-parallel connection.

S

x 1

L Power supply S

x 2

Light

S

x 3

Figure 2.5. An inverting circuit.

S x L Power supply

R

Figure 2.6. A truth table for AND and OR.

Figure 2.7. Three-input AND and OR.

x 1 x 2

x n

x 1 x 2 x n + + + x 1 x 2

x 1 x 2 +

x 1 x 2

x n

x 1 x 2

x 1 x 2 x 1 x 2 x n

(a) AND gates

(b) OR gates

x x

(c) NOT gateFigure 2.8. The basic gates.

Figure 2.9. An OR-AND function.

x 1 x 2 x 3

f x 1 x 2 + x 3 =

x 1

x 2

1 1 0 0

f 0 0 0 1

1 1 0 1

0 0 1 1

0 1 0 1

(a) Network that implements f x 1 x 1 x 2 + =

x 1 x

2 f x 1 x

2 , ( )

0 1 0 1

0 0 1 1

1 1 0 1

(b) Truth table for f

A

B

Figure 2.10a. Logic network.

1 0 1 0 1 0 1 0 1 0

x 1

x 2

A

B

f Time

(c) Timing diagram

1 1 0 0 0 0 1 1

1 1 0 1 0 1 0 1 g

x 1

x 2

(d) Network that implements g x 1 x 2 + =

Figure 2.10b. Logic network.

Figure 2.11. Proof of DeMorgan’s theorem.

Figure 2.12. The Venn diagram representation.

Please see “portrait orientation” PowerPoint file for Chapter 2

Figure 2.13. Verification of the distributive property.

Please see “portrait orientation” PowerPoint file for Chapter 2

Please see “portrait orientation” PowerPoint file for Chapter 2

Figure 2.14. Verification example.

Figure 2.15. A function to be synthesized.

f

(a) Canonical sum-of-products

f

(b) Minimal-cost realization

x 2

x 1

x 1 x 2

Figure 2.16. Two implementations of the function in Figure 2.15.

Figure 2.17. Three-variable minterms and maxterms.

Figure 2.18. A three-variable function.

Figure 2.19. Two realizations of the function in Figure 2.18.

f

(a) A minimal sum-of-products realization

f

(b) A minimal product-of-sums realization

x1

x2

x3

x2

x1x3

Figure 2.20. NAND and NOR gates.

x 1 x 2

x n

x 1 x 2 x n + + + x 1 x 2

x 1 x 2 +

x 1 x 2

x n

x 1 x 2

x 1 x 2 x 1 x 2 x n

(a) NAND gates

(b) NOR gates

Figure 2.21. DeMorgan’s theorem in terms of logic gates.

x 1 x 2

x 1

x 2

x 1 x 2

x 1 x 2

x 1

x 2

x 1 x 2

x 1 x 2 x 1 x 2 + = (a)

x 1 x 2 + x 1 x 2 = (b)

Figure 2.22. Using NAND gates to implement a sum-of-products.

x 1 x 2 x 3 x 4 x 5

x 1 x 2 x 3 x 4 x 5

x 1 x 2 x 3 x 4 x 5

Figure 2.23. Using NOR gates to implement a product-of sums.

x 1 x 2

x 3 x 4 x 5

x 1 x 2

x 3 x 4 x 5

x 1 x 2

x 3 x 4 x 5

Figure 2.24. Truth table for a three-way light control.

Figure 2.25a. SOP implementation of the three-way light control.

f

(a) Sum-of-products realization

x 1 x 2 x 3

Figure 2.25b. POS implementation of the three-way light control.

(b) Product-of-sums realization

f

x 1 x 2 x 3

0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 0 1 1 1 1

(a) Truth table

f

x 1

x 2 s

f

s

x 1 x 2

0 1

(c) Graphical symbol

(b) Circuit

0 1

(d) More compact truth-table representation

s x1 x2 f (s, x1, x2)

f (s, x1, x2)sx1

x2

Figure 2.26. Multiplexer.

Figure 2.27. Screen capture of the Waveform Editor.

Figure 2.28. Screen capture of the Graphic Editor.

Figure 2.29. The first stages of a CAD system.

Please see “portrait orientation” PowerPoint file for Chapter 2

Figure 2.30. A simple logic function.

f

x3

x1x2

Figure 2. 31. Verilog code for the circuit in Figure 2.30.

module example1 (x1, x2, x3, f);input x1, x2, x3;output f;

and (g, x1, x2);not (k, x2);and (h, k, x3);or (f, g, h);

 endmodule

Figure 2.32. Verilog code for a four-input circuit.

module example2 (x1, x2, x3, x4, f, g, h);input x1, x2, x3, x4;output f, g, h;

 and (z1, x1, x3);and (z2, x2, x4);or (g, z1, z2);or (z3, x1, ~x3);or (z4, ~x2, x4);and (h, z3, z4);or (f, g, h);

 endmodule 

Figure 2.33. Logic circuit for the code in Figure 2.32.

g

h

x 3

x 1

x 2 x 4

f

Figure 2.34. Using the continuous assignment to specify the circuit in Figure 2.30.

module example3 (x1, x2, x3, f);input x1, x2, x3;output f ;

assign f = (x1 & x2) | (~x2 & x3);

endmodule

Figure 2.35. Using the continuous assignment to specify the circuit in Figure 2.33.

module example4 (x1, x2, x3, x4, f, g, h);input x1, x2, x3, x4;output f, g, h;

assign g = (x1 & x3) | (x2 & x4);assign h = (x1 | ~x3) & (~x2 | x4);assign f = g | h;

endmodule

Figure 2.36. Behavioral specification of the circuit in Figure 2.30.

// Behavioral specificationmodule example5 (x1, x2, x3, f);

input x1, x2, x3;output f ;reg f ;

 always @(x1 or x2 or x3)

if (x2 == 1)f = x1;

elsef = x3;

endmodule

x 1 x 2

x 3

x 4

(a)

x 1 x 2

x 3

x 4

(b)

Figure P2.1. Two attempts to draw a four-variable Venn diagram.

x 3

x 2 x 1

x 4

x 3

x 2 x 1

m 0

m 1 m 2

Figure P2.2. A four-variable Venn diagram.

Figure P2.3. A timing diagram representing a logic function.

1 0 1 0 1 0 1 0

x 1

x 2

Time

x 3

f

1 0 1 0 1 0 1 0

x 1

x 2

Time

x 3

f

Figure P2.4. A timing diagram representing a logic function.