fet small-signal analysis. fet small-signal model transconductance the relationship of v gs (input)...

FET Small-Signal Analysis

FET Small-Signal Model

Transconductance

The relationship of VGS (input) to ID (output) is called transconductance.

The transconductance is denoted gm.

GS

Dm

V

Ig

Transfer Curve

Graphical Determination of gm

Mathematical Definition of gm

GS

Dm

VΔ

Ig

P

GS

P

DSSm

V

V1

V

2Ig

P

DSSm0

V

2Ig

P

GSm0m

V

V1gg

DSS

D

P

GS

I

I

V

V1

DSS

Dm0

P

GSm0m

I

Ig)

V

V(1gg

Using differential calculus

Maximum gm at VGS =0V:

Effect of ID on gm for

FET Impedance

ΩZi

osdo

y

1rZ

constantVI

Vr

GSD

DSd

Input Impedance Zi:

• Very large to assume input terminal approximate an open circuit

Output Impedance Zo:

yos: admittance equivalent circuit parameter listed on FET specification sheets.

FET Specification

FET AC Equivalent Circuit

JFET Fixed-Bias Configuration

The input is on the gate and the output is on the drain.

JFET Fixed-Bias Configuration

Once again: same step as BJT to redraw the network to AC equivalent circuit.

Capacitor – short circuit

DC batteries VGG and VDD are set to zero volts by a short-circuit equivalent

AC Equivalent Circuit

AC Equivalent Circuit

Impedances

GRZi dD r||RZo

Dd D 10RrRZo

Input Impedance: Output Impedance:

Voltage Gain

)R||(rgVi

VoAv Ddm

Dd Dm 10RrRg

Vi

VoAv

Phase Relationship

A CS amplifier configuration has a 180-degree phase shift between input and output.

Example

Fixed-bias configuration has an operating point defined by VGSQ = -2V and IDQ = 5.625 mA, with IDSS = 10mA and VP = -8V. The value of yos is provided as 40 µS. Determine:

a) gm

b) Zi

c) Zo

d) AV

e) AV ignoring the effects of rd

Solution

JFET CS Self-Bias Configuration

This is a CS amplifier configuration therefore the input is on the gate and the output is on the drain.

AC Equivalent Circuit

Impedances

Input Impedance:

Output Impedance:

GRZi

Dd R||rZo DdD 10RrRZo

Voltage Gain

)R||(rgAv Ddm

Dd Dm 10RrRgAv

Phase Relationship

A CS amplifier configuration has a 180-degree phase shift between input and output.

JFET CS Self-Bias Configuration – Unbypassed Rs

If Cs is removed, it affects the gain of the circuit.

AC Equivalent Circuit

Impedances

Input Impedance:

Output Impedance:

Impedances

Voltage Gain

Voltage Gain

Example

Solution

Solution

JFET CS Voltage-Divider Configuration

This is a CS amplifier configuration therefore the input is on the gate and the output is on the drain.

AC Equivalent Circuit

Impedances

Input Impedance: 21 R||RZi

Dd R||rZo

DdD 10RrRZo

Output Impedance:

Voltage Gain

)R||(rgAv Ddm

Dd Dm 10RrRgAv

JFET Source Follower (Common-Drain) Configuration

In a CD amplifier configuration the input is on the gate, but the output is from the source.

AC Equivalent Circuit

Impedances

Input Impedance: GRZi

mSd

g

1||R||rZo

SdmS 10Rr g

1||RZo

Output Impedance:

Voltage Gain

)R||(rg1

)R||(rg

Vi

VoAv

Sdm

Sdm

SdSm

Sm

10Rr Rg1

Rg

Vi

VoAv

Phase Relationship

A CD amplifier configuration has no phase shift between input and output.

JFET Common-Gate Configuration

The input is on source and the output is on the drain.

AC Equivalent Circuit

Impedances

Applying Kirchhoff’s voltage law around the output perimeter and Kirchhoff’s current law at node a ::

Impedances

Input Impedance:

Output Impedance:

dm

DdS

rg1

Rr||RZi Ddm

S 10Rr )g1(||RZi

dD r||RZo DdD 10RrRZo

Voltage Gain

d

D

d

DDm

r

R1

r

RRg

Vi

VoAv

Dd Dm 10RrRgAv

Applying Kirchhoff’s current law at node b ::

Phase Relationship

A CG amplifier configuration has no phase shift between input and output.

Depletion-Type MOSFETs

1. D-MOSFETs have similar AC equivalent models.

2. The only difference is that VSGQ can be positive for n-channel devices and negative for p-channel devices.

3. This means that gm can be greater than gm0.

D-MOSFET AC Equivalent Model

Example• Find – VGSQ and IDQ

– Determine gm and compare to gm0

– rd

– Find Zi, Zo, Av

Enhancement-Type MOSFETs

There are two types of E-MOSFETs:

nMOS or n-channel MOSFETspMOS or p-channel MOSFETs

E-MOSFET AC Equivalent Model

gm and rd can be found in the specification sheet for the FET.

Forward transfer admittance

E-MOSFET CS Drain-Feedback Configuration

AC Equivalent Circuit

Impedances

Input Impedance:

)R||(rg1

R||rRZi

Ddm

DdF

DdDdFDm

F

10Rr,R||rR Rg1

RZi

DdF R||r||RZo

DdDdF D 10Rr,R||rRRZo

Output Impedance:

The calculation

DdDdFDm

F

ddm

midii

ii

GSDd

oGSmi

10Rr,R||rR Rg1

RZi

,

RrRrg1

,

gIRrVI

that,find '

VI

V Rr

VVgI

D,point at LawCurrent sKirchoff' From

so

RIV

grearrangin

RV

llWe

RV

and

V

DFiDi

F

iD

F

o

in

DdF R||r||RZo

DdDdF D 10Rr,R||rRRZo

DdDdFDm

FDdm

FDd

m

F

FDd

m

F

i

oV

m

Fi

FDdo

Dd

oGSm

F

oi

F

oii

inGSDd

oGSmi

10Rr,R||rRRg

RRrg

RRr

1

gR1

R1

Rr1

gR1

VV

A

so

gR1

VR1

Rr1

V

grearrangin

Rr

VVgR

VV

that, findllWe

RVVI

and

VV Rr

VVgI

D, point at Law Current sKirchoff' From

,

,

'

The AC analysis of E-MOSFET

ThGSGSQ

2ThGSGS

GSGS

Dm

m

GS

Dm

m

2ThGSGSD

VVk2

VVkdV

dVI

g

point; operating theat

g determine willequation above of derivation The

VI

g

stics,characteri

drain of slope theby defined is g thatknow We

VVkI

below; as is voltagegcontrollin

and current output between iprelationsh The

Remember that, the biasing arrangement are limited for E-MOSFET

Voltage Gain

)R||r||(RgAv DdFm

DdDdF Dm 10Rr,R||rRRgAv

Phase Relationship

This is a CS amplifier configuration therefore it has 180-degree phase shift between input and output.

Do it•Determine input and output and also AV

impedance for k=0.3X10-3

10MΩ

Vi

Vo

2.2kΩ

+VDD (+16V)

VGS(Th)=3Vrd=100kΩ

Zi

E-MOSFET CS Voltage-Divider Configuration

AC Equivalent Circuit

Impedances

Input Impedance:

Output Impedance:

21 R||RZi

Dd R||rZo

Dd D 10RrRZo

Voltage Gain

)R||(rgAv Ddm

Dd Dm 10RrRgAv

Phase Relationship

This is a CS amplifier configuration therefore it has 180-degree phase shift between input and output.

Solution

E-MOSFET CS Voltage-Divider Configuration

AC Equivalent Circuit

Impedances

Input Impedance: [Formula 9.52]

Output Impedance: [Formula 9.53]

[Formula 9.54]

21 R||RZiDd R||rZo

Dd D 10RrRZo

Voltage Gain

[Formula 9.55]

[Formula 9.56]

)R||(rgAv Ddm

Dd Dm 10RrRgAv

Summary Table

Summary Table

Try yourself•Design a self-bias network that have gain of 10. The device should be biased at VGSQ=1/3VP

10MΩ

Vi

Vo

Rs

RD

+VDD (+20V)

IDSS =12mAVP=-3Vrd=40kΩ

Solution

To be continued……