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fakultät für informatikinformatik 12
technische universität dortmund
Evaluation and Validation
Peter MarwedelTU Dortmund, Informatik 12
Germany
2009/12/09
Gra
phic
s: ©
Ale
xand
ra N
olte
, Ges
ine
Mar
wed
el, 2
003
© These slides use Microsoft cliparts. All Microsoft restrictions apply.
- 2 -technische universitätdortmund
fakultät für informatik
p. marwedel, informatik 12, 2009
Structure of this course
2:Specification
3: ES-hardware
4: system software (RTOS, middleware, …)
8:Test
5: Validation & Evaluation (energy, cost, performance, …)
7: Optimization
6: Application mapping
App
licat
ion
Kno
wle
dge Design
repository Design
Numbers denote sequence of chapters
- 3 -technische universitätdortmund
fakultät für informatik
p. marwedel, informatik 12, 2009
Performance evaluation
Estimated cost and performance values:Difficult to generate sufficiently precise estimates;Balance between run-time and precision
Accurate cost and performance values:Can be done with normal tools(such as compilers).As precise as the input data is.
π x
We need to compute average and worst case execution times
- 4 -technische universitätdortmund
fakultät für informatik
p. marwedel, informatik 12, 2009
Thiele’s real-time calculus (RTC)/ Modular performance analysis (MPA) - Arrival curves -
1
2
3
T 2T 3T
u
1
2
3
T 2T 3T
u
T-J T+J
periodic event stream periodic event stream with jitter
Arrival curves describe the maximum and minimum number of events arriving in some time interval
Examples
- 5 -technische universitätdortmund
fakultät für informatik
p. marwedel, informatik 12, 2009
Thiele’s real-time calculus (RTC)/ Modular performance analysis (MPA) - Service curves -
Service curves u resp. ℓ describe the maximum and minimum service capacity available in some time interval
s
T
bandwidth bTDMA bus
Ts T-s T+s
bs
2T
u
Example:
- 6 -technische universitätdortmund
fakultät für informatik
p. marwedel, informatik 12, 2009
Thiele’s real-time calculus (RTC)/ Modular performance analysis (MPA) - Workload characterization -
u resp. ℓ describe the maximum and minimum service capacity required as a function of the number e of events
Example
1 2 3
4
8
12
16
e
WCET=4
BCET=3
u
ℓ (Defined only for an integer number of events)
- 7 -technische universitätdortmund
fakultät für informatik
p. marwedel, informatik 12, 2009
Workload required for incoming stream
uuu
Incoming workload
Upper and lower bounds on the number of events
uu 1)(
1)(
- 8 -technische universitätdortmund
fakultät für informatik
p. marwedel, informatik 12, 2009
Thiele’s real-time calculus (RTC)/ Modular performance analysis (MPA) - System of real time components -
u
,
RTC
RTC’
','
u
RTC”
…
','
u
u
,
Incoming event streams and available capacity are transformed by real-time components:
Theoretical results allow the computation of properties of outgoing streams
- 9 -technische universitätdortmund
fakultät für informatik
p. marwedel, informatik 12, 2009
Thiele’s real-time calculus (RTC)/ Modular performance analysis (MPA) - Transformation of arrival and service curves
Resulting arrival curves:
Remaining service curves:
Where: )()(inf ugutftgf
tu
0
)()(inf ugutftgfu
0
0
uu'
0
u
'
)()(sup ugutftgftu
0
)()(sup ugutftgfu
0
- 10 -technische universitätdortmund
fakultät für informatik
p. marwedel, informatik 12, 2009
Thiele’s real-time calculusRemarks
Details of the proofs can be found in relevant references Results also include bounds on buffer sizes and on
maximum latency. Theory has been extended into various directions,
e.g. for computing remaining battery capacities
- 11 -technische universitätdortmund
fakultät für informatik
p. marwedel, informatik 12, 2009
Application: In-Car Navigation System
Car radio with navigation systemUser interface needs to be responsiveTraffic messages (TMC) must be processed in a timely waySeveral applications may execute concurrently
© Thiele, ETHZ
- 12 -technische universitätdortmund
fakultät für informatik
p. marwedel, informatik 12, 2009
System Overview
NAV RAD
MMI
DB
Communication
© Thiele, ETHZ
- 13 -technische universitätdortmund
fakultät für informatik
p. marwedel, informatik 12, 2009
NAV RAD
MMI
DB
Communication
Use case 1: Change Audio Volume
< 200 ms
< 50 ms
© Thiele, ETHZ
- 14 -technische universitätdortmund
fakultät für informatik
p. marwedel, informatik 12, 2009
Use case 1: Change Audio Volume
© Thiele, ETHZ
CommunicationResourceDemand
- 15 -technische universitätdortmund
fakultät für informatik
p. marwedel, informatik 12, 2009
NAV RAD
MMI
DB
Communication
< 200 ms
Use case 2: Lookup Destination Address
© Thiele, ETHZ
- 16 -technische universitätdortmund
fakultät für informatik
p. marwedel, informatik 12, 2009
Use case 2: Lookup Destination Address
© Thiele, ETHZ
- 17 -technische universitätdortmund
fakultät für informatik
p. marwedel, informatik 12, 2009
NAV RAD
MMI
DB
Communication
Use case 3: Receive TMC Messages
< 1000 ms
© Thiele, ETHZ
- 18 -technische universitätdortmund
fakultät für informatik
p. marwedel, informatik 12, 2009
Use case 3: Receive TMC Messages
© Thiele, ETHZ
- 19 -technische universitätdortmund
fakultät für informatik
p. marwedel, informatik 12, 2009
Proposed Architecture Alternatives
NAV RAD
MMI22 MIPS
11 MIPS113 MIPS
NAV RAD
MMI22 MIPS
11 MIPS113 MIPS
RAD260 MIPS
NAVMMI
22 MIPS
RAD130 MIPS
MMINAV
113 MIPS
MMI260 MIPS
RADNAV
72 kbps
72 kbps 57 kbps
72 k
bps
72 k
bps
(A)
(E)(D)(C)
(B)
© Thiele, ETHZ
- 20 -technische universitätdortmund
fakultät für informatik
p. marwedel, informatik 12, 2009
Step 1: Environment (Event Steams)
Event Stream Model
e.g. Address Lookup(1 event / sec)
u
l
[s]
[events]
1
1
© Thiele, ETHZ
- 21 -technische universitätdortmund
fakultät für informatik
p. marwedel, informatik 12, 2009
Step 2: Architectural Elements
Event Stream Model
e.g. Address Lookup(1 event / sec)
Resource Model
e.g. unloaded RISC CPU(113 MIPS) ℓ=u
u
ℓ
[s]
[s][MIPS]
[events]
1
1
1
113
© Thiele, ETHZ
- 22 -technische universitätdortmund
fakultät für informatik
p. marwedel, informatik 12, 2009
Step 3: Mapping / Scheduling
Rate Monotonic Scheduling(Pre-emptive fixed priority scheduling):
Priority 1: Change Volume (p=1/32 s) Priority 2: Address Lookup (p=1 s) Priority 3: Receive TMC (p=6 s)
© Thiele, ETHZ
- 23 -technische universitätdortmund
fakultät für informatik
p. marwedel, informatik 12, 2009
Step 4: Performance Model
CPU1 BUS CPU3CPU2
Change Volume
Receive TMC
NAV RAD
MMI
Address Lookup
MMI NAV RAD
© Thiele, ETHZ
- 24 -technische universitätdortmund
fakultät für informatik
p. marwedel, informatik 12, 2009
Step 5: Analysis
CPU1 BUS CPU3CPU2
Change Volume
Receive TMC
NAV RAD
MMI
Address Lookup
MMI NAV RAD
© Thiele, ETHZ
- 25 -technische universitätdortmund
fakultät für informatik
p. marwedel, informatik 12, 2009
Analysis – Design Question 1
How do the proposed system architecturescompare in respect to end-to-end delays?
© Thiele, ETHZ
- 26 -technische universitätdortmund
fakultät für informatik
p. marwedel, informatik 12, 2009
End-to-end delays: (A) (E)(D)(C)(B)
Analysis – Design Question 1
0
50
100
Vol Key 2 Audio [ms]
0
50
100
Address Lookup [ms]0
500
1000
1500
TMC Decode [ms]
© Thiele, ETHZ
0
20
40
60
Vol Vis. 2 Audio [ms]
- 27 -technische universitätdortmund
fakultät für informatik
p. marwedel, informatik 12, 2009
Analysis – Design Question 2
How robust is architecture A?Where is the bottleneck of this architecture?
NAV RAD
MMI22 MIPS
11 MIPS113 MIPS
72 kbps
(A)
© Thiele, ETHZ
- 29 -technische universitätdortmund
fakultät für informatik
p. marwedel, informatik 12, 2009
TMC delay vs. MMI processor speed:
Analysis – Design Question 2
NAV RAD
MMI22 MIPS
11 MIPS113 MIPS
72 kbps
(A)
26.4 MIPS
© Thiele, ETHZ
- 30 -technische universitätdortmund
fakultät für informatik
p. marwedel, informatik 12, 2009
Analysis – Design Question 3
Architecture D is chosen for further investigation.
How should the processors be dimensioned?
RAD130 MIPS
MMINAV
113 MIPS72
kbp
s(D)
© Thiele, ETHZ
- 31 -technische universitätdortmund
fakultät für informatik
p. marwedel, informatik 12, 2009
RAD130 MIPS
MMINAV
113 MIPS
72 k
bps
33 MIPS29 MIPS
Analysis – Design Question 3
dmax = 200
dmax = 1000
dmax = 50
dmax = 200
© Thiele, ETHZ
- 32 -technische universitätdortmund
fakultät für informatik
p. marwedel, informatik 12, 2009
Conclusions
Easy to construct models (~ half day) Evaluation speed is fast and linear to model complexity
(~ 1s per evaluation) Needs little information to construct early models
(Fits early design cycle very well) Even though involved mathematics is very complex, the
method is easy to use (Language of engineers)
© Thiele, ETHZ
- 33 -technische universitätdortmund
fakultät für informatik
p. marwedel, informatik 12, 2009
Acknowledgement and References
The presentation contains contributions by Samarjit Chakraborty (NUS) Simon Künzli, Ernesto Wandeler, Alexander
Maxiaguine (ETHZ) Andreas Herkersdorf, Patricia Sagmeister (IBM) Jonas Greutert (Netmodule)
Many publications are available from http://www.tik.ee.ethz.ch/~thiele
© Thiele, ETHZ
- 34 -technische universitätdortmund
fakultät für informatik
p. marwedel, informatik 12, 2009
SYMTA
SYMTA (Ernst, TU Braunschweig) works with standard streams (periodic, periodic with jitter streams) and focuses on computing end-to-end guarantees in multiprocessor based systems
See www.symtavision.com
- 35 -technische universitätdortmund
fakultät für informatik
p. marwedel, informatik 12, 2009
Worst/best case execution times (1)
WCET
Actuall
y pos
sible
worst c
ase
Observ
ed ex
ecuti
on tim
e
Actuall
y bes
t pos
sible
ex. ti
me
BCET'
WCET’ (t
ighter
boun
d)
BCET
t
Oth
er a
utho
rs
WCET
BCET
Estimate
d WCET
Esti
mated
BCETFeasibleexecution
times
Observ
ed W
CET
Def
initi
on u
sed
in th
is c
ours
e
Nextslide
- 36 -technische universitätdortmund
fakultät für informatik
p. marwedel, informatik 12, 2009
Worst/best case execution times (2)
Requirements on WCET estimates: Safeness: WCET WCETEST! Tightness: WCETEST – WCET minimal
© h. falk/p. marwedel
WCETEST
- 37 -technische universitätdortmund
fakultät für informatik
p. marwedel, informatik 12, 2009
Worst case execution times (3)
Complexity: in the general case: undecidable if a bound exists. for restricted programs: simple for “old“ architectures,
very complex for new architectures with pipelines, caches, interrupts, virtual memory, etc.
Approaches: for hardware: requires detailed timing behavior for software: requires availability of machine programs;
complex analysis (see, e.g., www.absint.de)
Presentation by R. Wilhelm @ FEST (DVD in German), starting at min. 31:35 min.-47:00
- 38 -technische universitätdortmund
fakultät für informatik
p. marwedel, informatik 12, 2009
WCET estimation:AiT (AbsInt)
Executable program
CFG-Builder
Loop Trafo
AIP File ILP-Generator
ILP-Solver
EvaluationWCETVisuali-zation
Loop Bounds
Sta
tic a
naly
zer
Value Analyzer
Cache/Pipeline Analyzer
PER-File
CRL-File
Path Analysis
- 39 -technische universitätdortmund
fakultät für informatik
p. marwedel, informatik 12, 2009
WCET estimation for caches
Behavior at program joinsWorst case
Best case
{c} {e} {a} {d}
{a} {} {c,f} {d}
{c} {e} {a} {d}
{a} {c,f} {} {d}
{} {} {a,c} {d}
{a,c} {e,f} {} {d}
Intersection+max. age
Union+min. age
Tag Index Offset
LRU-based replacement
= = = =
Address
Movie: Presentation by Reinhard Wilhelm @ Freiburg ES days (German)
- 40 -technische universitätdortmund
fakultät für informatik
p. marwedel, informatik 12, 2009
Energy models
Tiwari (1994): Energy consumption within processors
Simunic (1999): Using values from data sheets. Allows modeling of all components, but not very precise.
Russell, Jacome (1998): Measurements for 2 fixed configurations
Steinke et al., UniDo (2001): mixed model using measurements and prediction
Jouppi (1996): Energy consumption of caches predicted by CACTI.
- 41 -technische universitätdortmund
fakultät für informatik
p. marwedel, informatik 12, 2009
Steinke’s model
E.g.: ATMEL board with ARM7TDMI and ext. SRAM
DataMemory
InstructionMemory
IAddr
VDD
ALU
Multi-plier
BarrelShifter
Register File
Instr. Decoder& Control Logic
Inst
rImm
RegValue
Reg#
Opcode
ARM7DAddr
mA mA
Data
Instr
h-costs, address bus, CPU + memory current
110
115
120
125
130
135
140
145
150
0 5 10 15 20
Hamming-Distance
Cur
rent
[mA
]
Read
Write
- 42 -technische universitätdortmund
fakultät für informatik
p. marwedel, informatik 12, 2009
CACTI model
Comparison with SPICE
Cache model used
http://research.compaq.com/wrl/people/jouppi/CACTI.html
- 43 -technische universitätdortmund
fakultät für informatik
p. marwedel, informatik 12, 2009
Summary
Performance analysis Simulation-based techniques
• Trade-off between speed and accuracy ( end of chapter 2)
Formal performance analysis• Thiele’s real-time calculus (RTC)/Modular performance analysis
(MPA)- Using bounds on the number of events in input streams- Using bounds on available processing capability- Derives bounds on the number of events in output streams- Derives bound on remaining processing capability, buffer sizes, …- Examples demonstrate design procedure based on RTC
Evaluation of objective “energy/power consumption”
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