f9 microkernel code reading part 4 memory management
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Part 4 : Code Reading of F9 Microkernel
ben6 2014-‐01-‐13
Memory Management
Agenda
• Brief of ARM memory system
• F9 Memory Management
• F9 Code reading
F9
Agenda
• Brief of ARM memory system
• F9 Memory Management
• F9 Code reading
F9
Cortex-‐M4 implementaAon
Cortex™-‐M4 Devices Generic User Guide
Brief of ARM memory system
• Mapped memory • bit-‐band • unaligned transfer • exclusive accessing • MPU
M4 memory map
Memory regions, types and aKributes Type Descrip;ons Normal The processor can re-‐order transacAons
for efficiency, or perform speculaAve reads.
Device The processor preserves transacAon order relaAve to other transacAons to Device or Strongly-‐ordered memory
Strongly Ordered
The processor preserves transacAon order relaAve to all other transacAons.
Different ordering requirements
• memory system can buffer a write to Device memory, but must not buffer a write to Strongly-‐ordered memory.
AddiAonal memory aKributes AAribute descrip;on
Shareable For a shareable memory region that is implemented, the memory system provides data synchronizaAon between bus masters in a system with mulAple bus masters for example, a processor with a DMA controller. Strongly-‐ordered memory is always shareable. If mulAple bus masters can access a non-‐shareable memory region, soWware must ensure data coherency between the bus masters. Note This aKribute is relevant only if the device is likely to be used in systems where memory is shared between mulAple processors.
Execute Never (XN)
the processor prevents instrucAon accesses. A fault excepAon is generated only on execuAon of an instrucAon executed from an XN region.
Bit-‐Band Memory Mapped
Peripheral
SRAM
code
0x00000000
0x200000000x1FFFFFFF
0x400000000x3FFFFFFF
0x5FFFFFFF
0.5GB
0.5GB
0.5GB
Bit-‐band Write Example Unuse
Bit-Band
Read 0x20000000 to register
Set bit 2 to register
Store register to 0x20000000
UseBit-Band
Write 1 to 0x22000008
Read data from 0x20000000 to buffer
Set bit 2 to buffer and write back to 0x20000000
Bit-‐band Code Write Example Unuse
Bit-Band
UseBit-Band
LDR R0,=0x20000000LDR R1,[R0]ORR.W R1,#0x4STR R1,[R0]
LDR R0,=0x22000008MOV R1,#1STR R1,[R0]
Bit-‐band Code Read Example Unuse
Bit-BandUse
Bit-Band
LDR R0,=0x20000000LDR R1,[R0]UBFX.W R1,R1,#2,#1
LDR R0,=0x22000008LDR R1,[R0]
Bit-‐band C Code Write Example
#define DEV_REG0 \((volatile unsigned long *)(0x40000000))#define DEV_REG0_BIT2 \((volatile unsigned long *)(0x22000008))*DEVICE_REG0 = 0x66;// …*DEVICE_REG0_BIT2 = 0x1;
Bit-‐Band area mapped table Bit-‐Band Area Aliased Equivalent
0x20000000 bit[0] 0x22000000 bit[0]
0x20000000 bit[1] 0x22000004 bit[0]
0x20000000 bit[2] 0x22000008 bit[0]
… …
0x20000000 bit[31] 0x2200007C bit[0]
0x20000004 bit[0] 0x22000080 bit[0]
… …
0x20000004 bit[31] 0x220000FC bit[0]
… …
0x200FFFFC bit[31] 0x223FFFFC bit[0]
Bit-‐Band benefits
• Bit operaAon efficiency • Make simple operate GPIO • Avoid race because read modify-‐write atomic in hardware level of mcu
Unaligned access • An aligned access is an operaAon where a word-‐aligned
address is used for a word, dual word, or mulAple word access, or where a halfword-‐aligned address is used for a halfword access. Byte accesses are always aligned.
• The Cortex-‐M4 processor supports unaligned access only
for the following instrucAons: – LDR, LDRT – LDRH, LDRHT – LDRSH, LDRSHT – STR, STRT – STRH, STRHT
Unaligned accesses are usually slower than aligned accesses. In addiAon, some memory regions might not support unaligned accesses. Therefore, ARM recommends that programmers ensure that accesses are aligned. To trap accidental generaAon of unaligned accesses, use the UNALIGN_TRP bit in the ConfiguraAon and Control Register
exclusive access instrucAons CMSIS functions for exclusive access instructions
• Instruction CMSIS function
• LDREX uint32_t __LDREXW (uint32_t *addr)
• LDREXH uint16_t __LDREXH (uint16_t *addr)
• LDREXB uint8_t __LDREXB (uint8_t *addr)
• STREX uint32_t __STREXW (uint32_t value, uint32_t *addr)
• STREXH uint32_t __STREXH (uint16_t value, uint16_t *addr)
• STREXB uint32_t __STREXB (uint8_t value, uint8_t *addr)
• CLREX void __CLREX (void)
M4 don’t have SWP because new ARM mcu read/write on different bus. Use exclusive access instead
Memory ProtecAon Unit (MPU) • independent aKribute sekngs for each region • overlapping regions • export of memory aKributes to the system.
If a program accesses a memory locaAon that is prohibited by the MPU, the processor generates a MemManage fault. This causes a fault excepAon, and might cause terminaAon of the process in an OS environment. In an OS environment, the kernel can update the MPU region sekng dynamically based on the process to be executed. Typically, an embedded OS uses the MPU for memory protecAon.
Memory ProtecAon Unit (MPU) Region defines: • eight separate memory regions, 0-‐7 (bigger number take higher precedence)
• a background region.
When memory regions overlap, a memory access is affected by the aKributes of the region with the highest number. The background region has the same memory access aKributes as the default memory map, but is accessible from privileged soWware only.
Agenda
• Brief of ARM memory system
• F9 Memory Management
• F9 Code reading
F9
F9 Memory Management(MM)
Unlike tradiAonal L4 kernels, built for "large systems", we focus on small MCU with energy efficiency.
Note: F9 MM is similar with Fiasco and memory management.
F9MM 3 Concepts
• Memory pool represent area of physical address space with specific aKributes.
• Flexible page describes an always size aligned region of an address space. Unlike other L4 implementaAons, flexible pages in F9 represent MPU region instead.
• Address space is made up of these flexible pages.
F9 MM Space efficiency
Obvious way is to use regions of standard size (e.g. 128 bytes), but it is very wasteful in terms of memory faults (we have only 8 regions for MPU, so for large ASes, we will oWen receive MM faults), and fpage table.
32 bytes
64 bytes
Page 96 bytes
fpage
MPU in Cortex-‐M supports regions of 2^n size only
Agenda
• Brief of ARM memory system
• F9 Memory Management
• F9 Code reading
F9
Code Reading base commit
git clone hKps://github.com/f9micro/f9-‐kernel.git f9-‐kernel cd f9-‐kernel git checkout f3f095887d2dc672dca29667ef91adafd8be95d3
Git repository: hKps://github.com/f9micro/f9-‐kernel.git Commit: f3f095887d2dc672dca29667ef91adafd8be95d3
Clone code with commit-‐id
MM related code
• include/fpage.h • include/fpage_impl.h • include/memory.h • kernel/memory.c • kernel/fpage.c • include/plaporm/mpu.h • plaporm/mpu.c
F9 MPU Memory Map staAc mempool_t memmap[] = { DECLARE_MEMPOOL_2("KTEXT", kernel_text, MP_KR | MP_KX | MP_NO_FPAGE, MPT_KERNEL_TEXT), DECLARE_MEMPOOL_2("UTEXT", user_text, MP_UR | MP_UX | MP_MEMPOOL | MP_MAP_ALWAYS, MPT_USER_TEXT), DECLARE_MEMPOOL_2("KIP", kip, MP_KR | MP_KW | MP_UR | MP_SRAM, MPT_KERNEL_DATA), DECLARE_MEMPOOL ("KDATA", &kip_end, &kernel_data_end, MP_KR | MP_KW | MP_NO_FPAGE, MPT_KERNEL_DATA), DECLARE_MEMPOOL_2("KBSS", kernel_bss, MP_KR | MP_KW | MP_NO_FPAGE, MPT_KERNEL_DATA), DECLARE_MEMPOOL_2("UDATA", user_data, MP_UR | MP_UW | MP_MEMPOOL | MP_MAP_ALWAYS, MPT_USER_DATA), DECLARE_MEMPOOL_2("UBSS", user_bss, MP_UR | MP_UW | MP_MEMPOOL | MP_MAP_ALWAYS, MPT_USER_DATA), DECLARE_MEMPOOL ("MEM0", &user_bss_end, 0x2001c000, MP_UR | MP_UW | MP_SRAM, MPT_AVAILABLE), #ifdef CONFIG_BITMAP_BITBAND DECLARE_MEMPOOL ("KBITMAP", &bitmap_bitband_start, &bitmap_bitband_end, MP_KR | MP_KW | MP_NO_FPAGE, MPT_KERNEL_DATA), #else DECLARE_MEMPOOL ("KBITMAP", &bitmap_start, &bitmap_end, MP_KR | MP_KW | MP_NO_FPAGE, MPT_KERNEL_DATA), #endif DECLARE_MEMPOOL ("MEM1", &kernel_ahb_end, 0x10010000, MP_UR | MP_UW | MP_AHB_RAM, MPT_AVAILABLE), DECLARE_MEMPOOL ("APB1DEV", 0x40000000, 0x40007800, MP_UR | MP_UW | MP_DEVICES, MPT_DEVICES), DECLARE_MEMPOOL ("APB2_1DEV", 0x40010000, 0x40013400, MP_UR | MP_UW | MP_DEVICES, MPT_DEVICES), DECLARE_MEMPOOL ("APB2_2DEV", 0x40014000, 0x40014c00, MP_UR | MP_UW | MP_DEVICES, MPT_DEVICES), DECLARE_MEMPOOL ("AHB1_1DEV", 0x40020000, 0x40022400, MP_UR | MP_UW | MP_DEVICES, MPT_DEVICES), DECLARE_MEMPOOL ("AHB1_2DEV", 0x40023c00, 0x40040000, MP_UR | MP_UW | MP_DEVICES, MPT_DEVICES), DECLARE_MEMPOOL ("AHB2DEV", 0x50000000, 0x50061000, MP_UR | MP_UW | MP_DEVICES, MPT_DEVICES), DECLARE_MEMPOOL ("AHB3DEV", 0x60000000, 0xA0001000, MP_UR | MP_UW | MP_DEVICES, MPT_DEVICES), };
KTEXT UTEXT KIP KDATA KBSS UDATA UBSS MEM0 KBITMAP KBITMAP MEM1 APB1DEV APB2_1DEV APB2_2DEV AHB1_1DEV AHB1_2DEV AHB2DEV AHB3DEV
LAB2: BIT-‐BAND F9-‐kernel Code Reading: memory Management
Lab 2 Bit-‐Band First Touch • Convert bit-band address and bit number to bit-band
alias address, please complete the following macro#define BITBAND(addr, bitnum) • Use BITBAND and MEM_ADDR set bit 4 to 0x20000100 addrHint: #define MEM_ADDR(addr) ((volatile unsigned long *)(addr))
Conclusion
• F9 Microkernel uses concept of flexible pages with memory pool which is aKributed physical address space to manage memory efficiency.
Discussions
?
F9
References • F9 Microkernel source code and introducAon
• GCC Naked AKribute • ARM: Memory Model of Cortex M4
• Cortex™ -‐M4 Devices Generic User Guide pdf • tu-‐dresden's fiasco Microkernel
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