ese 570: digital integrated circuits and vlsi …ese 570: digital integrated circuits and vlsi...

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

Lec 4: January 23, 2018 MOS Transistor Theory, MOS Model

Penn ESE 570 Spring 2018 – Khanna

Lecture Outline

!  CMOS Process Enhancements !  Semiconductor Physics

"  Band gaps "  Field Effects

!  MOS Physics "  Cut-off "  Depletion "  Inversion "  Threshold Voltage

Penn ESE 570 Spring 2018 - Khanna 2

CMOS Layers

!  “Standard” n-Well Process "  Active (Diffusion) (Drain/Source regions) "  Polysilicon (Gate Terminals) "  Metal 1, Metal 2, Metal3 "  Poly Contact (connects metal 1 to polysilicon) "  Active Contact (connects metal 1 to active) "  Via (connects metal 2 to metal 1) "  nWell (PMOS bulk region) "  n Select (used with active to create n-type diffusion) "  p Select (used with active to create p-type diffusion) 

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CMOS Process Enhancements

!  Interconnect "  Metal Interconnect (up to 8 metal levels) "  Copper Interconnect (upper two or more levels) "  Polysilicon (two or more levels, also for high quality capacitors) "  Stacked contacts and vias

!  Circuit Elements "  Resistors "  Capacitors "  BJTs

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CMOS Process Enhancements

!  Interconnect "  Metal Interconnect (up to 8 metal levels) "  Copper Interconnect (upper two or more levels) "  Polysilicon (two or more levels, also for high quality capacitors) "  Stacked contacts and vias

!  Circuit Elements "  Resistors "  Capacitors "  BJTs

!  Devices "  Multiple thresholds (High and low Vt) "  High-k gate dielectrics "  FinFET

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High-K dielectric

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SiO2 Dielectric Poly gate MOSFET High-K Dielectric Metal gate MOSFET

Dielectric constant=3.9 Dielectric constant=20

High-K dielectric Survey

Wong/IBM J. of R&D, V46N2/3P133—168, 2002 Penn ESE 570 Spring 2018 - Khanna 7

22nm 3D FinFET Transistor

8

Tri-Gate transistors with multiple fins connected together

increases total drive strength for higher performance

http://download.intel.com/newsroom/kits/22nm/pdfs/22nm-Details_Presentation.pdf

High-k gate

dielectric

Penn ESE 570 Spring 2018 - Khanna

CMOS Process Enhancements

!  Interconnect "  Metal Interconnect (up to 8 metal levels) "  Copper Interconnect (upper two or more levels) "  Polysilicon (two or more levels, also for high quality capacitors) "  Stacked contacts and vias

!  Circuit Elements "  Resistors "  Capacitors "  BJTs

!  Devices "  Multiple thresholds (High and low Vt) "  High-k gate dielectrics "  FinFET

!  Silicon on insulator process (SOI) "  Fabricate on insulator for high speed/low leakage

9

Semiconductor Physics

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Silicon Lattice

!  Cartoon two-dimensional view

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Energy State View

Valance Band – all states filled

Ene

rgy

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Energy State View

Valance Band – all states filled

Ene

rgy

Conduction Band– all states empty

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Energy State View

Valance Band – all states filled

Ene

rgy

Conduction Band– all states empty

Band Gap

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Band Gap and Conduction

Ec

Ev

Ev

Ec

Ev

Ec

OR

Insulator Metal

8ev

Ev

Ec

Semiconductor

1.1ev

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Doping

!  Add impurities to Silicon Lattice "  Replace a Si atom at a lattice site with another

!  E.g. add a Group 15 element "  E.g. P (Phosphorus)

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Doping with P

!  End up with extra electrons "  Donor electrons

!  Not tightly bound to atom "  Low energy to displace "  Easy for these electrons

to move

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Doped Band Gaps

!  Addition of donor electrons makes more metallic "  Easier to conduct

Ev

Ec

Semiconductor

1.1ev ED 0.045ev

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Doping with B

!  End up with electron vacancies -- Holes "  Acceptor electron sites

!  Easy for electrons to shift into these sites "  Low energy to displace "  Easy for the electrons to move

"  Movement of an electron best viewed as movement of hole

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Doped Band Gaps

!  Addition of acceptor sites makes more metallic "  Easier to conduct

Ev

Ec

Semiconductor

1.1ev EA 0.045ev

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MOSFETs

!  Donor doping "  Excess electrons "  Negative or N-type material "  NFET

!  Acceptor doping "  Excess holes "  Positive or P-type material "  PFET

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MOSFET

!  Semiconductor can act like metal or insulator "  Depends on doping

!  Use field to modulate conduction state of semiconductor

- - - - - -

+ + + + +

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MOS Capacitor Charge

!  MOS gate-to-substrate capacitor "  Charge across MOS cap induce e-field

+ + + + + + + +

- - - - - - - - - semiconductor

gate

source drain

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MOS Field?

!  What does “capacitor” field do to the Donor-doped semiconductor channel?

- -

Vgs=0 No field

- - - -

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MOS Field?

!  What does “capacitor” field do to the Donor-doped semiconductor channel?

+ + + +

- - - Vcap>0

- -

Vgs=0 No field

- - - -

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MOS Field?

!  What does “capacitor” field do to the Donor-doped semiconductor channel?

- -

Vgs=0 No field

+ + + + +

- - - - - - = Vgs>0

+ + + +

- - - Vcap>0

- - - -

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+ + + + +

- - - - - -

- - - - - -

MOS Field Effect

!  Charge on capacitor "  Attract or repel charges to form channel "  Modulates conduction "  Positive

"  Attracts carriers

"  Negative? "  Repel carriers

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Field Effect?

!  Effect of positive field on Acceptor-doped Silicon?

Vgs=0 No field

+ + + +

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Field Effect?

!  Effect of positive field on Acceptor-doped Silicon?

Vgs=0 No field + + + +

- - - Vcap>0

+ + + +

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Field Effect?

!  Effect of positive field on Acceptor-doped Silicon?

Vgs=0 No field

+ + + + +

= Vgs>0

No conduction

+ + + +

- - - Vcap>0

+ + + +

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Field Effect?

!  Effect of negative field on Acceptor-doped Silicon?

+ +

Vgs=0 No field +

+ + +

- - -

Vcap<0 + +

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Field Effect?

!  Effect of negative field on Acceptor-doped Silicon?

+ +

Vgs=0 No field

+ + + + + =

Vgs>0

+ + + +

- - -

Vcap<0

- - -

+ +

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MOS Physics - nMOS

MOS capacitor

Penn ESE 570 Spring 2018 - Khanna

Two-Terminal MOS Structure

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2

GATE

n+ n+

Si – Oxide interface

Penn ESE 570 Spring 2018 - Khanna

Two-Terminal MOS Structure

!  Equilibrium (Mass action law) "  Product of hole and electron densities is constant at

equilibrium "  n0p0=ni

2 ni=1.45x1010 cm-3

Penn ESE 570 Spring 2018 - Khanna

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2

GATE

n+ n+

Si – Oxide interface

Two-Terminal MOS Structure

!  n0p0=ni2 ni=1.45x1010 cm-3

!  Let substrate be uniformly doped with concentration NA

Penn ESE 570 Spring 2018 - Khanna

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2

GATE

n+ n+

Si – Oxide interface

Two-Terminal MOS Structure

!  n0p0=ni2 ni=1.45x1010 cm-3

!  Let substrate be uniformly doped with concentration NA

"  pp0=NA # np0=ni2/NA

Penn ESE 570 Spring 2018 - Khanna

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2

GATE

n+ n+

Si – Oxide interface

Two-Terminal MOS Structure

!  n0p0=ni2 ni=1.45x1010 cm-3

!  Let substrate be uniformly doped with concentration NA

"  pp0=NA # np0=ni2/NA

Penn ESE 570 Spring 2018 - Khanna

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2

GATE

n+ n+

Si – Oxide interface

If N-type doped substrate: nn0=ND # pn0=ni

2/ND

P-type Doped Semiconductor Band Gap

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Free space

Conduction band

Intrinsic Fermi level

Fermi level

Valence band

Electron affinity of silicon

!  qΦ and E are in units of energy = electron-volts (eV); where 1 eV = 1.6 x 10-19 J.

!  1 eV corresponds to energy acquired by a free electron that is accelerated by an electric potential of one volt.

!  Φ and V corresponds to potential difference in volts. Penn ESE 570 Spring 2018 - Khanna

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Free space

Conduction band

Intrinsic Fermi level

Fermi level

Valence band

P-type Doped Semiconductor Band Gap

Ei =EC −EV2

Penn ESE 570 Spring 2018 - Khanna

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Free space

Conduction band

Intrinsic Fermi level

Fermi level

Valence band

ΦFp =EF − Eiq

→ΦFp =kTqlnniNA

Fermi potential:

P-type Doped Semiconductor Band Gap

Ei =EC −EV2

Penn ESE 570 Spring 2018 - Khanna

MOS Capacitor Energy Bands

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MOS System Band Diagram

!  Three components put in physical contact "  Fermi levels must line up

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MOS Capacitor with External Bias

!  Three Regions of Operation (w/ VB=0): "  Accumulation Region – VG < 0 "  Depletion Region – VG > 0, small "  Inversion Region – VG ≥ VT, large

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Accumulation Region

!  Holes "  Accumulate at the

silicon-oxide interface

!  Electrons "  Near surface repelled

into silicon bulk

!  Interface accumulated with mobile carriers (holes)

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Accumulation Region – Energy Bands

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VG < 0 Band bending due to VG < 0

Accumulation

qΦFp qΦ(x) qΦS

x

EFm

EFp

0

qVG= EFp− EFm

Si surface

Penn ESE 570 Spring 2018 - Khanna

Depletion Region

47

tox

- - - - -

Penn ESE 570 Spring 2018 - Khanna

!  Holes "  Near silicon-oxide

interface repelled into silicon bulk

!  Electrons "  Left behind at interface

!  Interface depleted of mobile carriers (holes)

Depletion Region – Energy Bands

48

Depletion VG > 0 (small)

xd

Band bending due to VG > 0

qΦFp qΦS

qΦ(x)

x

EFm

EFp

0

qVG= EFp− EFm

Si surface

Penn ESE 570 Spring 2018 - Khanna

Depletion Region

49

Bulk potential

tox

- - - - Surface potential

ΦFp =ΦF =kTqln niNA

< 0

ΦS

ΦFpΦ

26 mV at room T

Penn ESE 570 Spring 2018 - Khanna

Depletion Region

50

Bulk potential

tox

- - - - Surface potential

ΦFp =ΦF =kTqln niNA

< 0

ΦS

ΦFpΦ

26 mV at room T

dQ = −qNAdx Mobile hole charge density (per unit area) in thin layer below surface

dφ = −x dQεSi

Potential required to displace dQ by distance x

Penn ESE 570 Spring 2018 - Khanna

Depletion Region

51

Bulk potential

tox

- - - - Surface potential

ΦFp =ΦF =kTqln niNA

< 0

ΦS

ΦFpΦ

26 mV at room T

dQ = −qNAdx Mobile hole charge density (per unit area) in thin layer below surface

dφ = −x dQεSi

Potential required to displace dQ by distance x

dφ = q ⋅NA ⋅ xεSi

dx

Penn ESE 570 Spring 2018 - Khanna

Depletion Region

52

Bulk potential

tox

- - - - Surface potential

ΦFp =ΦF =kTqln niNA

< 0

ΦS

ΦFpΦ

26 mV at room T

dφ = q ⋅NA ⋅ xεSi

dx

dφΦS

ΦFp

∫ =q ⋅NA ⋅ xεSi

dx0

xd

∫ =q ⋅NA ⋅ xd

2

2εSi=ΦFp −ΦS

⇒ xd =2εSi ΦFp −ΦS

q ⋅NA

Penn ESE 570 Spring 2018 - Khanna

Depletion Region

53

Bulk potential

tox

- - - - Surface potential

ΦFp =ΦF =kTqln niNA

< 0

ΦS

ΦFpΦ

26 mV at room T

dφ = q ⋅NA ⋅ xεSi

dx

dφΦS

ΦFp

∫ =q ⋅NA ⋅ xεSi

dx0

xd

∫ =q ⋅NA ⋅ xd

2

2εSi=ΦFp −ΦS

⇒ xd =2εSi ΦFp −ΦS

q ⋅NA

Penn ESE 570 Spring 2018 - Khanna

Depletion Region

54

Bulk potential

tox

- - - - Surface potential

ΦFp =ΦF =kTqln niNA

< 0

ΦS

ΦFpΦ

26 mV at room T

xd =2εSi ΦFp −ΦS

q ⋅NA

Q = −qNAxd

Q = −qNA

2εSi ΦFp −ΦS

q ⋅NA

= − 2qNAεSi ΦFp −ΦS

Penn ESE 570 Spring 2018 - Khanna

Inversion Region

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tox

- - - - - - - - -

VG ≥ VT

Penn ESE 570 Spring 2018 - Khanna

!  Holes "  Repelled deeper into silicon

bulk

!  Electrons "  Attracted to silicon-oxide

interface

!  Inversion condition "  When ΦS

= −ΦF

"  Density of mobile electrons at surface = density of mobile carriers in bulk

Inversion Region – Energy Bands

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Inversion VG ≥ VT0 > 0

xdm

qΦS

qΦFp

x 0

EFm

EFp qVG= EFp− EFm

Si surface

Penn ESE 570 Spring 2018 - Khanna

Inversion Region

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tox

- - - - - - - - -

VG ≥ VT

Penn ESE 570 Spring 2018 - Khanna

Q = − 2qNAεSi ΦFp −ΦS = − 2qNAεSi 2ΦFp

xdm =2εSi ΦFp −ΦS

q ⋅NA=2εSi 2ΦFp

q ⋅NA

!  Inversion condition

"  When ΦS= −ΦF

"  Density of mobile electrons at surface = density of mobile carriers in bulk

Band Diagram Demo

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http://demonstrations.wolfram.com/AppliedVoltageOnAnIdealMOSCapacitor/

- - - - -

MOS Capacitor with External Bias

!  Three Regions of Operation: "  Accumulation Region – VG < 0 (Cut-off) "  Depletion Region – VG > 0, small (Subthreshold) "  Inversion Region – VG ≥ VT, large (Above Threshold)

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- - - - -

Cut-off/Subthreshold Above threshold

VG ≥ VT

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depletion region

-

VG VS VD

2-terminal MOS Cap # 3-terminal nMOS

- - - - -- -

-

-- --

Penn ESE 570 Spring 2018 - Khanna

nMOS = MOS cap + source/drain

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VSB = 0

-

- - - - - -

- - -

-

VG VD VS

Penn ESE 570 Spring 2018 - Khanna

Threshold Voltage

!  For VSB=0, the threshold voltage is denoted as VT0 or VT0n,p

"  ΦGC : Work function difference between gate and channel "  Metal Gate: ΦGC=ΦF(substrate) –ΦM "  Poly Gate: ΦGC =ΦF(substrate) –ΦF(gate)

"  QOX : Fixed positive charge density at interface "  QOX= qNOX C/cm2

"  COX : Gate oxide capacitance per unit area "  COX=εOX/tox

"  ΦGC : Bulk fermi potential "  QB0 : Depletion region charge density at inversion

" 

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VT 0 =ΦGC −Qox

Cox

− 2ΦF −QB0

Cox

QB0 = − 2qNAεSi 2ΦF

Threshold Voltage

!  For VSB=0, the threshold voltage is denoted as VT0 or VT0n,p

"  ΦGC : Work function difference between gate and channel "  Metal Gate: ΦGC=ΦF(substrate) –ΦM "  Poly Gate: ΦGC =ΦF(substrate) –ΦF(gate)

"  QOX : Fixed positive charge density at interface "  QOX= qNOX C/cm2

"  COX : Gate oxide capacitance per unit area "  COX=εOX/tox

"  ΦGC : Bulk fermi potential "  QB0 : Depletion region charge density at inversion

" 

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VT 0 =ΦGC −Qox

Cox

− 2ΦF −QB0

Cox

QB0 = − 2qNAεSi 2ΦF

Threshold Voltage

64

for VSB = 0

for VSB != 0 VT =ΦGC −

QoxCox

− 2ΦF −QBCox

VT =ΦGC −QoxCox

− 2ΦF −QB0Cox

−QB −QB0Cox

VT =VT 0 −QB −QB0Cox

Penn ESE 570 Spring 2018 - Khanna

VT =VT 0 =ΦGC −QoxCox

− 2ΦF −QB0Cox

Threshold Voltage

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for VSB = 0

for VSB != 0 VT =ΦGC −

QoxCox

− 2ΦF −QBCox

VT =ΦGC −QoxCox

− 2ΦF −QB0Cox

−QB −QB0Cox

VT =VT 0 −QB −QB0Cox

−QB −QB0

Cox

=2qNAεSiCox

2ΦF −VSB − 2ΦF( )

VT =VT 0 +γ 2ΦF −VSB − 2ΦF( )

γ

Penn ESE 570 Spring 2018 - Khanna

VT =VT 0 =ΦGC −QoxCox

− 2ΦF −QB0Cox

Q = − 2qNAεSi ΦF −ΦS

Threshold Voltage

N-channel P-channel ϕF negative positive QB0,QB negative positive ϒ positive negative VSB ≥0 ≤0 VT0 positive (VT0n) negative (VT0p)

Penn ESE 570 Spring 2018 - Khanna

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!  Be careful with signs!

67

|VSB|

Threshold Voltage

Penn ESE 570 Spring 2018 - Khanna

Big Idea

!  3 operation regions "  Cut-off "  Depletion "  Inversion

!  Threshold voltage "  Defined by onset of inversion "  Doping and VSB change VT

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Admin

!  HW 2 due Thursday, 1/25 "  Submit in canvas

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