elen0040 - electronique num´erique
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ELEN0040 - Electronique numerique
Patricia ROUSSEAUX
Annee academique 2014-2015
CHAPITRE 3
Combinational Logic Circuits
ELEN0040 3 - 96
1 Combinational Functional Blocks1.1 Rudimentary Functions1.2 Functions and Functional Blocks1.3 Decoders1.4 Encoders1.5 Multiplexers1.6 Implementing Combinational Functions with Multiplexers
2 Arithmetic Functions2.1 Binary Adders2.2 Binary Arithmetic2.3 Binary Adders-Subtractors2.4 Overflow2.5 Other Arithmetic Functions
ELEN0040 3 - 97
Functions and Functional Blocks
◮ Introduction of fundamental components performing basiccombinational functions
◮ The basic functions considered are those found to be very useful indesign : decoding, encoding, selecting
◮ Corresponding to each of the functions is a combinational circuitimplementation called a functional block : decoder, encoder andmultiplexer
◮ In the past, functional blocks were packaged assmall-scale-integrated (SSI), medium-scale integrated (MSI), andlarge-scale-integrated (LSI) circuits.
◮ Today, they are often simply implemented within avery-large-scale-integrated (VLSI) circuit.
ELEN0040 3 - 98
Multiple-bit Rudimentary Functions
� Multi-bit Examples:
� A wide line is used to representa bus which is a vector signal
� In (b) of the example, F = (F3, F2, F1, F0) is a bus.� The bus can be split into individual bits as shown in (b)� Sets of bits can be split from the bus : (c) bits 2 and 1 of F. � The sets of bits need not be continuous : (d) bits 3, 1, and 0 of F.
99
F(d)
0
F3
1 F2
F1A F0
(a)
01
A1
2 34
F0
(b)
4 2:1 F(2:1)2
F(c)
4 3,1:0 F(3), F(1:0)3
A A
Enabling Function
� Enabling permits an input signal to pass through to an output
� Disabling blocks an input signal from passing through to an output, replacing it with a fixed value !
� The value on the output when it is disable can be 0 , or 1
• When disabled, 0 output
• When disabled, 1 output
100
XF
EN
(a)
ENX
F
(b)
Decoding ( n → m ; n < m )
� Decoding - the conversion of an n-bit input code to an m-bit output code with
n ≤ m ≤ 2n
� such that each valid input code word produces a unique output code
� Circuits that perform decoding are called decoders� Here, functional blocks for decoding are
• called : n-to-m line decoders, where m ≤ 2n, and• generate 2n (or fewer) minterms for the n input
variables
101
Decoder Examples
� 1-to-2-Line Decoder
� 2-to-4-Line Decoder
102
The 2-4-line decoder is made up of 2 1-to-2-line decoders and 4 AND gates.
A D0 D1
0 1 0
1 0 1
(a) (b)
D1 5 AA
D0 5 A
A 1
0
0
1
1
A 0
0
1
0
1
D 0
1
0
0
0
D 1
0
1
0
0
D 2
0
0
1
0
D 3
0
0
0
1
(a)
(b)
D 0 5 A 1 A 0
D 1 5 A 1 A 0
D 2 5 A 1 A 0
D 3 5 A 1 A 0
A 1
A 0
Decoder Expansion
� For a larger decoder with n inputs and 2n outputs, use hierarchical design
� Split the decoder into smaller dimensions ones� At each stage, divide by 2 the number of inputs � The output AND gates are driven by two decoders
with their numbers of inputs either equal or differing by 1.
� These decoders are then designed using the same procedure until 2-to-1-line decoders are reached.
� The procedure can be modified to apply to decoders with the number of outputs ≠ 2n
103
Decoder Expansion - Example 1
� 3-to-8-line decoder • Number of inputs n=3
• Number of output ANDs m=23=8• First split : 3 = 1*2 + 1
� One 2-to-4-line decoder� One 1-to-2-line decoder
• Second split : split the 2-to-4-line decoder, 2=2*1� Two 1-to-2-line decoders
• At each stage, each decoder with k (k>1) inputs provides its 2k outputs through 2k 2-AND gates
104
Decoder Expansion - Example 1
� Circuit
3 105
3-to-8 Line decoder
1-to-2-Line decoders
4 2-input ANDs 8 2-input ANDs
2-to-4-Linedecoder
D0A 0
A 1
A 2
D1
D2
D3
D4
D5
D6
D7
Decoder Expansion - Example 2
� 7-to-128-line decoder • Number of output ANDs m=27= 128• Number of inputs n= 7• First split : 7=1*4+1*3
� One 4-to-16-line decoder� One 3-to-8-line decoder
• Second split :� 4-to-16-line decoder : 4=2*2 → Two 2-to-4-line decoders� 3-to-8-line decoder : 3=1*2+1 → One 2-to-4-line decoder
+ one 1-to-2-line decoder
• Third split : � 2-to-4-line decoders : 2=2*1 → Two 1-to-2-line decoders
106
7-to-128-line decoder : hierarchical structure
107
128 2-ANDs16 2-ANDs
8 2-ANDs
4 2-ANDs
4 2-ANDs
4 2-ANDs
DEC 1-2
DEC 1-2
DEC 1-2
DEC 1-2
DEC 1-2
DEC 1-2
DEC 1-2
DEC 2-4
DEC 2-4
DEC 2-4
DEC 3-8
DEC 4-167 inputs
Decoder with Enable
� In general, attach m-enabling circuits to the outputs� See truth table below for function
• Note the use of X’s to denote both 0 and 1 in the inputs• Combination containing two X’s represent four binary combinations
� Demultiplexer : distribute value of signal EN to 1 of 4 outputs
� In this case, • input data =EN• Selection inputs = A1, A0
108
EN
A 1
A 0
D0
D1
D2
D3
(b)
EN A1 A 0 D 0 D1 D2 D 3
01111
X0011
X0101
01000
00100
00010
00001
(a)
Combinational Logic ImplementationDecoder and OR Gates
� A decoder provides 2n minterms� Any function can be represented by its SOM
expression� A decoder can be used to implement m functions
of n variables :• Find the sum-of-minterms expressions• Use one n-to-2n-line decoder• Use m OR gates, one for each output
� Not always the best solution !
109
Decoder and OR Gates Example
� Implement the following set of odd parity functions of (A7, A6, A5, A3)P1 = A7 A5 A3
P2 = A7 A6 A3
P4 = A7 A6 A5
� Finding sum ofminterms expressions
P1 = Σm(1,2,5,6,8,11,12,15)P2 = Σm(1,3,4,6,8,10,13,15)P4 = Σm(2,3,4,5,8,9,14,15)
� Find circuit� Best solution ? Better to resort
to XOR gates
110
+
+
+
+
+
+
0123456789101112131415
A7A6A5A3
P1
P4
P2
DEC 4-16
Encoding
� Encoding - the opposite of decoding - the conversion of an m-bit input code to a n-bit output code with n ≤ m ≤ 2n such that each valid code word produces a unique output code
� Circuits that perform encoding are called encoders� An encoder has 2n (or fewer) input lines and n output
lines which generate the binary code corresponding to the input values
� Typically, an encoder converts a code containing exactly one bit that is 1 to a binary code corresponding to the position in which the 1 appears.
111
Encoder Example
� A decimal-to-BCD encoder• Inputs: 10 bits corresponding to decimal digits 0
through 9, (D0, …, D9)• Outputs: 4 bits with BCD codes• Function: If input bit Di is a 1, then the output (A3,
A2, A1, A0) is the BCD code for i
� The truth table could be formed, but alternatively, the equations for each of the four outputs can be obtained directly.
112
Encoder Example (continued)
113
Encoder Example (continued)
� Input Di is a term in equation Aj if bit Aj is 1 in the binary coded value of i.
� Equations:
A3 = D8 + D9
A2 = D4 + D5 + D6 + D7
A1 = D2 + D3 + D6 + D7
A0 = D1 + D3 + D5 + D7 + D9
114
Priority Encoder
� If more than one input value is 1, then the encoder just designed does not work.
� One encoder that can accept all possible combinations of input values and produce a meaningful result is a priority encoder.
� It implements a priority function, one 1 value is given the priority above others
� For example, among the 1s that appear, it selects the most significant input position (or the least significant input position) containing a 1 and responds with the corresponding binary code for that position.
115
Priority Encoder Example
� Priority encoder with 5 inputs (D4, D3, D2, D1, D0) - highest priority to most significant 1 present –
� Code outputs A2, A1, A0 and V where V indicates at least one 1 present.
� In the Table, X in input variable represent 0 or 1 so that row 6 of the table represents 16 rows of the truth table
116
No. of Min-terms/Row
Inputs Outputs
D4 D3 D2 D1 D0 A2 A1 A0 V
1 0 0 0 0 0 X X X 0
1 0 0 0 0 1 0 0 0 1
2 0 0 0 1 X 0 0 1 1
4 0 0 1 X X 0 1 0 1
8 0 1 X X X 0 1 1 1
16 1 X X X X 1 0 0 1
Priority Encoder Example (continued)
� Equations (after simplification) :
A2 = D4
A1 = D3 + D2 = F1, F1 = (D3 + D2)
A0 = D3 + D1 = (D3 + D1)
V = D4 + F1 + D1 + D0
117
D3
D4 D3D4 D4D4 D4 D2 D4 D2
Selecting
� Selecting data or information is a critical function in digital systems and computers
� Circuits that perform selecting have:• A set of information inputs from which the selection is made• A single output• A set of control lines for making the selection
� Logic circuits that perform selecting are called multiplexers
118
Multiplexers
� A multiplexer selects information from an input line and directs the information to the output line
� A typical multiplexer has n control inputs (Sn - 1, … S0) called selection inputs, 2n
information inputs (I2n- 1, … I0), and one output Y
� A multiplexer can be designed to have minformation inputs with m < 2n as well as nselection inputs
119
Multiplexers (2)
120
Input Selection
Inputs Output
2-to-1-Line Multiplexer
� Two information inputs I0, I1, so n=1� A single selection input S:
• S = 0 selects input I0• S = 1 selects input I1
� Truth table :� The equation:
Y = I0 + SI1
121
S
2-to-1-Line Multiplexer
� The circuit:
� We recognize :• 1-to-2-line Decoder• 2 Enabling circuits• 2-input OR gate
122
S
I0
I1
DecoderEnablingCircuits
Y
2n-to-1-Line Multiplexer
� For n>1 selecting inputs� An 2n-to-1-line multiplexer can be built from :
• one n-to-2n-line decoder generating the mi
• one 2n × 2 AND-OR circuit combining the enabling circuits and the OR gate
� Example : n=2� Equation
� � ��� ����+ ��� ���� � ����� � ������ � ����+���� �� �+��
123
Example: 4-to-1-line Multiplexer
� one 2-to-22-line decoder� one 22 × 2 AND-OR
124
S1Decoder
S0
Y
S1Decoder
S0
Y
S1Decoder
4 3 2 AND-ORS0
Y
I2
I3
I1
I0
Inputs !
4×2 AND-OR
mi
Multiplexer with m outputs
� Select “vectors of bits” instead of “bits”� Use multiple copies of 2n × 2 AND-OR in parallel� Example: m=4
4-to-1-linequad multi-plexer
125
4 3 2 AND-OR
2-to-4-Line decoder
4 3 2 AND-OR
4 3 2 AND-OR
4 3 2 AND-OR
I0,0
I3,0
I0,1
I3,1
I0,2
I3,2I0,3
I3,3
Y0
D0
D3
A 0
A 1
Y1
Y2
Y3
.
.
.
.
.
....
.
.
.
.
.
.
4×2 AND-OR
4×2 AND-OR
4×2 AND-OR
4×2 AND-OR
Combinational Logic Implementation- Multiplexer Approach 1
� Multiplexing is a universal function� Any combinational n-variable function can be
implemented with a • A sum-of-minterms expression• An 2n-to-1-line multiplexer
� Design: • Apply the function input variables to the multiplexer
selection inputs Sn - 1, … , S0
• Find the SOM expression from the truth table• Put values to multiplexer inputs :
� If minterm mj is present in SOM, put Ij=1� If minterm mj is not present in SOM, put Ij=0
126
Example : F(X,Y) = Ʃm(0, 3)
S1Decoder
S0
Y
S1Decoder
S0
Y
S1Decoder
4 3 2 AND-ORS0
Y
I2
I3
I1
I0
127
Y
X
m0
m1
m2
m3
1
1
0
0
4×2 AND-OR
Example: Gray to Binary Code
� Design a circuit to convert a 3-bit Gray code to a binary code
� The formulation givesthe truth table on theright
� It is obvious from thistable that X = C and theY and Z are more complex
128
GrayA B C
Binaryx y z
0 0 0 0 0 01 0 0 0 0 11 1 0 0 1 00 1 0 0 1 10 1 1 1 0 01 1 1 1 0 11 0 1 1 1 00 0 1 1 1 1
Gray to Binary (continued)
� Rearrange the table sothat the input combinationsare in counting order
� Functions y and z can be implemented usinga dual 8-to-1-line multiplexer by:• connecting A, B, and C to the multiplexer select inputs• placing y and z on the two multiplexer outputs• connecting their respective truth table values to the
inputs129
GrayA B C
Binaryx y z
0 0 0 0 0 00 0 1 1 1 10 1 0 0 1 10 1 1 1 0 01 0 0 0 0 11 0 1 1 1 01 1 0 0 1 01 1 1 1 0 1
Gray to Binary (continued)
� � � �, �, �, � � � ���, �, �, ��
130
D04D05D06D07
S1S0
AB
S2
D03D02D01D00
Out
C
D14D15D16D17
S1S0
AB
S2
D13D12D11D10
Out
C
11
1
1
11
11
00
0
0
0
0
0
0
Y Z
8-to-1MUX
8-to-1MUX
GrayA B C
Binaryx y z
0 0 0 0 0 00 0 1 1 1 10 1 0 0 1 10 1 1 1 0 01 0 0 0 0 11 0 1 1 1 01 1 0 0 1 01 1 1 1 0 1
Combinational Logic Implementation- Multiplexer Approach 2 (more economical !)
� A simpler implementation is obtained by using :• A 2n-1-to-1-line multiplexer• A single inverter
� Design:• Apply the first n-1 function input variables to the
multiplexer selection inputs Sn - 2, … , S0
• Find the SOM expression from the truth table• Define the multiplexer inputs to get the minterms of
the function :� let �� be the n-th function input variable� each multiplexer input is either : 1, 0, �� or ��
131
Gray to Binary (continued)
132
GrayA B C
Binaryx y z
RudimentaryFunctions of
C for y
Rudimentary Functions of
C for z
0 0 0 0 0 0
0 0 1 1 1 1
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 0 0 1
1 0 1 1 1 0
1 1 0 0 1 0
1 1 1 1 0 1
F = C
F = C
F = C
F = C
F = C
F = CF = C
F = C
Gray to Binary (continued)
� Assign the variables and functions to the multiplexer inputs:
� Note that this approach (Approach 2) reduces the cost by almost half compared to Approach 1.
133
S1S0
AB
D03D02D01D00
Out Y
8-to-1MUX
CC
C
C D13D12D11D10
Out Z
8-to-1MUX
S1S0
AB
C
C
C
CC C
Y � m 1,2,5,6 Z � m�1,2,4,7�
Summary
Decoder :
◮ n inputs
◮ m outputs, n ≤ m ≤ 2n
◮ generate minterms : outputDi = mi
Encoder :
◮ 2n inputs = 2n minterms, onlyone equal to 1
◮ n outputs
◮ generate the binaryrepresentation of the inputvalues : n-bit representation
ELEN0040 3 - 134
Summary (continued)
Multiplexer :
◮ n selecting inputs
◮ 2n information inputs
◮ one output
◮ select binary information fromone input
F = S1S0D0 + S1S0D1 + S1S0D2 + S1S0D3
ELEN0040 3 - 135
1 Combinational Functional Blocks1.1 Rudimentary Functions1.2 Functions and Functional Blocks1.3 Decoders1.4 Encoders1.5 Multiplexers1.6 Implementing Combinational Functions with Multiplexers
2 Arithmetic Functions2.1 Binary Adders2.2 Binary Arithmetic2.3 Binary Adders-Subtractors2.4 Overflow2.5 Other Arithmetic Functions
ELEN0040 3 - 136
Arithmetic circuits
◮ An arithmetic circuit is a combinational circuit that performsarithmetic operations :
◮ addition◮ subtraction◮ multiplication◮ division
◮ The operations are performed with binary numbers or decimalnumbers in a binary code
◮ Apply the rules of arithmetic with binary numbers◮ rules for numbers representation◮ resort to 1 or 2’s complements
◮ An arithmetic circuit :◮ operates on binary vectors◮ uses the same subfunction for each bit position◮ is made of the iterative interconnection of basic functional blocks,
one for each bit position = iterative array
ELEN0040 3 - 137
Adders
Functional blocks :
◮ Half-Adder : a 2-input, 2-output functional block that performs theaddition of the two input bits
◮ Full-Adder : a 3-input, 2-output functional block that performs theaddition of the three input bits, including a third carry input bitobtained from a previous adder
Multiple bit adders :
◮ Ripple Carry Adder : an iterative array to perform binary addition
◮ Carry Look Ahead Adder : an improved structure with higherperformance
ELEN0040 3 - 138
139
Half-Adder
� A Half-Adder performs the following computations:
� It adds two bits to produce a two-bit sum� The sum is expressed as a Sum bit, S and
a Carry bit, C
X 0 0 1 1
+ Y + 0 + 1 + 0 + 1
C S 0 0 0 1 0 1 1 0
Half-Adder : Truth table
� From the truth table, we get the equations :
� For S
� And for C :
140
X Y C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0)YX()YX(S
YXYXYXS
++++⋅⋅⋅⋅++++====⊕⊕⊕⊕====⋅⋅⋅⋅++++⋅⋅⋅⋅====
)(C
YXC
)YX( ⋅⋅⋅⋅====⋅⋅⋅⋅==== X
Y
141
Half-Adder : Five Implementations
� We can derive the 5 following sets of equations for a half-adder:
� (a), (b), and (e) are SOP, POS, and XOR implementations for S.
� In (c), the C function is used as a term in the AND-NOR implementation of S, and in (d), the function is used in a POS term for S.
YXC)(S)c(
YXC)YX()YX(S)b(
YXCYXYXS)a(
YXC⋅⋅⋅⋅====
====⋅⋅⋅⋅====
++++⋅⋅⋅⋅++++====⋅⋅⋅⋅====
⋅⋅⋅⋅++++⋅⋅⋅⋅====
⋅⋅⋅⋅++++YXCYXS)e(
)YX(CC)YX(S)d(
⋅⋅⋅⋅====⊕⊕⊕⊕====
++++====⋅⋅⋅⋅++++====
C
142
Half-Adder : Implementations
� The most common half adder implementation is: (e)
� A NAND only implementation is: (d)
YXCYXS
⋅⋅⋅⋅====⊕⊕⊕⊕====
)(CC)YX(S
)YX( ⋅⋅⋅⋅====⋅⋅⋅⋅++++====
XY
C
S
X
Y
C
SC
XOR
143
Full-Adder
� A full adder is similar to a half adder, but includes a carry-in bit from previous stages.
� Like the half-adder, it computes a sum bit, S and a carry bit, C.
� It performs the following computations
� For a carry-in Z=0it is the same as the half-adder
� For a carry- in Z=1
Z 0 0 0 0X 0 0 1 1
+ Y + 0 + 1 + 0 + 1C S 0 0 0 1 0 1 1 0
Z 1 1 1 1X 0 0 1 1
+ Y + 0 + 1 + 0 + 1C S 0 1 1 0 1 0 1 1
Full-Adder : Truth table
� From the truth table, we get the equations :
� After simplification :
Odd function
144
X Y Z C S0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1
ZX YCZYXZYXZYXZYXS
++++ ++++====++++++++++++====
ZX Y ZX YZX Y ++++
ZYXS ⊕⊕⊕⊕⊕⊕⊕⊕====
Z)Y(YXC ⊕⊕⊕⊕++++====
ZPGC ++++====
XXYZ
Full-Adder : Implementation
145
ZYXS ⊕⊕⊕⊕⊕⊕⊕⊕==== ZPGC ++++====
The term G=X·Y is carry generate.The term P= X⊕Y is carry propagate
P
G
References
◮ Logic and Computer Design Fundamentals, 4/E, M. Morris ManoCharles Kime , Course materialhttp ://writphotec.com/mano4/
◮ Cours d’electronique numerique, Aurelie Gensbittel, BertrandGranado, Universite Pierre et Marie Curiehttp ://bertrand.granado.free.fr/Licence/ue201/coursbeameranime.pdf
ELEN0040 3 - 146
ELEN0040 3 - 147
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