elec 7770 advanced vlsi design spring 2007 clock skew problem

Spring 07, Mar 22Spring 07, Mar 22 ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 11

ELEC 7770ELEC 7770Advanced VLSI DesignAdvanced VLSI Design

Spring 2007Spring 2007Clock Skew ProblemClock Skew Problem

Vishwani D. AgrawalVishwani D. AgrawalJames J. Danaher ProfessorJames J. Danaher Professor

ECE Department, Auburn UniversityECE Department, Auburn University

Auburn, AL 36849Auburn, AL 36849

vagrawal@eng.auburn.eduvagrawal@eng.auburn.edu

http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr07http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr07

Spring 07, Mar 22Spring 07, Mar 22 ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 22

Single ClockSingle Clock

FF A FF BComb.

CK

Data_in Data_out

CKA

CKA CKB

CKB

Single-cycle path delay

Spring 07, Mar 22Spring 07, Mar 22 ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 33

Multiple ClocksMultiple Clocks

FF A FF BComb.Data_in Data_out

CKA

CKA CKB

CKB

Multi-cycle path delay

Spring 07, Mar 22Spring 07, Mar 22 ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 44

Clock SkewClock Skew

Skew is the time delay of clock signal at a flip-Skew is the time delay of clock signal at a flip-flop with respect to some time reference.flop with respect to some time reference.

For a given layout each flip-flop has a skew, For a given layout each flip-flop has a skew, measured with respect to the a common measured with respect to the a common reference.reference.

Skews of flip-flops separated by combinational Skews of flip-flops separated by combinational paths affect the short-path and long-path paths affect the short-path and long-path constraints.constraints.

Spring 07, Mar 22Spring 07, Mar 22 ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 55

Skews for Single-Cycle PathsSkews for Single-Cycle Paths

CombinationalBlockDelay:

FFi

CKi

FFj

CKj

xi xj

xi and xj are arrival times of clock edges

δ(i,j) ≤ d(i,j) ≤ Δ(i,j)

Spring 07, Mar 22Spring 07, Mar 22 ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 66

Short-Path Constraint (Double-Clocking)Short-Path Constraint (Double-Clocking)

CKi

CKj

xi

xj

intendedNot intended

Thj

xi + δ(i,j) ≥ xj + Thj

δ(i,j)

Tck

Spring 07, Mar 22Spring 07, Mar 22 ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 77

Long-Path Constraint (Zero-Clocking)Long-Path Constraint (Zero-Clocking)

CKi

CKj

xi

xj

intended Not intended

Tsj

xi + Δ(i,j) ≤ xj + Tck – Tsj

Δ(i,j)

Tck

Spring 07, Mar 22Spring 07, Mar 22 ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 88

Maximum Clock FrequencyMaximum Clock Frequency

Linear program:

Minimize Tck

Subject to:

For all flip-flop pairs (i,j),

xi + δ(i,j) ≥ xj + Thj

xi + Δ(i,j) ≤ xj + Tck – Tsj

Spring 07, Mar 22Spring 07, Mar 22 ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 99

Finding Clock SkewsFinding Clock Skews

FFi

Ci

Ri

FFj

Cj

Rj

FFk

Ck

RkCK

xi

xj

xk

Use Elmore delay formula to calculate xi, xj, xk.

Spring 07, Mar 22Spring 07, Mar 22 ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 1010

Interconnect Delay: Elmore Delay ModelInterconnect Delay: Elmore Delay Model W. Elmore, “The Transient Response of Damped Linear Networks with W. Elmore, “The Transient Response of Damped Linear Networks with

Particular Regard to Wideband Amplifiers,” Particular Regard to Wideband Amplifiers,” J. Appl. PhysJ. Appl. Phys., vol. 19, ., vol. 19, no.1, pp. 55-63, Jan. 1948.no.1, pp. 55-63, Jan. 1948.

CKi j

kRi Rj Rk

Ci Cj CkShared resistance:Rii = RiRij = Rji = RiRik = Rki = RiRjj = Ri + RjRjk = Rkj = Ri + RjRkk = Ri + Rj + Rk

Spring 07, Mar 22Spring 07, Mar 22 ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 1111

Elmore Delay CalculationElmore Delay Calculation

Delay at node k, xk = 0.69 (Ci × Rik + Cj × Rjk + Ck × Rkk )

= 0.69 [Ri Ci + (Ri+Rj) Cj + (Ri+Rj+Rk)Ck]

Spring 07, Mar 22Spring 07, Mar 22 ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 1212

Finding Finding δδ(I,j) and (I,j) and ΔΔ(I,j)(I,j)

A1

B3

C1

D2

E1

F1

J1

G2

H3

, -, -

, - 0, 0

, -, -

, -, -

i

j

k

3, 3

, -

, -

4, 4

5, 5

6, 6

5, 6

, -6, 6

Minimum delayMaximum delay

Spring 07, Mar 22Spring 07, Mar 22 ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 1313

Maximum Clock Frequency for Maximum Clock Frequency for Tolerance Tolerance ±q/2 in Skew±q/2 in Skew

Linear program:

Minimize Tck

Subject to:

For all flip-flop pairs (i,j),

xi + δ(i,j) ≥ xj + Thj + q

xi + Δ(i,j) ≤ xj + Tck – Tsj – q

Where q is a constant.

Spring 07, Mar 22Spring 07, Mar 22 ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 1414

Maximum Tolerance for Given Clock Maximum Tolerance for Given Clock FrequencyFrequency

Linear program:

Maximize q

Subject to:

For all flip-flop pairs (i,j),

xi + δ(i,j) ≥ xj + Thj + q

xi + Δ(i,j) ≤ xj + Tck – Tsj – q

Where Tck is a constant.

Spring 07, Mar 22Spring 07, Mar 22 ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 1515

TradeoffsTradeoffs

Increasing clock period Tck

Incr

ea

sing

ske

w to

lera

nce

q

No

so

lutio

n b

eca

use

of

Ze

ro s

lack

.

Spring 07, Mar 22Spring 07, Mar 22 ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 1616

Clock Skew ProblemClock Skew Problem

N. Maheshwari and S. S. Sapatnekar, Timing Analysis and Optimization of Sequential Circuits, Springer, 1999.

J. P. Fishburn, “Clock Skew Optimization,” J. P. Fishburn, “Clock Skew Optimization,” IEEE IEEE Trans. ComputersTrans. Computers, vol. 39, no. 7, pp. 945-951, , vol. 39, no. 7, pp. 945-951, July 1990.July 1990.