ecen620: network theory broadband circuit design fall...

Sam PalermoAnalog & Mixed-Signal Center

Texas A&M University

ECEN620: Network TheoryBroadband Circuit Design

Fall 2019

Lecture 3: Phase-Locked Loop Systems

Announcements

• HW1 due Sept 24

Reading/References

• Chapter 2, 3, 5, & 12 of Phaselock Techniques, F. Gardner, John Wiley & Sons, 2005. • https://onlinelibrary.wiley.com/doi/book/10.1002/0471732699

• Chapter 1-3.4 of “Low-Power Low-Jitter On-Chip Clock Generation,” M. Mansuri, Ph.D. thesis, UCLA, 2003.• Posted on website

• Other references• M. Perrott, High Speed Communication Circuits and Systems Course, MIT

Open Courseware• Chapter 2 of Phase-Locked Loops, 3rd Ed., R. Best, McGraw-Hill, 1997.• Chapter 4 of Phase-Locked Loops for Wireless Communications, D. Stephens,

Kluwer, 2002.

Agenda

• PLL Overview

• PLL Linear Model

• PLL Stability

• PLL Units

• PLL Noise Transfer Functions

• PLL Transient Behavior

PLL Block Diagram

[Perrott]

• A phase-locked loop (PLL) is a negative feedback system where an oscillator-generated signal is phase AND frequency locked to a reference signal

PLL Applications

• PLLs applications• Frequency synthesis

• Multiplying a 100MHz reference clock to 10GHz

• Skew cancellation• Phase aligning an internal clock to an I/O clock

• Clock recovery• Extract from incoming data stream the clock frequency and

optimum phase of high-speed sampling clocks

• Modulation/De-modulation• Wireless systems• Spread-spectrum clocking

Forward Clock I/O Circuits

• TX PLL

• TX Clock Distribution

• Replica TX Clock Driver

• Channel

• Forward Clock Amplifier

• RX Clock Distribution

• De-Skew Circuit• DLL/PI• Injection-Locked Oscillator

Embedded Clock I/O Circuits

• TX PLL

• TX Clock Distribution

• CDR• Per-channel PLL-based• Dual-loop w/ Global PLL &

• Local DLL/PI• Local Phase-Rotator PLLs• Global PLL requires RX

clock distribution to individual channels

Xilinx 0.5-32Gb/s Transceiver Clocking

• LC-PLL with 2 LC-VCOs used to cover high data rates (8-32Gb/s)

• Ring-PLL used for lower data rates• CML clock distribution with active inductive loads used

for low jitter

Active Inductor based Clock Distribution

Frac-N LC PLL1, 2

Ring PLL

DCCIQ CAL

Receiver

DCCTransmitter

Channels 1-4

I/Q1, I/Q2

2PI (D,X,S)

Technology CMOS 16nm FinFET Power Supply (Vavcc, Vavtt, Vaux) 0.9 V, 1. 2V, 1.8 V

Frequency range 500 Mb/s – 32.75 Gb/s Transceiver Quad area 2.625 mm × 2.218 mm

LC PLL range 8-16.375 GHz Ring PLL range 2-6.25 GHz

TX PRBS7 jitter at 32.75Gb/s TJ: 5.39 ps, RJ: 190 fs 32.75Gb/s RX JTOL @ 30MHz

@ 100MHz 0.45 UI 0.6 UI

Channel loss at 32.75Gb/s 30 dB Measured BER at 32.75Gb/s < 10-15

Power at 32.75Gb/s with DFE 577mW/ch (17.6pJ/b)

[Upadhyaya VLSI 2016]

Agenda

• PLL Overview

• PLL Stability

• PLL Units

Linear PLL Model

• Phase is generally the key variable of interest• Linear “small-signal” analysis is useful for understand PLL dynamics if

• PLL is locked (or near lock)• Input phase deviation amplitude is small enough to maintain operation in

lock range

Phase Detector

• Detects phase difference between feedback clock and reference clock• The loop filter will filter the phase detector output, thus to characterize

phase detector gain, extract average output voltage (or current for charge-pump PLLs)

Loop Filter

• Lowpass filter extracts average of phase detector error pulses

VCO ControlVoltage

Charging

Discharging

VSSF(s)

Voltage-Controlled Oscillator

• Time-domain phase relationship

VDDVDD/20

0 1KVCO

tvKtt cVCOoutout 00

dtdt tvKtt cVCOoutout Laplace Domain Model

out(t)

Loop Divider

• Time-domain model

t outfb 1

t outoutfb 1dt1

[Perrott]

out(t) fb(t)

Phase & Frequency Relationships

• Phase Step

phaseoftime)vschange of (ratederivativefirst theisFrequency Angular

phaseandtfrequency angular with tsinusoid aConsider

frequencyin change No

sin 11

[Best]

• Frequency Step

phasein ramp a produces stepfrequency A

sinsin

tttttu

[Best]

phasein change quadratic a produces rampfrequency A

2 where

sinsin

ttttdtu

[Best]

• Frequency Ramp

Understanding PLL Frequency Response

• Linear “small-signal” analysis is useful for understand PLL dynamics if• PLL is locked (or near lock)• Input phase deviation amplitude is small enough to maintain operation in

lock range

• Frequency domain analysis can tell us how well the PLL tracks the input phase as it changes at a certain frequency

• PLL transfer function is different depending on which point in the loop the output is responding to

Input phase response VCO output response

[Fischette]

Open-Loop PLL Transfer Function

sFKKsssG VCOPD

• Open-loop response generally decreases with frequency

Closed-Loop PLL Transfer Function

NsFKKs

sGsssH

sNsFKKl

101t Determinan System

101t DeterminanPath Forward

Gain Loop

GainPath Forward

• Low-pass response whose overall order is set by F(s)

PLL Error Transfer Function

NsFKKs

ssEVCOPDref

sNsFKKl VCOPD

101t Determinan System

101t DeterminanPath Forward

Gain Loop

1GainPath Forward

• Ideally, we want this to be zero• Phase error generally increases with

frequency due to this high-pass response

PLL Order and Type

• The PLL order refers to the number of poles in the closed-loop transfer function• This is typically one greater than the number of loop

filter poles

• The PLL type refers to the number of integrators within the loop• A PLL is always at lease Type 1 due to the VCO

integrator

• Note, the order can never be less than the type

First-Order PLL

• Simple first-order low-pass transfer function

• Closed-loop bandwidth is equal to the DC loop gain magnitude

DCdBVCOPD

DCVCOPD

VCOPDs

DCVCOPD

sKKKsG

:FunctionError

:Bandwidth Loop-Closed

:FunctionTransfer

lim :MagnitudeGain Loop DC

:GainPath Forward

• Note, the “DC Loop Gain Magnitude” is not simply the PLL open-loop gain evaluated at s=0. It is

.lim0 N

• This expression cancels the VCO DC pole and allows a comparison between PLLs of different orders and types. It is useful to predict the steady-state phase error. See Gardner 2.2.3 and 5.1.1.

First-Order PLL Tracking Response• The PLL’s tracking behavior, or how the phase error responds to an input

phase change, varies with the PLL type

• Phase Step Response

frequencyin change No

sin 11

[Best]

• The final value theorem can be used to find the steady-state phase error

0limlim00

ss KssssE

• All PLLs should have no steady-state phase error with a phase step error• Note, this assumes that the frequency of operation is the same as the VCO

center frequency (Vctrl=0). Working at a frequency other than the VCO center frequency is considered having a frequency offset (step).

First-Order PLL Tracking Response

• Frequency Offset (Step)

• The final value theorem can be used to find the steady-state phase error

ss KKsssE

020limlim

• With a frequency offset (step), a first-order PLL will lock with a steady-state phase error that is inversely proportional to the loop gain

phasein ramp a produces stepfrequency A

sinsin

tttttu

[Best]

First-Order PLL Issues

• The DC loop gain directly sets the PLL bandwidth• No degrees of freedom

• In order to have low phase error, a large loop gain is necessary, which implies a wide bandwidth• This may not be desired in applications where we would like to filter

input reference clock phase noise

• First-order PLLs offer no filtering of the phase detector output• Without this filtering, the PD may not be well approximated by a

simple KPD factor• Multiplier PDs have a “second-harmonic” term• Digital PDs output square pulses that need to be filtered

Second-Order Type-1 PLL w/ Passive Lag-Lead Filter

Passive Lag-Lead Loop Filter[Allen]

2 :FunctionError

2 :Factor Damping

:Frequency Natural

:FunctionTransfer

11 :GainPath Forward

VCOPDn

nVCOPD

VCOPDVCOPD

VCOPDs

DCVCOPD

NKKsNKKs

sssKKsG

Q21 :Note

step phase a with zero be shoulderror phase Again,

limlim 22

ss ssKK

NssssE

• A second-order type-1 PLL will still lock with a phase error if there is a frequency offset!

Second-Order Type-1 PLL Tracking Response

ss KssKK

020 2limlim

Second-Order Type-1 PLL Properties

• While the second-order type-1 PLL will still lock with a phase error with a frequency offset, it is much more useful than a first-order PLL

• There are sufficient design parameters (degrees of freedom) to independently set n, , and KDC

• The loop filter conditions the phase detector output for proper VCO control

• Loop stability needs to be considered for the second-order system

• Note, this type of loop filter is typically used with a charge-pump driving it. Thus, the filter transfer function is equal to the impedance.

Second-Order Type-2 PLL w/ Passive Series-RC Lag-Lead Filter

Passive Series-RC Loop Filter

2 :FunctionError

2 :Factor Damping

:Frequency Natural

:FunctionTransfer

:GainPath Forward

VCOPDn

VCOPDVCOPD

RCsRKK

sRKKsG

step phase a with zero be shoulderror phase Again,

limlim 22

ss sssssE

• A second-order type-2 PLL will lock with no phase error with a frequency offset!

limlim 22020

ss sssssE

Second-Order Type-2 PLL Properties

• A big advantage of the type-2 PLL is that it has zero phase error even with a frequency offset• This is why type-2 PLLs are very popular

• A type-2 PLL requires a zero in the loop filter for stability.• Note, this is not required in a type-1 PLL

• This zero can cause extra peaking in the frequency response• Important to minimize this in some applications, such

as cascaded CDR systems

Agenda

• PLL Overview

• PLL Stability

• PLL Units

Feedback Configuration

ACL(s)

Here f = feedback factor (B(s) in previous slides)

[Karsilayan]

Aa pCL 100 10 :large is If

[Karsilayan]Note: a(s) can have higher-order poles

[Karsilayan]

First-Order PLL

DCdBVCOPD

DCVCOPD

VCOPDs

DCVCOPD

sKKKsG

:FunctionError

:Bandwidth Loop-Closed

:FunctionTransfer

:GainPath Forward

First-Order PLL Stability

• Open-loop Bode plots are useful for checking stability via the phase margin

• A first-order PLL is inherently stable and always has 90phase margin

(dB) log20 10 NjG

KKKsG DCVCOPD 1

2 :FunctionError

2 :Factor Damping

:Frequency Natural

:FunctionTransfer

11 :GainPath Forward

VCOPDn

nVCOPD

VCOPDVCOPD

VCOPDs

DCVCOPD

NKKsNKKs

sssKKsG

Second-Order Type-1 PLL w/ Lag-Lead Filter Stability

Norm. KDC Zeta PM0.1 0.38 42.51 1 7710 3.09 88.7

• Assuming a decade spacing between filter pole and zero

Normalizing KDC for =1

• A larger KDC provide a more stable system

DC (dB) log20 10 NjG

Second-Order Type-1 PLL w/ Lag-Lead Filter Output Response w/ Phase Step

Norm. KDC Zeta PM0.1 0.38 42.51 1 7710 3.09 88.7

• Note, time axis is scaled by sqrt(KDC) in order to view the phase step plots on one graph

Root Locus

• A Root-Locus Plot is a plot of the closed-loop poles in the complex s-plane as the loop gain changes from zero to very large

• Useful in visualizing system stability and sensitivity to variations in loop gain

• For stability, all poles should lie within the left-half plane, i.e no poles should be in the right-half plane

• A good design ensures that the poles have sufficient margin from the imaginary axis for proper stability, damping, and acceptable gain peaking

Second-Order Type-1 PLL w/ Passive Lag-Lead Filter Root Locus

:Loop-Closed 1

N:Loop-Open

2=1, 1=9• Initial pole values with

zero loop gain are the open-loop poles

1.01 021

• Final pole values with infinite loop gain are the open-loop zeros

1 1 1 pp

Second-Order Type-1 PLL w/ Passive Lag-Lead Filter Root Locus

:Loop-Closed 1

N:Loop-Open

2=1, 1=9

K1 for =10.1*K1 =0.38

10*K1 =3.09

For ≤1

Second-Order Type-1 PLL w/ Passive Lag-Lead Filter Closed-Loop Response

:Loop-Closed 1

N:Loop-Open

20*log10|H(j)|

/n t*sqrt(KDC)

Normalized Phase Step Response

Norm. KDC Zeta PM0.1 0.38 42.51 1 7710 3.09 88.7

• A larger KDC provide a more stable system and wider loop bandwidth

2 :FunctionError

2 :Factor Damping

:Frequency Natural

:FunctionTransfer

:GainPath Forward

factor gain loop a Define

VCOPDn

VCOPDVCOPD

RCKKss

RCsRKK

sRKKsG

R=1, C=1• Initial pole values with

0 0 21 pp

• Final pole values with infinite loop gain are the open-loop zeros

21 1 1 pRC

Second-Order Type-2 PLL w/ Passive Series-RC Lag-Lead Filter Root Locus

RCKKss

:Loop-Closed

N :Loop-Open

R=1, C=1

Second-Order Type-2 PLL w/ Passive Series-RC Lag-Lead Filter Root Locus

RCKKss

:Loop-Closed

N :Loop-Open

K1 for =10.1*K1 =0.38

10*K1 =3.09

Normalizing K for =1

• A larger K provide a more stable system

(dB) log20 10 NjG

Second-Order Type-2 PLL w/ Passive Series-RC Lag-Lead Filter Stability

Norm. KDC Zeta PM0.1 0.38 351 1 76.210 3.09 88.6

20*log10|H(j)|

/n t*sqrt(KDC)

• A larger KDC provide a more stable system and wider loop bandwidth

Second-Order Type-2 PLL w/ Passive Series-RC Lag-Lead Filter Closed-Loop Response

RCKKss

:Loop-Closed

N :Loop-Open

Norm. KDC Zeta PM0.1 0.38 351 1 76.210 3.09 88.6

Typical Charge-Pump PLL Loop Filter

• A secondary capacitor C2 is often added for additional filtering to reduce reference spurs

• This introduces an extra pole and potential stability concerns

VCO ControlVoltage

Charging

Discharging

VSSF(s)

CRCCCss

w/o C2

2 :Factor Damping

:Frequency Natural

withsystemorder -second a as eapproximatcan frequency,high aat is pole- third theIf

:FunctionError

:FunctionTransfer

:GainPath Forward

factor gain loop a Define

RCKKss

CCCsRC

CRCCCssRC

CNRCKKs

CRCCCs

CRCCCss

RCKKss

CCCsRC

CNRCKKs

CRCCCs

CRCCCssRC

CRCCCss

VCOPDn

VCOPDVCOPD

Third-Order Type-2 PLL w/ Passive Series-RC Lag-Lead Filter & Additional Pole

CRCCCss

R=1, C1=1, C2=0.1• Initial pole values with

11 0 021

CRCCCppp

• Final pole values with infinite loop gain

p 5 1 13,21

Third-Order Type-2 PLL w/ Passive Series-RC Lag-Lead Filter & Additional Pole Root Locus

Open Loop: N

Closed Loop:

R=1, C1=1, C2=0.1

Third-Order Type-2 PLL w/ Passive Series-RC Lag-Lead Filter & Additional Pole Root Locus

K1 for =10.1*K1 =0.38

*A third-order system doesn’t formally have a value. Here we are using the same loop parameter values as the second-order type-2 PLL for a given .

Open Loop: N

Closed Loop:

• A larger K provide a more stable system

(dB) log20 10 NjG

Second-Order Type-2 PLL w/ Passive Series-RC Lag-Lead Filter Stability

Norm. K Zeta PM0.1 0.38 351 1 76.210 3.09 88.6

• A larger K may not provide a more stable system

(dB) log20 10 NjG

Third-Order Type-2 PLL w/ Passive Series-RC Lag-Lead Filter & Additional Pole Stability

CRCCCssRC

Norm. K Zeta* PM0.1 0.38 301 1 5510 3.09 27

*A third-order system doesn’t formally have a value. Here we are using the same loop parameter values as the second-order type-2 PLL for a given .

20*log10|H(j)|

/n t*sqrt(KDC)

• If K is increased too high frequency peaking and transient ringing occurs!

Third-Order Type-2 PLL Closed-Loop Response

Norm. K Zeta* PM0.1 0.38 301 1 5510 3.09 27

Open Loop: N

Closed Loop:

Instability and the Nyquist Criterion

N1factor feedback by the multiplied gain forward theis PLL aFor

[Karsilayan]

Frequency Sweep of Loop Gain, T(s)[Karsilayan]

: PLL aFor NsGsT

Agenda

• PLL Overview

• PLL Stability

• PLL Units

PLL Units w/ Dimensionless Filter (Non-Charge-Pump PLL)

Phase Detector

• Detects phase difference between feedback clock and reference clock

• The loop filter will filter the phase detector output, thus to characterize phase detector gain, extract average output voltage

• The KPD factor can change depending on the specific phase detector circuit

66V/rad are units

:filterloop less-dimension w/ PLL

Dimension-Less Loop Filter

• Lowpass filter extracts average of phase detector signal

• No units for the dimension-less loop filter67

Example: Passive Lag-Lead Loop Filter[Allen]

Voltage-Controlled Oscillator

• Time-domain phase relationship

VDDVDD/20

0 1KVCO

tvKtt cVCOoutout 00

dtdt tvKtt cVCOoutout Laplace Domain Model

out(t)

Vsrad102

VMHz12

Vsrad are units

Loop Divider

• Time-domain model

t outfb 1

t outoutfb 1dt1

[Perrott]

out(t) fb(t)

• The loop divider is dimension-less in the PLL linear model

PLL Units w/ Dimensionless Filter (Non-Charge-Pump PLL)

70less-unit isDivider Loop

Vsrad are units

less-unit isFilter LoopV/rad are units

[Mansuri]

PLL Units w/ Impedance Filter (Charge-Pump PLL)

PDDIKK

Phase Frequency Detector (PFD)• Phase Frequency Detector allows for wide

frequency locking range, potentially entire VCO tuning range

• 3-stage operation with UP and DOWN outputs• Net difference in pulse width represents phase error• UP longer = Positive • DN longer = Negative

• Edge-triggered results in duty cycle insensitivity

• The un-averaged PFD gain (ratio of net output pulse time width with input phase error time) is typically “1” and dimension-less

Averaged PFD Transfer Characteristic

• Constant slope and polarity asymmetry about zero phase allows for wide frequency range operation

• The averaged PFD gain is typically “1/(2*pi)” with units of rad-1

UP=1 & DN=-1

[Perrott]

Charge Pump

• Converts PFD output signals to charge

• Charge is proportional to PFD pulse widths

used isdetector phasedifferent a ifcan vary gain Thisrad

Amps 2

Gain Pump-Charge & PFD Total

radAmps

2 Gain Pump-Charge Averaged

Amps Gain Pump-ChargeAveraged-Un

Loop Filter

• Lowpass filter extracts average of phase detector error pulses

• The units of the filter are ohms75

VCO ControlVoltage

Charging

Discharging

VSSF(s)

CRCCCss

w/o C2

[Mansuri]

PLL Units w/ Impedance Filter (Charge-Pump PLL)

PDDIKK

less-unit isdivider Loop

Vsrad are units , of units hasFilter Loop

radA of units hasgain combined Pump-Charge &Detector Phase Total

averaged if radA averaged,-un ifA are unitsGain Pump Charge

averaged if rad of units averaged,-un if less-unit is 1-

KOnly Average

Agenda

• PLL Overview

• PLL Stability

• PLL Units

PLL Noise Transfer Function

[Mansuri]

Input Noise Transfer Function

outn ss

RCKKss

RCKKsss

RCsNKK

Input Phase Noise:

Voltage Noise on Input Clock Source:

[Mansuri]

)1 (assumes 2

:factorgain loop aw/ PDVCOCP KN

Input Noise Transfer Function

outn ss

RCKKss

RCKKsss

RCsNKK

Input Phase Noise:

Voltage Noise on Input Clock Source:

,10 ,12

26.1 ,253

1N ,12 ,rad 2

10*2 ,1 ,1*2

ParametersSimulation

bufdelay

VGHzKAK

GHzMHz

VCO Noise Transfer Function

outn ss

RCKKss

ssHVCO

RCKKss

sT VCOVCO

VCOVCO

VCO Phase Noise:

Voltage Noise on VCO Inputs:

KVCO is different if the input is at the Vcntrl input (KVCO) or supply (KVdd)

[Mansuri]

VCO Noise Transfer Function

outn ss

RCKKss

ssHVCO

RCKKss

sT VCOVCO

VCOVCO

VCO Phase Noise:

Voltage Noise on VCO Inputs:

,10 ,12

26.1 ,253

1N ,12 ,rad 2

10*2 ,1 ,1*2

bufdelay

VGHzKAK

GHzMHz

Clock Buffer Noise Transfer Function

outn ss

RCKKss

ssHbuf

RCKKss

sT VCOdelay

VCOdelay

bufbuf

Output Phase Noise:

Voltage Noise on Buffer Inputs:

Kdelay units = (s/V)

[Mansuri]

VCOdelays

Clock Buffer Noise Transfer Function

outn ss

RCKKss

ssHbuf

RCKKss

sT VCOdelay

VCOdelay

bufbuf

Output Phase Noise:

Voltage Noise on Buffer Inputs:

,10 ,12

26.1 ,253

1N ,12 ,rad 2

10*2 ,1 ,1*2

bufdelay

VGHzKAK

GHzMHz

28GHz PLL Phase Noise Example

• Charge pump noise dominates at low frequencies• VCO noise at mid-band and high frequencies• Output buffers outside loop dominate at high frequencies

With ~100fs target, no single dominant source -every component contributes

Frequency Offset (Hz) [Turker ISSCC 2019]

PLL Noise Transfer Function Take-Away Points

• The way a PLL shapes phase noise depends on where the noise is introduced in the loop

• Optimizing the loop bandwidth for one noise source may enhance other noise sources

• Generally, the PLL low-pass shapes input phase noise, band-pass shapes VCO input voltage noise, and high-pass shapes VCO/clock buffer output phase noise

Agenda

• PLL Overview

• PLL Stability

• PLL Units

Linear PLL Model

• If the phase input amplitude is small, then the linear model can be used to predict the transient response

NsFKKs

ssEVCOPDref

• Ideally, we want this to be zero• Phase error generally increases with

frequency due to this high-pass response

step decayingly exponentiaan is ResponseTransient

:ResponseTransient

step phase a with zero be shoulderror Phase

0limlim :Theorem Value Final theUsing

DCeKss

KsssssE

ssEKsF VCOPDdBDC

dBVCOPD

311 , ,

• Frequency Offset (Step) Response

step risingly exponentiaan is ResponseTransient

1 :ResponseTransient

offsetfrequency again with loop the tonalproporitioinversely iserror phase The

limlim :Theorem Value Final theUsing

DCDCss

DCeKKs

KKsssssE

ssEKsF VCOPDdBDC

dBVCOPD

311 , ,

• Frequency Ramp Response

1 :ResponseTransient

finite is ifinfinity togrow error will phase The

rad/sec of rate aat ith timelinearly w changing isfrequency input that theAssume

DCetKKKs

KsssssE

ssEKsF VCOPDdBDC

dBVCOPD

311 , ,

sssF VCOPD

DCDCDCnn

yourself thiscompute Try to

:ResponseTransient

DCDCss

sssF VCOPD

DCDCDCnn

:ResponseTransient

offsetfrequency again with loop the tonalproporitioinversely iserror phase The

DCDCDCss

KKsKss

sssF VCOPD

DCDCDCnn

:ResponseTransient

finite is ifinfinity togrow error will phase The

DCDCss

RCKKss

RCKKsss

sssEs ss

:ResponseTransient

RCKKss

sF VCOPD

RCKKss

21 :ResponseTransient L

Second-Order Type-2 PLL Phase Step Response

KRCRCn

RCKKss

RCKKsss

sssEs ss

:ResponseTransient

PLL 2-Type a with zero togoeserror phase The

RCKKss

sF VCOPD

Second-Order Type-2 PLL Frequency Step Response

KRCRCn

RCKKss

RCKKsss

sssEs n

:ResponseTransient

lag phase dynamic a with rampfrequency acan track PLL 2-order type-secondA

RCKKss

sF VCOPD

Second-Order Type-2 PLL Frequency Ramp Response

KRCRCn

RCKKss

Ideal Phase Detector

• An ideal phase detector has the same gain (slope) over a 2 range

• This allows the linear PLL model to be used for all phase relationships

Real Phase Detectors

• Many phase detectors are nonlinear and do not display the same gain for a given phase relationship

• This implies that the PLL cannot be described by the linear model for large input phase deviations

PLL Frequency Step Response:Linear vs Behavioral Model

ref(s)=Frequency Step Input: s2 = Mrad/sec

No Cycle Slips Observedwith Linear Model

Cycle Slips

• Due to non-linearities in loop components (primarily the PD), a real PLL’s response can vary significantly from the linear model

PLL Hold Range (Sinusoidal PD)• A PLL Hold Range is the input frequency range over which the PLL can

maintain static lock

rad/sec :Range Hold

todconstraine isfrequency lock the,1 exceedcannot sine Since

iserror phase thedetector, phase sinusoidal aWith

:2-TypeOrder -Second

:1-TypeOrder -Second

:Order-First

isError Phase State-Steady theModelLinear w/

VCOPDDC

• The hold range is finite for a type-1 PLL, and theoretically infinite for a type-2 PLL. However in practice it will be limited by another PLL block, such as the VCO tuning range.

First-Order PLL Phaselock Acquisition (Sinusoidal PD)

orefref

and is phaseinput

thesuch that , fromdifferent frequency aat is signalinput theAssume

sin :OutputDetector Phase Sinusoidal

:Frequency ousInstantane VCO

PDsinusoidalawith PLLorder -firstsimpleaAssuming

PDVCOee

oePDVCOorefoutrefe

oePDVCOoout

ocVCOoout

KKKtKdt

dKKtdvKtt

wheresind

equation aldifferentinonlinear following theyields time w.r.t. thisatingDifferenti

iserror phase PLL The

is phaseoutput PLLThe

First-Order PLL Hold Range (Sinusoidal PD)

todconstraine isfrequency lock the,1 exceedcannot sine Since

locked,isPLLtheIf

rad/sec :Range Hold KH

KK sin

Kby equation aldifferentiPLLorder -first thegNormalizin

unstable are nulls slope-positive while

points,lock stable are nulls slope-Negative

0 wherenulls 2 are thereplot, plane-phase In the dtd e

• Every cycle (2 interval) contains a stable null, thus ecannot change by more than one cycle before locking

• There is no cycle slipping in the locking process• A cycle slip occurs when the phase error changes by more

than 2 without locking

Error,Frequency Normalized

e Error,Phase

First-Order PLL Phaselock Acquisition Time (Sinusoidal PD)

tlysignifican increasecan andion approximatlinear thisfrom

deviate willresponse thelarge, is 0 if However,

response step phase modellinear theissolution eapproximat the

,sinsuch that small, is 0 and zero is If

solveformally toneed wetime,acquistionphaselock thefind order toIn

Ktoute

oePDVCOe

• If the frequency offset exceeds the PLL hold range, the phase error will oscillate asymmetrically as the PLL undergoes cycle slips

First-Order PLL Lock Failure (Sinusoidal PD)

First-Order PLL VCO Control Voltage

rad/sec :Range Hold KH

Second-Order Type-2 PLL PhaselockAcquisition (Sinusoidal PD)

0sin1sin0

is phaseoutput PLL The

sin1sin1

as expressed becan domain - timein the responsefilter The

PDsinusoidalawith PLL2-order type-secondaAssuming

0 010 1

ePDVCOoout

ocVCOoout

ePDePD

dddKKtdvKtt

dKKdvtvtv

eeePDVCOe

ePDVCOorefoutrefe

dddKKt

sin1cos

equation aldifferentinonlinear following theyields time w.r.t. twice thisatingDifferenti

0sin1sin

iserror phasePLLThe

0 010 1

0sincos2

following theyieldsequation aldifferentinonlinear theinto thisngSubstituti

arefactor dampingandfrequency naturalthePLL,2-TypeOrder -Second For this

eneene

VCOPDVCOPDn

• No closed form solution exists, and numerical techniques are required to solve

0sincos2 2

eneene

Acquisition with a phase error

time vs and

ee ee vs :Plot Plane Phase

Second-Order PLL Phase Plane Plots (Sinusoidal PD)

0sincos2 2

eneene

• An unstable singularity is called a Saddle Point

• A trajectory that terminates on a saddle point is called a “Separatrix”

• If a trajectory lies between the 2 separatrices, it will lock without cycle slipping

• If a trajectory lies outside the 2 separatrices, it will cycle slippling one or more times before locking (if at all)

Second-Order PLL Pull-Out Range and Lock Time (Sinusoidal PD)

(Hz) 41

,11 Assuming

bandwidth noise PLL theis Here,

10% than lesserror phasefor

as edapproximat becan timeacquistion PLL therange,out -pull than theless is stepfrequency a If

1.4 and 0.5between for

Lnfreqphaseacq

• The Pull-Out Range is the maximum frequency step that can occur before the loop locks without cycle slipping

Second-Order PLL Locking Outside of the Pull-Out Range (Sinusoidal PD)

• Multiple cycle slips are observed before the loop locks

Next Time

• Phase Detector Circuits

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