ece 497 js lecturejsa.ece.illinois.edu/ece497js/lect_01.pdf · title: microsoft powerpoint -...

ECE 497 JS LectureIntroduction

Spring 2004

Jose E. Schutt-AineElectrical & Computer Engineering

University of Illinoisjose@emlab.uiuc.edu

Outline

Trends in electronics industry

Motivations for SI-based design

References

Activities at home* Telecommuting / home* Teleshopping / home banking* Home medical and health care

Information-oriented living* Shopping / events / traffics* Pastime / learning / sightseeing* Administrative services for residents

Pursuing comfortable labor* Remote and mobile offices* Remote control, unattended factory* Collaboration environment

Voice64 kbps

Documentsand drawings

128 kbps

3D-CG1 Mbps

HD stillimages1 Mbps

Video images1 Mbps

NTSC images6 Mbps

HDTV images26 Mbps

Required media andthe amount of information

100 Mbps per home

Demand in the Information Age

Source: ITRCS

1980 1985 1990 1995 2000 2005 2010A

Limits of Optical

Future System Needs and Functions

Auto Digital Wireless

Consumer Computer

High bandwidth High-speed Digital

Analog, RF

time time

Before Today

Integration & Signal SpeedIntegration & Signal Speed

Chip size(mm2)

Number of transistors(million)

Interconnect width(nm)

Total interconnect length(km)

1997 2003 20122006

300 430 750520

11 76 200 1400

200 100 70 35

2.16 2.84 5.14 24

Semiconductor Technology TrendsSemiconductor Technology Trends

650 595 540 485Generation (nm)

SPEED/PERFORMANCE ISSUE

Gate Delay

Sum of Delays, Al & SiO2

Sum of Delays, Cu & Low K

Interconnect Delay, Al & SiO2

Interconnect Delay, Cu & Low K

430 375 320 265 210 155 100

Gate wi Al & SiO2

Al 3.0 µΩ -cmCu 1.7 µΩ -cmSiO2 κ = 4.0Low κ κ = 2.0Al & Cu .8µ ThickAl & Cu Line 43µ Long

The Interconnect BottleneckThe Interconnect Bottleneck

TechnologyGeneration

MOSFET IntrinsicSwitching Delay

ResponseTime

1.0 um

0.01 um

~ 10 ps

~ 1 ps

~ 100 ps

ChipChip--Level Interconnect DelayLevel Interconnect DelayLine

0 0.4 0.8 1.2 1.6 2Time (ns)

Far End Response

BoardVLSISubmicronDeep Submicron

0.8 1.2 1.6 2Time (ns)

Near End Response

BoardVLSISubmicronDeep Submicron

Pulse Characteristics: rise time: 100 ps fall time: 100 ps pulse width: 4ns

Line Characteristics length : 3 mm near end termination: 50 Ω far end termination 65 Ω

LogicthresholdLogic

threshold

TransmissionChannel

Common

Signal Integrity

Crosstalk Dispersion Attenuation

Reflection Distortion Loss

Delta I Noise Ground Bounce Radiation

Sense Line

Drive Line

Interconnect BottleneckInterconnect Bottleneck

Signal Degradation

• Simultaneous switching and inductance (Leff)

• Leff is f( current magnitude and direction)

• Interactions between noise generated by power/ground and signal paths

Mixed Signal NoiseMixed Signal Noise

Power bus

Interconnect

Analog Digital

coupled noise

Substrate

Power bus

Interconnect

bond InductanceChip-packageinterconnect

Intel LG440X Mother Board

Packages & Packaging TrendsPackages & Packaging Trends

Quad Flat Pack Thermal Package

Top pads

Signal 1- Ground 1

Signal 2 - Vcc1

Signal 3- Ground 2

Signal 4 - Vcc2

Bottom pads

Levels of Interconnections- Chip level

- Package level

- Board level

- Backplane

- Cables

Domains- RF

- Digital

- Mixed-Signal

Interconnect SchemesInterconnect Schemes

Board Level Complexity

- Up to 16 layers- Hundreds of vias- Thousands of TLs- High density- Nonuniformity

Damascene Process(IBM)

- 6 layers of metallization- Copper- Channel length of 0.12 um- Resistivity 45% lower than Al- Prevent copper from diffusing into Si

Key Features

Packaging of RF Systems

* Dominated with Passive & Reactive Components

* Scale with Frequency rather than Technology

* Packaging Dominated by Transmission Lines

* A/D Packaging Requirements Very Stressing

* High Quality Factor for Resonant Systems

* Reduce or control Mixed-Signal Noise

Design Verification

Behavior Design

Behavior Synthesis RTL

Synthesis Place and

Custom Design

RTL Design

Layout Verif.

Parasitic Extraction

Floorplanning

Functionality TimingFab

Design for Test Chip Test

Module Reuse

Hardware/SoftwarePartitioning

Arch. Analysis

Customer

Analog/RF Design

tight integration required

Design FlowDesign Flow

DesignSpecification

FunctionalDesign

LogicDesign

CircuitDesign

PhysicalDesign

fabrication

extraction andverification

circuitanalysis

logicsimulation

functionalsimulation

specification

behavioralrepresentation

structuralrepresentation

physicalrepresentation

requirements

Deep Submicron Timing Closure

Unbounded design iterations resulting from unpredicted timing violations

- 0.25 microns and lower- 2 to 20 iterations- mismatch between logic and physical designs - greater timing variations- dominated by interconnects- inductive and capacitive coupling- slows time-to-market

Expert SystemExpert System

V = ZI

∇2V = k2V

∇2V = 0

∂V∂x

= Z∂I∂t

V = ZI

Large Networks

Full-Wave Analysis

Lumped Circuits

Distributed Circuits

Quasi-Static Analysis

Framework

SPICE EngineSolvers & Libraries

NetworkExtractor

MeshGenerator

FastSolvers

Optimizers

Interconnect

2D/3D geometry

IBISTranslator

Level I Level I FullFull--Wave MethodsWave Methods

∇ ×

r E = −

∂r B

∇ ×

r J + ∂

∇ ⋅r B = 0

∇ ⋅r D = ρv

FDTD: Discretize equations and solve with appropriate boundary conditions

Level II Level II QuasiQuasi--Static ExtractionStatic Extraction

CAPACITANCE

* MoM- BEM

INDUCTANCE

* MoM- BEM (2D)

* FEM (2D)

* PEEC (3D)

Level III Level III Transmission Line SimulationTransmission Line Simulation

* Method of Characteristics

* Transform Method

* Green’s Function Method

* Model Order Reduction Method

Level IVLevel IVCircuit SimulationCircuit Simulation

* Modified Nodal Analysis (MNA)

* Waveform Relaxation

* Harmonic Balance

Level VLevel VCircuit SimulationCircuit Simulation

* Asymptotic Waveform Evaluation

* Complex Frequency Hopping

* Passive Multipoint Matching Method

* Latency Insertion Method

Large Network (>1,000 nodes)

Reduced Order Model

(< 30 poles)

SPICE Y(t) v(t) = i(t) Y(ω) V(ω) = I(ω)

Order Reduction

Y(ω) = Y(ω)~ ~

Recursive Convolution

Y(t) v(t) = i(t) ~

MOR Schemes* AWE

* Padé via Lanczos

* Complex frequency hopping

* Direct rational approximation

Model Order ReductionModel Order Reduction

MulticonductorMulticonductor Line SimulationLine Simulation

Established platform

Powerful engine

Source code available for free

Extensive libraries of devices

New device installation procedure straightforward

Why SPICE ?Why SPICE ?

spice3f4

conf examples lib doc

helpdir scripts

utiltmppatches srcnotesman

man1 man3 man5 unsuppobin include lib skeleton

ckt cp dev fte hlp inp mfb mfbpc misc ni sparse mac

asrc bsim1 bsim2 cap cccs ccvs csw dio disto ind isrc mes

ltrajfet

mos2 mos3 mos6 res sw tra urc vccs vcvs vsrc

Parser StampFromNetlist I=YVDevice To

Solver

Directory Structure

SPICESPICE

Orion Cluster

Welcome To EPEP13th Topical Meeting

on Electrical Performance of

Electronic PackagingEPEP 2004Sponsors:

The IEEE Microwave Theory and Techniques SocietyThe IEEE Components,

Packaging and Manufacturing Technology Society

October 25 - 27, 2004

Portland, Oregon

http://www.epep.org/

http://groups.yahoo.com/group/si-list/

si-list is a signal integrity mail list intended for theinterchange of technical information amongst membersof the si community in both industry and academia around the world.

SI SI ––List/NewsgroupList/Newsgroup

ece 497 js lecturejsa.ece.illinois.edu/ece497js/lect_01.pdf · title: microsoft powerpoint -...

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