dynamic logic circuits

Kalyan Kumar KalitaM.Tech(ECE)

Roll No:- 1403206003GIMT Azara

E-mail: kalita.k3@gmail.com

10/30/2014 1

Dynamic Logic

Dynamic logic circuits offer severalsignificant advantages over static logiccircuits.

The operation of all dynamic logic gatesdepends on temporary storage of charge inparasitic node capacitances, instead ofrelying on steady-state circuit behavior.

10/30/2014 2

Dynamic logic circuits require periodicclock signals in order to control chargerefreshing.

The capability of temporary storing a state,at a capacitive node allows us to implementvery simple sequential circuits with memoryfunctions.

Common clock signals synchronize theoperation of various circuit blocks.

10/30/2014 3

Power consumption increases with theparasitic capacitances.

Therefore dynamic circuit implementationin smaller area, consumes less power thanthe static logic.

10/30/2014 4

Dynamic CMOS TG Logic

10/30/2014 5

TG Dynamic Shift Register

10/30/2014 6

Single Phase TG Shift Register

10/30/2014 7

Precharge-Evaluation Logic

10/30/2014 8

Domino CMOS Logic

10/30/2014 9

Domino CMOS Logic

10/30/2014 10

Cascading Domino CMOS Logic

10/30/2014 11

NORA Logic

10/30/2014 12

When the clk signal is low, the output nodes of nMOSlogic blocks are pre-charged to VDD through the pMOSpre-charge transistors, whereas the output nodes of pMOS logic blocks are pre-discharged to 0V through the nMOS discharge transistors driven by ø.

10/30/2014 13

When the clock signal makes a low to high transition,where as the inverted signal makes a high-to-lowtransition simultaneously, all cascaded nMOS andpMOS logic states evaluate one after the other, muchlike the domino CMOS Logic.

The advantage of NORA CMOS logic is that a staticCMOS inverter is not required at the output of everydynamic logic stage.

10/30/2014 14

NORA CMOS Logic Circuit

10/30/2014 15

NORA CMOS Logic Circuit

10/30/2014 16

Zipper CMOS Logic Circuit

10/30/2014 17

TSPC Dynamic CMOS

10/30/2014 18

Charge Leakage The operation of a dynamic gate relies on the dynamic

storage of the output value on a capacitor. If the pull-down network is off, the output should remain at theprecharged state of VDD during the evaluation stage.This current gradually leaks away due to leakagecurrents.

Source 1 and 2 are the reversed-biased diode andsubthreshold leakage of the NMOS pull-down deviceM1, respectively. The charge stored on CL will slowlyleak away through these leakage channels.

10/30/2014 19

Dynamic circuit therefore require a minimal clock rate,

which is typically on the order of a few kHz. Note thatthe PMOS precharge device also contributes someleakage current due to the reverse bias diode and thesubthreshold conduction.

Leakage is caused by the high-impedance state of theoutput node during the evaluate mode, when the pull-down path is turned off. The leakage problem may becounteracted by reducing the output impedance onthe output node during evaluation. This is often doneby adding a bleeder transistor. The only function of thebleeder –an NMOS style pull-up device.

10/30/2014 20

10/30/2014 21

Charge Sharing

10/30/2014 22

Another important concern in dynamic logic is theimpact of change sharing. During the precharge phase,the output node is precharged to VDD. Assume that allinputs are set to 0 during precharge, and that thecapacitance Ca is discharged. Assume further thatinput B remains at 0 during evaluation, while input Amakes a 0-1 transition, turning transistor Ma on. Thechange stored originally on capacitor CL isredistributed over CL and Ca. This causes a drop in theoutput voltage, which cannot be recovered due to thedynamic nature of the circuit.

10/30/2014 23

Thank U

10/30/2014 24