dispositivi e sistemi logici
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2.2
Small Scale of Integration (SSI)Part Name Function
*74*00 Quad 2-Input NAND Gates
*74*01 Quad 2-Input NAND Gates Open Collector
*74*02 Quad 2-Input NOR Gates
.. ..
*74*04 Hex Inverter
.. ..
*74*10 Triple 3-Input NAND Gates
.. ..
*74*20 Dual 4-Input NAND Gates
.. ..
*74*137 3 to 8 Decoder Multiplexer
.. ..
*74*169 Sync. Up/Down Binary Counter
.. ..
*74*175 Quad D Flip-Flop
.. ..
*74*1244 Octal Bus/Line Driver
2.3
Progettazione SSI
1
1
2
2
3
3
4
4
D D
C C
B B
A A
Title
Number RevisionSize
A3
Date: 25/09/2003 Sheet of File: C:\Inetpub\..\74xx.SchDoc Drawn By:
1
23
74AC00MTC
U5A
CLR1
CLK9
D14
Q12
Q13
D25
Q27
Q26
D312
Q310
Q311
D413
Q415
Q414
VCC16
GND8
74AC00MTC
U4
56
4
74AC00MTC
U2B
89
10
74AC00MTC
U2C
U/D1
LD9
ENT10
ENP7
CLK2
RCO15
A3
QA14
B4
QB13
C5
QC12
D6
QD11
VCC16
GND8
DM74ALS169BN
U6
910
1213
8
DM74ALS21AN
U1B
8
910
DM74ALS02N
U3C
11
1213
DM74ALS02N
U3D
A
B
C
D
E
CLK
CLR
VCC
VCC
CLK
CLK
OUT0OUT1OUT2OUT3
OUT[0..3]
RCO
1
23
74AC00MTC
U2A
2
31
DM74ALS02N
U3A
5
64
DM74ALS02N
U3B
12
45
6
DM74ALS21AN
U1A
Instance Name
Part Name
Sub-Part Name
2.5
Very Large Scale of Integration
3 – Input NAND
Full Custom
Standard Cell
Gate Array
Vengono disegnate tutte le maschereCosti di progetto elevatissimiCosti di realizzazione elevatissimi
Basata su celle predisegnateCosti di progetto ElevatiCosti di realizzazione elevati
Vengono Disegnate le sole interconnessioniCosti di progetto ElevatiCosti di realizzazione meno bassi (Non Riprogrammabili)
(Non Riprogrammabili)
2.6
Logic DevicesASIC (Application Specific Integrated Circuit)
• Standard Cell
• Gate Array
PLD (Programmable Logic Devices)
• SPLD (Simple PLD)• PLA (Programmable Logic Array) • PAL (Programmable Array Logic)• GAL (Generic Array Logic)
• CPLD (Complex PLD)
• FPGA
Programmate durante la produzione nella Fab
Re/Programmabili sul campo
Re/Programmabili nel circuito
2.7
Prime Strutture PLD
Programmable Logic Array (PLA)
Programmable Array Logic (PAL)
IN1IN2IN3INn
OUT1OUT2OUT3OUTm
IN1IN2IN3INn
OUT1
OUTm
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