digital systems tce1111 1 shift registers and shift register counters week 10 and week 11 (lecture 2...

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DIGITAL SYSTEMS TCE1111

Shift Registers and Shift Register Counters

Week 10 and Week 11(Lecture 2 of 2)

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Shift Register is one of the most widely used functional device in Digital Systems. The simple pocket calculator illustrates the shift register’s characteristics.How Shift Register Works ?

If a 4-bit shift Register receives 4-bits of parallel data and shift them to the right four positions into some other device

STEP-1

1 QD

1 QD

0 QD

0 QD

0

CLOCK

0

XXXX

1 0 0 0Parallel load a 1000:

Serial receiving device

Cp Cp Cp CpCLOCK INPUT

X=Undetermined State

Shift Register

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DIGITAL SYSTEMS TCE1111

STEP -2

STEP -3

1 QD

0 QD

1 QD

0 QD

0

CLOCK

0

XXX0

1 0 0 0

Cp Cp Cp Cp

Apply pulse 1:

1

1 QD

0 QD

0 QD

1 QD

0

CLOCK

0

XX00

1 0 0 0

Cp Cp Cp Cp

Apply pulse 2:

2

Shift Register

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STEP - 4

STEP -5

1 QD

0 QD

0 QD

0 QD

1

CLOCK

0

X000

1 0 0 0

Cp Cp Cp Cp

Apply pulse 3:

3

1 QD

0 QD

0 QD

0 QD

0

CLOCK

0

0001

1 0 0 0

Cp Cp Cp Cp

Apply pulse 4:

4

Shift Register

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One method of identifying Shift Registers is how data is loaded into and read from the storage unit. There are Four Categories of Shift Registers.

Shift Register

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Serial in/serial out shift register.• Serial entry of data into a shift register.

• A 4-bit device implemented with D flip-flop.

Shift Register

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Four bits (1010) being entered serially into the register.• The register is initially clear.

• The 0 is put onto the data input line, when the 1st. Clock pulse, FF0 is reset, thus storing 0.

• Next the 2nd. Bit 1, is applied to the data input, making D=1 for FF0 and D=0 for FF1, when 2nd. Clock pulse occurs, the 1 on the data input is shifted into FF0, and the 0 was in FF0 is shifted into FF1.

• The 3rd. Bit, a 0 is put onto the data input line, and a clock pulse is applied, the 0 is entered into FF0, the 1 stored in FF0 is shifted into FF1, and the 0 stored in FF1 is shifted into FF2.

• The last bit, a 1, is now applied to the data input and a clock pulse is applied. This time the 1 is entered into FF0, the 0 stored in FF0 is shifted into FF1, the 1 stored in FF1 is shifted into FF2, and the 0 stored in FF2 is shifted into FF3.

• This complete the serial entry of four bits into the shift register.

Shift Register

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Four bits (1010) being entered serially into the register.

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Assumed that the registers is initially cleared. Show the state of the 5-bit register for the specified data input and clock waveforms.

Shift Register

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A serial in/parallel out shift register.

• Figure shows a 4-bit serial in/parallel out shift register and its logic block symbol.

Shift Register

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Show the of the 4-bit register for the data input and clock waveforms. The register initially contains all 1’s.

The register contains 0110 after 4 clock pulses.

Shift Register

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A 4-bit parallel in/serial out shift register.

Shift Register

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A 4-bit parallel in/serial out shift register.

• There are four data-input lines, D0, D1, D2, D3 and a SHIFT/LOAD input, which allows four bits of data to load in parallel into the register.

• When SHIFT/LOAD is LOW, gates G1 through G3 are enabled, allowing each data bit to be applied to the D input of its respective flip-flop.

• When a clock is applied, the flip-flops with D=1 will set and those with D=0 will reset, thereby storing all four bits simultaneously.

• When SHIFT/LOAD is HIGH, gates G1 through G3 are disabled and G4 through G6 are enabled, allowing the data bits to shift right from one stage to the next.

• The OR gates allow either the normal shifting operation or parallel data-entry operation, depending on which AND gates are enabled by the level on the SHIFT/LOAD input.

Shift Register

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Show the data-output waveform for a 4-bit register with the parallel input data and the clock and SHIFT/LOAD waveforms given.

Shift Register

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A parallel in/parallel out register.

Shift Register

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• The 74HC195 can be used for parallel in/parallel out operation. It also can be used for serial in/serial out and serial in/parallel out operation.

Shift Register

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It can be used for parallel in/parallel out by using Q3 as the output.

• When the SHIFT/LOAD input is LOW, the data on the parallel inputs are entered synchronously on the positive transition of the clock.

• When SHIFT/LOAD is HIGH, stored data will shift right (Q0 to Q3) synchronously with the clock.

• Inputs J and K are the serial data inputs to the first stage of the register (Q0); Q3 can be used for serial output data.

• The active-LOW clear input is asynchronous.

Shift Register

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Sample timing diagram for a 74HC195 shift register.

Shift Register

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4-Bit Bidirectional Shift Register-Logic Diagram

Shift Register

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4-Bit Bidirectional Shift Register-Operation • A HIGH on the control input allows data bits inside the

register to be shifted to the right and a LOW enables data bits inside the register to be shifted to the left.

• When the control input is HIGH, gates G1 through G4 are enabled, and the state of the Q output of each flip-flop is passed through to the D input of the following flip-flop. When a clock pulse occurs, the data bits are shifted one place to the right.

• When the control input is LOW, gates G5 through G8 are enabled, and the Q output of each flip-flop is passed through to the D input of the preceding flip-flop. When a clock pulse occurs, the data bits are then shifted one place to the left.

/RIGHT LEFT

/RIGHT LEFT

/RIGHT LEFT

Shift Register

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4-Bit Bidirectional Shift Register-Timing Diagram

Assume that initially Q0=1, Q1=1, Q2=0, and Q3=1 and the serial data-input is LOW. Timing diagram for the given control input waveform is given below:

/RIGHT LEFT

Shift Register

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The Johnson Counter

• A Johnson counter will produce a modulus of 2n.

• A 4-bit device has a total of 8 states and the 5-bit device has a total of 10 states.

• The implementation of a Johnson counter is the same regardless of the number of stages.

• The Q output of each stage is connected to the D input of the next stage, except the Q output of the last stage is connected back to the D input of the first stage.

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The Johnson CounterClock Pulse Q0 Q1 Q2 Q3

0 0 0 0 0

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

7 0 0 0 1

Four-bit Johnson sequence:

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The Johnson Counter

Clock Pulse Q0 Q1 Q2 Q3 Q4

0 0 0 0 0 0

1 1 0 0 0 0

2 1 1 0 0 0

3 1 1 1 0 0

4 1 1 1 1 0

5 0 1 1 1 1

6 0 1 1 1 1

7 0 0 1 1 1

8 0 0 0 1 1

9 0 0 0 0 1

Five-bit Johnson sequence:

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The Johnson Counter

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The Johnson Counter Timing sequence for a 4-bit Johnson counter

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The Johnson Counter• Timing sequence for a 5-bit Johnson counter

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Logic diagram for a 10-bit ring counter.

• The interstage connections are the same as those for a Johnson counter, except that Q rather than Q is fed back from the last stage.

The Ring Counter

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10-bit ring counter sequence

CLOCK PULSE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9

0 1 0 0 0 0 0 0 0 0 0

1 0 1 0 0 0 0 0 0 0 0

2 0 0 1 0 0 0 0 0 0 0

3 0 0 0 1 0 0 0 0 0 0

4 0 0 0 0 1 0 0 0 0 0

5 0 0 0 0 0 1 0 0 0 0

6 0 0 0 0 0 0 1 0 0 0

7 0 0 0 0 0 0 0 1 0 0

8 0 0 0 0 0 0 0 0 1 0

9 0 0 0 0 0 0 0 0 0 1

The Ring Counter

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If a 10-bit ring counter has the initial state 1010000000, determine the waveform for each of the Q outputs.

The Ring Counter