digital logic electricity, gates, components. digital logic reading: appendix c through c.3 the...

DIGITA

L LOGIC

ELECTR

ICIT

Y, G

ATES, C

OMPONENTS

DIGITAL LOGIC READING: APPENDIX C THROUGH C.3

The Student shall be able to:

• Define voltage, current, resistance, volts, amps, ohms.

• Recite ohm’s law

• Draw the symbol for AND, OR, XOR, NAND, NOR, NOT.

• Write mathematical statements using AND, OR, XOR, NOT.

• Prepare a truth table.

• Prepare a truth table for AND, OR, XOR, NOT.

• Design a circuit using Sum of Products.

• Design an efficient solution using a Karnaugh Map or K-Map.

• Define decoder, multiplexor, parity, adder, and recognize their circuit diagrams.

• Design a circuit with Logic Circuit

ELECTRICITY

Voltage = DepthCurrent = SpeedResistance = Work or Obstructions

voltage current

resistance

RESISTANCE: MEASURED IN OHMS Ω

Voltage => Volts = V

Current => Amperes = Amps = A

Resistance => Ohms = Ω

ELECTRICITY: NOTATION

Voltage = Current * Resistance (V=IR)Resistance = Voltage/Current (R=V/I)

Example:Given:•Voltage = 10 V•Resistance = 1k ΩWhat is Current?•Current = I = V/R = 10/1000 = 1/100 = 0.01 A =10 mAmps

OHM’S LAW: V=IR

ELECTRONIC BREADBOARD

Notch = DirectionVCC =PowerGND = Ground4 NAND Gates

DIP Package

A DIGITAL LOGIC CHIP

OR, AND, NOT

AND: ∙ &EXAMPLE: 1 ∙ 0 = 0

TruthTable

0 1

0 0 0

1 0 1

OR: +EXAMPLE: 1 + 0 = 1

Clock Alternates – 1 - 0

+TruthTable

0 1

0 0 1

1 1 1

XOREXAMPLE: 1 XOR 0 = 1

Clock Alternates – 1 - 0

XORTruthTable

0 1

0 0 1

1 1 0

ADDITIONAL ELECTRONIC GATES

NAND

NOR

XOR

XNOR

or

LED DISPLAY

Top Bottom LeftTop Right Top LeftBottom Right MiddleBottom Period

BUILDIN

G DIG

ITAL

COMPONEN

TS MultiplexorAdderDecoder

MULTIPLEXER - DEMULTIPLEXER

Multiplexer Demultiplexer

selector

MULTIPLEXER: SELECTS ONE INPUT

A

B

S

How is the solution provided mathematically?

Out

MULTIPLEXER: SELECTS ONE INPUT

A

B

S

Out

Out = (A !S) + (B S)

A, B: Input bits

S: Sum

S = A XOR B

C: Carry

C = A & B

Notice there is no Carry-in

HALF ADDER

FULL ADDER

FULL ADDER

ENCODER - DECODER

EncoderEncoder DecoderDecoderInput

Output

DECODER

DecoderDecoder

Input Output

0 0 0 0 0 0 0 0 0 0 1

0 0 1 0 0 0 0 0 0 1 0

0 1 0 0 0 0 0 0 1 0 0

0 1 1 0 0 0 0 1 0 0 0

1 0 0 0 0 0 1 0 0 0 0

1 0 1 0 0 1 0 0 0 0 0

1 1 0 0 1 0 0 0 0 0 0

1 1 1 1 0 0 0 0 0 0 0

DECODER: SUMS OF PRODUCT SOLUTION

Input Output

0 0 0 0 0 0 0 0 0 0 1

0 0 1 0 0 0 0 0 0 1 0

0 1 0 0 0 0 0 0 1 0 0

0 1 1 0 0 0 0 1 0 0 0

1 0 0 0 0 0 1 0 0 0 0

1 0 1 0 0 1 0 0 0 0 0

1 1 0 0 1 0 0 0 0 0 0

1 1 1 1 0 0 0 0 0 0 0

2 1 0 7 6 5 4 3 2 1 0

DESIG

NING A

CIR

CUIT

1. Define the Truth Table

2. Write Sum of Products

3. Optimize4. Develop circuit

Exa

mple

: Par

ity

PARITY

Used in Data Communications, RAID disk systems

Even Parity Example: Each Byte sums to even number of 1-bits

0000000 -> 0

1111111 -> 1

0101010 -> 1

1000001-> ?

Odd Parity Example: Each 3 bits sums to odd number of 1-bits

00-> 1

10 -> 0

11-> ?

Enables ERROR CHECKING, Sometimes ERROR CORRECTION

STEP 1: PROVIDE TRUTH TABLEEVEN PARITY: OUTPUT ASSURES EVEN 1 DIGITS

STEP 2: WRITE SUM OF PRODUCTS

STEP 3: OPTIMIZE

LAWS

Commutative Law:

A+B = B+A

AB = BA

Associative Law:

A+(B+C)=(A+B)+C

A(BC) = (AB)C

Distributive Law:

A(B+C) = AB + AC

BOOLEAN ALGEBRA

STEP 4: DEVELOP CIRCUIT … LOGIC CIRCUIT

Green = 01

Yellow = 10

Red = 00

Succession:

Green 01 -> Yellow 10

Yellow 10 -> Red 00

Red 00 -> Green 01

TRAFFIC LIGHT

TRAFFIC LIGHT: DESIGN

STEP 1:

PROVIDE TRUTH TABLE

IN0 IN1 OUT0

OUT1

0 0 0 1

0 1 1 0

1 0 0 0

STEP 2:

WRITE SUM OF PRODUCTS

OPTIM

IZAT

ION:

KARNAUGH MAPS

(K-

MAPS)

AN OPT

IMIZ

ATIO

N TECHNIQ

UE

TRAFFIC LIGHT: DESIGN

STEP 1:

PROVIDE TRUTH TABLE

IN0 IN1 OUT0

OUT1

0 0 0 1

0 1 1 0

1 0 0 0

STEP 2:

DEVELOP K-MAP

COMPARISON: TRUTH TABLE VS. K-MAP

TRUTH TABLE

Left columns: Input

Right columns: Output

KARNAUGH MAP

IN0 IN1 OUT0

OUT1

0 0 0 1

0 1 1 0

1 0 0 0

SOLVING A K-MAP WITH 4 INPUTS

EVEN PARITY: OUTPUT ASSURES EVEN 1 DIGITS

CONVERT TO K-MAP

EVEN PARITY: OUTPUT ASSURES EVEN 1 DIGITS

ANALYZE K-MAP

OPTIMIZED PARITY IMPLEMENTATIONOPTIMIZED: 6 GATES; ORIGINAL 8 GATES:

CONCLUSION

DEFINITIONS

Electricity: V = I R

Symbols: AND, OR, NOR, XOR, NAND, NOR

•Equation Form

•Gate Form

Components: Multiplexer, Decoder, Parity, Adder

DESIGNING LOGIC

1. Define Truth Table

2. Analyze Write Sum of

Products Use Karnaugh Map Optimize in other

ways

3. Develop Circuit