digital logic- computer architecture

CSC: 345 Computer Architecture

Jane Huang

Lecture 2

Digital Logic (Appendix A)

Today’s Overview

• Complete discussion on Instruction Cycle.

• Homework questions and discussion.

• Appendix A– Digital Logic

– Boolean Algebra

– Gates

– Combination Circuits

– Sequential Circuits

• Discuss Small group presentations

Digital Logic

Digital circuitry designed and analysed using Boolean algebra.

George Boole, English Mathematician, proposed basic principles of boolean algebra in his 1854 treatise on “An Investigation of the Laws of Thought on Which to Found the Mathematical Theories of Logic and Probabilities”

Boolean algebra is used for: Analysis: Describe the function of

digital circuitry. Design: To develop a simplified

implementation of a given functionality.

Boolean Algebra

Variables (True = 1, False = 0)

Operations: AND • , OR + , NOT ¯ .

A AND B = A • B (Also can be represented as AB)

A OR B = A + B

NOT A = A

We can represent these operations using truth tables:

In the absence of parentheses, AND takes precedence over OR.

P Q NOT P P AND Q P OR Q P XOR Q P NAND Q P NOR Q

0 0

0 1

1 0

1 1

1

1

0

0

0

0

0

1

0

1

1

1

0

1

1

0

1

1

1

0

1

0

0

0

Watch out for this distributive law:A + (B • C) = (A + B) • (A + C)

DeMorgan’s theorem will be very helpful to us!

Examples

Construct a truth table for ABC + AB

A B C ABC AB ABC + AB

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0

0

0

0

0

0

0

1

1

1

0

0

0

0

0

0

1

1

0

0

0

0

0

1

Gates

Logical functions are implemented by the interconnection of gates.

A gate is an electronic circuit that produces an output signal as a simple boolean operation on its input signals.

Gates include: AND OR NOT NAND NOR

X Y F

0 0 0

0 1 0

1 0 0

1 1 1

AND Gate

F = X YF = XY

AND Gate

Gates

X Y F

0 0 0

0 1 1

1 0 1

1 1 1

OR Gate

F = X+Y

X F

0 1

1 0NOT Gate

F = X

X Y F

0 0 1

0 1 1

1 0 1

1 1 0

X Y F

0 0 1

0 1 0

1 0 0

1 1 0

X Y F

0 0 0

0 1 1

1 0 1

1 1 0

NAND GateF = (XY)

NOR GateF = (X+Y)

XOR GateF = (XY)+(XY)

Functionally Complete Sets

Design and fabrication are simpler if only one or two types of gates are used.

We need to identify functionally complete sets of gates:

AND, OR, NOT(Obvious why this is complete!)

AND, NOTSynthesize OR from DeMorgan’s theorem.

OR, NOTSynthesize AND from DeMorgan’s theorem.

NAND

NOR Not so intuitive!! DeMorgan’s Theorem:

AB = A + B

Use of NAND gates to create a functional complete set of gates.

A A

A ABB AB

A

B

A

BA+B

Combinational Circuits

An interconnected set of gates.

Output at any time is a function of the input at that time.

Appearance of input followed almost immediately by appearance of output.

For any given function – there are a number of alternative circuits that can be used.

Example:

F = ABC + ABC + ABC

Sum of Products

A B C F

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1A CB

F

0

0

1

1

0

0

1

0

An Alternate Form:

F = ABC + ABC + ABC (Sum of Products)

An equivalent representation isgiven as:

F = (ABC) • (ABC) • (ABC) • (ABC) • (ABC) (ie none of the input combinations that produce 0 is true)

Apply DeMorgan’s theorem

(X • Y • Z) = X + Y + Z

Convert to Product of Sums

F = (A+B+C) • (A+B+C) • (A+B+C) • (A+B+C) • (A+B+C)

A B C F

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 0

1 0 1 0

1 1 0 1

1 1 1 0

An Alternate Form:

F = (A+B+C) • (A+B+C) • (A+B+C) • (A+B+C) • (A+B+C)

A

CB

A

CB

A

CB

A

CB

A

CB

F

Product of Sums

Algebraic Simplification

Need to reduce an algebraic expression to one with fewer elements.

Simpler (smaller, cheaper, faster) implementation

F = ABC + ABC + ABCis equivalent to:

F = AB + BC

or

F = B(A + C)A

C

B

F

Simplification Methods

Apply algebraic identities to simplify:

Try simplifying F = ABC + ABC + ABC

We need a simpler approach!!

Karnaugh Maps

Represents a boolean function of up to 6 variables.

Array of 2n squares representing the possible combinations of n binary variables.

Functions of 2 variables are represented respectively as:

Karnaugh maps borrowed from: http://www.maxmon.com/kmaps1.htm

Karnaugh Maps

Using Karnaugh Maps

00 01 11 10

00

01 1 1

11

10

CDAB

C

D

A

B

Any two adjacent squares differ in only one of the variables.

If two adjacent squares both have a ‘1’ in them – then the corresponding terms only differ in one variable.

The two terms can be merged by eliminating that variable.

In this example:F = ABCD + ABCD can be simplified to ABD

Duplication Rules

Adjacency rules can be extended in several ways:

Wrapping around the edge of the map is allowed. (ie top square is adjacent to bottom square, and LHS to RHS).

Instead of grouping just 2 squares – we can group 2n squares. (ie 2, 4, 8 etc)

Amongst the marked squares (ie with ‘1’s), circle the largest possible blocks (1,2,4,8)

Make sure that each marked square is in at least one block. (i.e some squares might appear in more than one circle if for examle there are three ‘1’s in a row).

00 01 11 10

00 1

01

11

10 1

CDAB

C

D

A

B

F = BCD

00 01 11 10

00

01 1 1

11

10

CDAB

C

D

A

B

F = ABD

00 01 11 10

00 1 1 1 1

01

11

10

CDAB

C

D

A

B

F = AB

00 01 11 10

00

01 1 1

11 1 1

10

CDAB

C

D

A

B

F = BC

00 01 11 10

00 1 1

01 1 1

11 1 1

10 1 1

CDAB

C

D

A

B

00 01 11 10

00 1 1

01

11

10 1 1

CDAB

C

D

A

B

00 01 11 10

00 1 1 1 1

01 1 1 1 1

11

10

CDAB

C

D

A

B

00 01 11 10

00 1 1

01 1 1

11 1 1

10 1 1

CDAB

C

D

A

B

00 01 11 10

00

01 1

11 1 1

10 1

CDAB

C

D

A

B

Overlapping Groups

Any group of 1s that is completely overlapped by other groups can be eliminated.

00 01 11 10

00 d

01 1

11 1 1

10 1

CDAB

C

D

A

B

In some cases, certain combinations of variables never occur, and therefore we just don’t care about whether they are set to 1 or 0.

These are marked as d on the K-Maps – and may be included or excluded from groupings.

Develop the boolean expressions for a circuit that adds 1 to a packed decimal digit.

In a packed decimal digit, each digit is represented by a 4-bit code.

For example: 8 1000729 0111 0010 1001

Method:

Develop a truth table showing inputs and outputs.

Plot the function onto a karnaugh map.

Simplify the karnaugh map.

Construct the circuit.

An Example

Num-ber

Input Num-ber

Output

A B C D W X Y Z

0 0 0 0 0 1 0 0 0 1

1 0 0 0 1 2 0 0 1 0

2 0 0 1 0 3 0 0 1 1

3 0 0 1 1 4 0 1 0 0

4 0 1 0 0 5 0 1 0 1

5 0 1 0 1 6 0 1 1 0

6 0 1 1 0 7 0 1 1 1

7 0 1 1 1 8 1 0 0 0

8 1 0 0 0 9 1 0 0 1

9 1 0 0 1 0 0 0 0 0

1 0 1 0 d d d d

1 0 1 1 d d d d

1 1 0 0 d d d d

1 1 0 1 d d d d

1 1 1 0 d d d d

1 1 1 1 d d d d

Don

’t C

are

00 01 11 10

00

01 1

11 d d d d

10 1 d d

CDAB

C

D

A

B

00 01 11 10

00

01

11 d d d d

10 d d

CDAB

C

D

A

B

00 01 11 10

00

01

11 d d d d

10 d d

CDAB

C

D

A

B

00 01 11 10

00

01

11 d d d d

10 d d

CDAB

C

D

A

B

W

dd10

dddd11

01

00

10110100CD

AB

C

D

A

B

W

Start with the first output variable

Mark the don’t cares.

dd110

dddd11

101

00

10110100CD

AB

C

D

A

B

W

Mark a ‘1’ in the correct square to represent 1’s in the output variable’s column from the truth table.

dd110

dddd11

101

00

10110100CD

AB

C

D

A

B

W

Create groupings.

W = AD + BCD

Work in groups to design a circuit capable of performing a right circular shift on the binary representation of numbers 0 to 7.

For example 5 = 0101.

If we circular shift the bits right one position then:

A Small Group Activity

0 1 0 1

0 1 0 1

1 0 1 0

Create a truth table for the input and output variables.

Create a karnaugh-map for each output variable.

Reduce the map.

Draw the circuit.

Connects multiple inputs to a single output.

At any one time – ONE of the inputs is selected and passed to the output.

Multiplexers

4-to-1MUX

D0

D1

D2

D3

S2 S1

F

S2 S1 F

0 0 D0

0 1 D1

1 0 D2

1 1 D3

Multiplexer ImplementationS2 S1 F

0 0 D0

0 1 D1

1 0 D2

1 1 D3

S2 S1

D0

D1

D2

D3

F

Used in digital circuits to control signal and data routing.

Loading of the PC in which the value may come from:

Binary counter

IR

Output of ALU

Multiplexer Input to Program Counter

4-to-1 MUX

S2

S1

C0 IR0 ALU0

PC0

4-to-1 MUX

S2

S1

C1 IR1 ALU1

PC2

A combinatorial circuit with a number of output lines.

Only one output line is asserted at any time.

The asserted output line is selected by the inputs.

A decoder has n inputs and 2n outputs.

DecodersA

B

C

000 D0

001 D1

010 D2

011 D3

100 D4

101 D5

110 D6

111 D7

Many uses – for example address decoding.

IK-byte memory using four 256 X 8-bit RAM chips

Single unified address space broken down as:0000-00FF Chip 0

0100-01FF Chip 1

0200-02FF Chip 2

0300-03FF Chip 4

Each chip requires 8 address lines supplied by lower 8 bits of the address. (Why 8 lines?)

The higher order 2 bits are used to select one of the four RAM chips.

A 2-to-4 decoder is used whose output enables one of the four chips.

Decoder Usage

256 X 8RAM

256 X 8RAM

256 X 8RAM

256 X 8RAM

2X4Decoder

A0

A7

A8

A9

Enable Enable Enable Enable

Address Decoding

Normally combinational circuits provide no memory or state information.

In a sequential circuit, the output depends on:Current input

Current state

• Simplest form of a sequential circuit is the flip-flop.S-R Latch

Clocked S-R Flip-Flop

D Flip-Flop

J-K Flip-Flop

A flip-flop is a bi-stable device – existing in one of two states (1 or 0). It only changes state if new input appears.

The flip-flop has two outputs usually labeled Q and Q. These are the complements of each other.

Sequential Circuits

S-R Latch

R

S

Q

Q

Bistable:

R=S=0, Q=0

R=S=0, Q=1

Therefore 1 bit memory with Q representing the value of the bit.

S and R write values ‘1’ and ‘0’ respectively.

Time delay occurs (asynchronous operation)R S Q

0 0 1

0 1 0

1 0 0

1 1 0

NOR GateF = (X+Y)

0

0

00

0

1

S-R LatchR

S

Q

Q

0

0

00

0

1

Characteristic Table

Current Inputs

Current State

Next State

SR Qn Qn+1

00 0 0

00 1 1

01 0 0

01 1 0

10 0 1

10 1 1

11 0 ---

11 1 ---

Simplified Characteristic Table

S R Qn+1

0 0 Qn

0 1 0

1 0 1

1 1 ---

R

S

Q

Q

Clocked S-R LatchIn a digital computer, events are often synchronized with a clock pulse:

The output can only be reset on the clock pulse.

Clock

D Flip-Flop

D

Q

Q

Clock

D Qn+1

0 0

1 1

D Flip-flop solves the problem of non-allowable inputs.

Implementing an 8-bit parallel register

Next week – Chapter 3 I/O Interconnection Structures

Please check the website for additional helpful readings.

Groups – sign-up for a small group before you leave tonight.

Homework is posted on the website.

Any additional questions?

Conclusions