development status of soi asic/fpga status of soi / mpu and asic development for space nov. 11th...
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Current status ofSOI / MPU and ASIC
development for space
Nov. 11th 2010
Electronic Devices and Materials GroupAerospace Research and Development Directorate, JAXA
Hiroyuki SHINDOUshindou.hiroyuki@jaxa.jp
The 23rd Microelectronics Workshop
1
Development history of MPU/ASIC
4k/10k G/A(2µm rule)
8/16bit MPU
100k G/A(1µm rule)32bit MPU (H32/V70)
1M G/A (0.35µm rule)64bit MPU(25MHz)
4M gateStandard cell(0.18µm rule)64bit MPU (200MHz)
>4M gateStandard cell (0.15µm-SOI)64bit MPU(>300MHz)
19801990
20002010
For <0.18µm technology, SEE*s are main concern for LSIs for space applications. FD-SOI** is attractive for space because of its SEE hardness as compared with bulk technology.
Year
JAXA has developed LSIs with the latest technology for commercial market.
The 23rd Microelectronics Workshop @ Tsukuba
*Single Event Effect**Fully depleted Silicon on insulator
2
Oki 0.15um FD-SOI Structure & Process
Gate length [µm] 0.15Gate oxide [nm] 2.5SOI thickness [nm] 40BOX thickness [nm] 145
Process parameters of 0.15µm FD-SOI
Up to 6 metal is availableLow Leakage (LL) Ioff < 2E-12 A/um
STI (Shallow Trench Isolation) is applied.Less floating body effect compared with PD
The 23rd Microelectronics Workshop @ Tsukuba
RHBD* techniques JAXA/HIREC developed is applied for space products.(MPU, ASIC, FPGA etc.) *Radiation Hardness By Design methodology.
3
The redundant transistor pairs completely prevent the SET* pulse generations on the output terminal.
This concept can be easily extended for any logic gates and circuits.
Basic concept of RHBD
A YRedundant Tr Pairs
RHBD Inverter
A Y
The 23rd Microelectronics Workshop @ Tsukuba
*SET: Single Event Transient
10-3
10-2
0.1
1.0
0 20 40 60 80LET [MeV/(mg/cm2)]
Erro
r X-S
ectio
n [µ
m2 /b
it]
対策なし(リファレンス)
対策あり(エラーなし、上限値)
10-3
10-2
0.1
1.0
10-3
10-2
0.1
1.0
0 20 40 60 800 20 40 60 80LET [MeV/(mg/cm2)]
Erro
r X-S
ectio
n [µ
m2 /b
it]
対策なし(リファレンス)
対策あり(エラーなし、上限値)Ar
Kr
XeRHBD Inverter
Conventional
5
Milestone (HR5000S)
The 22nd Microelectronics Workshop @ Tsukuba
JFY2010JFY2008 JFY2009
Qualification will be completed this month.
Synthesis & layout
Chip manufacturing
QT
Tape out
Assembly & evaluation1st Si
Nov. 2010
Minor design modification
Chip manufacturing & evaluation2nd Si
6The 23rd Microelectronics Workshop @ Tsukuba
JAXA qualified 64bit MPU (HR5000)
MPU coreMPU core(MIPS64 5kf)(MIPS64 5kf)
MPU coreMPU core(MIPS64 5kf)(MIPS64 5kf)
CPU BusCPU BusSlaveSlave
CPU BusCPU BusSlaveSlave
CPU BusCPU BusCPU BusCPU Bus
UARTUART InterruptInterruptControllerController
MemoryMemoryControllerController
DMADMA
TimerTimerPCI HostPCI HostBridgeBridge
UARTUARTUARTUART InterruptInterruptControllerControllerInterruptInterrupt
ControllerController
MemoryMemoryControllerControllerMemoryMemory
ControllerControllerDMADMADMADMA
TimerTimerTimerTimerPCI HostPCI HostBridgeBridge
PCI HostPCI HostBridgeBridge
PCI BusPCI BusPCI BusPCI Bus
64bit RISC (with FPU)64bit RISC (with FPU)200MHz (320MIPS)200MHz (320MIPS)32kB(Inst.)+32kB(data) cache32kB(Inst.)+32kB(data) cache
64bit RISC (with FPU)64bit RISC (with FPU)200MHz (320MIPS)200MHz (320MIPS)32kB(Inst.)+32kB(data) cache32kB(Inst.)+32kB(data) cache
MIPS64 5kf architecture with on-chip peripherals.
JAXA qualified. (Mar. 2007)
0.18µm commercial CMOS process.200MHz operation (320MIPS)
7
Key feature of SOI MPU (HR5000S)
304 pin QFP package.RHBD techniques is applied to both the logical circuit and the cache memory to improve SEU tolerance.
MIPS64 5kf architecture with on-chip peripherals.0.15µm FD-SOI CMOS process.50MHz operation*
*PLL circuit for space use is not applied. Now under development.
HR5000S (SOI version of HR5000 64bit MPU)
Logic : >64 [MeV/(mg/cm2)]Cache :>64 [MeV/(mg/cm2)]
The 23rd Microelectronics Workshop @ Tsukuba
8The 23rd Microelectronics Workshop @ Tsukuba
HR5000S circuit layout
D-Cache Data RAM
D-Cache Tag RAM
MPU Logic cells
I-Cache Tag RAM
I-Cache Data RAM
D/I CacheWay RAM
5mm
10mm
The chip size was adjusted to 5mm x 10mm though RHBD was applied to the cache memory.
9The 23rd Microelectronics Workshop @ Tsukuba
HR5000 vs HR5000S (Area & Power)
0.0
0.2
0.4
0.6
0.8
1.0
Area Power Consumption
HR5000HR5000S
I-Cache Data RAMI-Cache
Data RAM
I-Cache Tag RAMI-Cache Tag RAM
I CacheWay RAMI Cache
Way RAM
D CacheWay RAMD Cache
Way RAM
D-Cache Data RAMD-Cache Data RAM
D-Cache Tag RAMD-Cache Tag RAM
MPU Logiccells
MPU Logiccells
I-Cache Data RAMI-Cache
Data RAM
I-Cache Tag RAMI-Cache Tag RAM
I CacheWay RAMI Cache
Way RAM
D CacheWay RAMD Cache
Way RAM
D-Cache Data RAMD-Cache Data RAM
D-Cache Tag RAMD-Cache Tag RAM
MPU Logiccells
MPU Logiccells
1.00.72
1.00.39
Relative value comparison between HR5000 and HR5000S
HR50000.18um CMOS
1.8V / 3.3V
HR5000S0.15um FD-SOI
1.5V / 3.3V
@ 50MHz
10The 23rd Microelectronics Workshop @ Tsukuba
SEE test results
LET [MeV/(mg/cm2)]
TestProgram
Fluence[Particles/cm2]
# of Error(Cache)
# of Error(Logic)
# of SEL
0.6 Whetstone 1.11e+7 0 0 0
40.8Whetstone 1.05e+5 0 0 0Quick sort 1.16e+5 0 0 0
64.0Whetstone 1.14e+5 0 0 0Quick sort 1.06e+5 0 0 0
Heavy-Ion Irradiation* Test Results for MPU evaluation board
MPU evaluation board25 [MHz] operation
Test programs were continuously executed while doing the irradiation to monitor anomaly events (Cache / Logic).
*Test was performed at Japan Atomic Energy Agency (JAEA), Japan
11The 23rd Microelectronics Workshop @ Tsukuba
Predicted SEU rate on orbit
Logic (F/F) SRAM TotalLETth [MeV/(mg/cm2)] >64.0 >64.0Cross Section [cm2/bit] < 2.1E-11 < 3.0E-12# of cells used for HR5000S 35922 669696
Predicted SEU rate (Case 1 : 692 km, 98.16 deg. Sun-synchronous orbit)Solar Min. [SEUs/device/day] < 4.3E-15 < 2.7E-15 < 7.0E-15Solar Max. [SEUs/device/day] < 2.1E-15 < 1.4E-15 < 3.5E-15
Predicted SEU rate (Case 2 : 36,000 km, 0.0 deg. Geostationary orbit)Solar Min. [SEUs/device/day] < 2.0E-14 < 1.3E-14 < 3.3E-14Solar Max. [SEUs/device/day] < 1.0E-14 < 6.4E-15 < 7.4E-15
Predicted SEU rate in radiation environment of SSO and GEO(Calculated from the Irradiation test data for the cell library.)
Excellent SEU tolerance!
13The 23rd Microelectronics Workshop @ Tsukuba
RHBD 0.15µm SOI-ASIC Characteristics
Standard cells - Low power type (Normal Vth)- High Speed type (Low Vth)
42 type of RHBD sequential logic cells,293 type of combinational logic.I/Os Digital I/Os, PCI, LVDS
Supply voltage 1.5V Core / 3.3V IO
Stand-by power(2 input NAND)
42.3 pW (Low power type)537.8 pW (High speed type)
@ 25 degree C, 1.5V
Delay(2 input NAND)
46.1 psec (Low power type)36.9 psec (High speed type)
@ 25 degree C, 1.5V Fanout=1
Toggle frequency(D-F/F)
1.485 GHz (Low power type)2.207 GHz (High speed type)
@ 25 degree C, 1.5V Fanout=1
Usable gate 3,720 Kgate (@10x10 mm) Area utilization = 65%
SEU/TID >64 [MeV/(mg/cm2)], 1kGy(Si)
Qualification will be completed this month.Process Design Kit (PDK) has already been released.
14The 23rd Microelectronics Workshop @ Tsukuba
SOI ASIC design status for space
The evaluation of 7 kinds of ASIC designs is now in progress to achieve near future space missions.
Design phase : 3 designs
On-board evaluation : 2 designs ES chip evaluation : 2 designs
A YRedundant Tr Pairs
RHBD InverterRHBD Inverter(SET free)(SET free)
A YRedundant Tr PairsA YRedundant Tr Pairs
RHBD InverterRHBD Inverter(SET free)(SET free)
A YRedundant Tr Pairs
RHBD InverterRHBD Inverter(SET free)(SET free)
A YRedundant Tr PairsA YRedundant Tr Pairs
RHBD InverterRHBD Inverter(SET free)(SET free)
0.15um SOI + RHBD
15The 23rd Microelectronics Workshop @ Tsukuba
Summary
Development of MPU based on 0.15um FD-SOI technology is in progress.QT will be finished soon.
The evaluation of ASIC designs for space is now in progress.
SOI technology with RHBD technique will become one of the important technologies to make sure the space mission succeed.
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