design fsm, instruction set architecture

Design FSM,Instruction Set Architecture

Prof. Sin-Min Lee

State Machines• Construct a sequence detector: 001

Solution:

1) Formulate State Diagram:

BB DDCCAA0 0 1

0

0

1

1

1

2) Construct State Table:

Present State Next State

A

B

C

D

0 1 Z

B

B

B

C

A

A

A

D

0

0

0

1

Input (x) Output (PS)

Next State

A

B

C

D

Z

0

0

0

1

Input (x)Output (PS)

Present State

3) Construct Logic Table

Q1 Q0

0

0

0

1

1 1

1

1

1

11

1

0

0

0

0

X=0 X=1

Q1 Q0 Q1 Q0

0 0

0 0

0 0

01

4) Extract Logic Equations

A

B

C

D

Z

0

0

0

1

Input (x)Output (PS)

Q1 Q0

0

0

0

1

1 1

1

1

1

11

1

0

0

0

0

X=0 X=1

Q1 Q0 Q1 Q0

0 0

0 0

0 0

01

Present State Next State

Q 0 = X, Q1 = XQ1Q 0 + XQ1Q0,+

Z = Q1Q0+

5) Draw Logic Diagram

D Q0

Q0*

X*

clkQ0 = X

Q1 = XQ1Q 0 + XQ1Q0 D Q1

Q1

XQ1

Q0

And

XQ1Q0

And

Or

+

+

Continue…Continue…

Z = Q1Q0

Q1

Q0

And Z

6)Draw functional block diagram

001 Detect

Output Input

Clock

State Machines• Construct a soda machine which 1) take only quarters, and 2) deliver a soda when all three quarters are inserted

Solution:

1) Formulate State Diagram:

BB DDCCAA25C 25C 25C

25C

25C

Not 25C

Not 25C

Not 25C

2) Construct State Table:

Present State Next State

A

B

C

D

0 1 Z

A

A

A

A

B

C

B

D

0

0

0

1

Input (x) Output (PS)

Next State

A

B

C

D

Z

0

0

0

1

Input (x)Output (PS)

Present State

3) Construct Logic Table

Q1 Q0

0

0

0

0

0 0

0

0

1

11

1

0

0

0

0

X=0 X=1

Q1 Q0 Q1 Q0

0 1

1 1

0 1

01

4) Extract Logic Equations

A

B

C

D

Z

0

0

0

1

Input (x)Output (PS)

Q1 Q0

0

0

0

0

0 0

0

0

1

11

1

0

0

0

0

X=0 X=1

Q1 Q0 Q1 Q0

0 1

1 1

0 1

01

Present State Next State

Q 0 = XQ1 + XQ0 Q1 = XQ 0,+

Z = Q1Q0+

1

1

1

0

5) Draw Logic Diagram

D Q0

Q0*

X

clkQ 1 = XQ0

Q0 = XQ1 + XQ0 D Q0

Q0

XQ1 And

X

Q0And

Or

+

+ AndQ0

Continue…Continue…

Z = Q1Q0

Q1

Q0

And Z

6)Draw functional block diagram

Quarters Detect

Soda Money

Clock

Moore Machine Vs. Mealy Machine

Moore machine associates its output with the states. The outputs are represented either within the vertexcorresponding to a state or adjacent to the vertex.

Mealy machine associates its output with the transitions.Each arc of the input values shows the output valuesgenerated during the transition.

What is “Computer

Architecture”Computer Architecture is the design of the computer at the hardware/software interface.

Computer Architecture = Instruction Set Architecture + Machine Organization

Computer Architecture

Instruction Set Design Machine Organization

Computer Interface Hardware Components

Compiler/System View Logic Designer’s View

The Instruction Set: a Critical Interface

instruction set

software

hardware

ISA

The instruction set architecture, or ISA, is much like the car interface, but for microprocessors.

ISA includes the information needed to interact with the microprocessor, but not the details of how microprocessor itself is designed and implemented.

ISA is the set of all instructions that the microprocessor can execute.

Language Categories

1. High-level languages Platform-independent: the same code can be run on

computers with different microprocessors and OSs. C++, Java, Fortran

2. Assembly languages Specific to a microprocessor Directly manipulate the data stored in internal components

3. Machine languages Instructions are binary Programs are converted to machine language Each processor has its own machine language

Compiling and Assembling

High-level language programs are compiled.

Assembly language programs are assembled

Compiling

A program written in high-level language, a source code, is input to a compiler.

The compiler checks for syntax errors and generates an object code file, machine language equivalent of the source code.

A linker combines all object codes and stores it as an executable file. Some programs use the object code of other programs.

A loader copies the executable file into memory

Compilation Process

Assembling

Each assembly language instruction corresponds to one unique machine code instruction. Assembler are much

less complex than compilers

High-level and Assembly

Most software is written in high-level language. There are many support tools for high-level

languages. Assembly language is used in conjunction with

high-level languages to optimize code. The program is no longer platform-independent

Compilation for Java Applets

Assembly Language Instructions

Instruction types:1. Data transfer instructions

2. Data operation instructions

3. Program control instructions

Instruction Set Architecture Instruction set architecture is the attributes of a

computing system as seen by the assembly language programmer or compiler. This includes Instruction Set (what operations can be

performed?) Instruction Format (how are instructions specified?) Data storage (where is data located?) Addressing Modes (how is data accessed?) Exceptional Conditions (what happens if something

goes wrong?) A good understanding of computer architecture is

important for compiler writers, operating system designers, and general computer programmers.

What is ISA?

Aspects of the computer visible to the programmer:

Data Types Registers Instructions Addressing

Instruction Set Architecture as an ADT “…the attributes of a [computing] system as seen by the

programmer, i.e. the conceptual structure (state) and functional behavior (operations), as distinct from the organization of the data flow and controls, the logical design, and the physical implementation.”

- Amdahl, Blaauw, and Brooks, 1964

Registers + Memory

instructioninstruction instruction…..

instructioninstruction instruction…..

inst

ruct

ion

instruction

Instruction Set Architecture as an ADT

Before Register and Memory

add r1, r2, r3

2021

r3

128

r2

r1

r0

PC

63

242322

027

40

21

3

··2021

··

(add r1, r2, r3)

(lw r2, 1(r0))

(sw r3, 0(r0))

(beq r0, r1, 2)

(j 15)

After Register and Memory

Registers

Memory

212

20

r3

128

r2

r1

r0

PC

63

242322

027

40

21

3

··2021

··

(add r1, r2, r3)

(lw r2, 1(r0))

(sw r3, 0(r0))

(beq r0, r1, 2)

(j 15)Registers

Memory

Assumptions 8 bit ISA # of registers = 4 + PC (Program Counter) Memory size = 64B

Assumptions 8 bit ISA # of registers = 4 + PC (Program Counter) Memory size = 64B

Instruction Set Architecture as an ADT

Before Register and Memory

lw r2, 1(r0)

After Register and Memory

222

20

r3

78

r2

r1

r0

PC

63

242322

027

40

21

3

··2021

··

(add r1, r2, r3)

(lw r2, 1(r0))

(sw r3, 0(r0))

(beq r0, r1, 2)

(j 15)Registers

Memory

212

20

r3

128

r2

r1

r0

PC

63

242322

027

40

21

3

··2021

··

(add r1, r2, r3)

(lw r2, 1(r0))

(sw r3, 0(r0))

(beq r0, r1, 2)

(j 15)Registers

Memory

Assumptions 8 bit ISA # of registers = 4 + PC (Program Counter) Memory size = 64B

Assumptions 8 bit ISA # of registers = 4 + PC (Program Counter) Memory size = 64B

Instruction Set Architecture as an ADT

Before Register and Memory

sw r3, 0(r0)

After Register and Memory

232

20

r3

78

r2

r1

r0

PC

63

242322

087

40

21

3

··2021

··

(add r1, r2, r3)

(lw r2, 1(r0))

(sw r3, 0(r0))

(beq r0, r1, 2)

(j 15)Registers

Memory

222

20

r3

78

r2

r1

r0

PC

63

242322

027

40

21

3

··2021

··

(add r1, r2, r3)

(lw r2, 1(r0))

(sw r3, 0(r0))

(beq r0, r1, 2)

(j 15)Registers

Memory

Assumptions 8 bit ISA # of registers = 4 + PC (Program Counter) Memory size = 64B

Assumptions 8 bit ISA # of registers = 4 + PC (Program Counter) Memory size = 64B

Instruction Set Architecture as an ADT

Before Register and Memory

beq r0, r1, 2

After Register and Memory

242

20

r3

78

r2

r1

r0

PC

63

242322

087

40

21

3

··2021

··

(add r1, r2, r3)

(lw r2, 1(r0))

(sw r3, 0(r0))

(beq r0, r1, 2)

(j 15)Registers

Memory

232

20

r3

78

r2

r1

r0

PC

63

242322

087

40

21

3

··2021

··

(add r1, r2, r3)

(lw r2, 1(r0))

(sw r3, 0(r0))

(beq r0, r1, 2)

(j 15)Registers

Memory

Assumptions 8 bit ISA # of registers = 4 + PC (Program Counter) Memory size = 64B

Assumptions 8 bit ISA # of registers = 4 + PC (Program Counter) Memory size = 64B

Instruction Set Architecture as an ADT

Before Register and Memory

j 15

After Register and Memory

150

20

r3

78

r2

r1

r0

PC

63

242322

087

40

21

3

··2021

··

(add r1, r2, r3)

(lw r2, 1(r0))

(sw r3, 0(r0))

(beq r0, r1, 2)

(j 15)Registers

Memory

240

20

r3

78

r2

r1

r0

PC

63

242322

087

40

21

3

··2021

··

(add r1, r2, r3)

(lw r2, 1(r0))

(sw r3, 0(r0))

(beq r0, r1, 2)

(j 15)Registers

Memory

Assumptions 8 bit ISA # of registers = 4 + PC (Program Counter) Memory size = 64B

Assumptions 8 bit ISA # of registers = 4 + PC (Program Counter) Memory size = 64B

Data Types

Unsigned Integers Signed Integers Characters Floating-point Numbers

Unsigned Integers

Stores the integer in standard binary format

00101011 = 1 + 2 + 8 + 32 = 43

Signed Integers

Stores the integer in two’s complement format to denote sign

Steps to convert signed integer to base 10: Store leading bit, 1 = negative, 0 = positive Invert all bits Add 1

Characters

Represented by integer values

Many different character encodings exist: ASCII UNICODE UTF-8 UTF-16

Floating-point Numbers

Four components in a floating-point number: Sign Mantissa Radix Exponent

Registers

Registers provide a variety of services: Instruction Counter Register-to-Register Operations Memory-to-Register Operations Memory-to-Memory Operations Processor Status

Instruction Counter Register

All von Neumann machines have an instruction counter which is a register

Register-to-Register Registers

Operate on one register using another register (ADD)

Supported by all ISA’s

Memory-to-Register Registers

Operate on memory using a register (LOAD, STORE)

Not supported by all ISA’s

Memory-to-Memory Registers

Operate on one memory location using another memory location (STRCMP)

Not supported by all ISA’s

Processor Status Registers

A collection of registers that indicate the current state of the processor (Carry, Interrupt, Zero)

Different ISA’s use different status registers

Instructions

Categories of instructions: Operate Memory Access Control Miscellaneous

Operate Instructions

Typical operations include: Arithmetic (ADD, SUB, MUL, DIV) Logical (AND, OR, NOT, XOR) Shift (ROL, ROR) Character (STRCMP) Stack (PUSH, POP)

Memory Access Instructions

Typical operations include: Load (LODSB) Store (STOSB)

Control Instructions

Conditional Branch (JZ, JC, JO, JS) Unconditional Branch (JMP)

Miscellaneous Instructions

Input/Output (IN, OUT) Interrupts (CLI, INT, IRET) Halt Privileged

Addressing

Register Addressing Memory Addressing

Register Addressing

When an operand is taken from a register it is called register addressing

Memory Addressing

Logical Address Space (sequential memory locations)

Physical Address Space (many types exists: absolute addressing, indirect addressing, etc.)

ISA Examples

MIPS Motorola 6800 ARM SPARC PowerPC x86 IA-64

What is an ISA (Instruction Set Architecture)? Machine language instructions Registers Data representation (endianess, word size) Addressing methods Privilege modes ISA is not: CPU speed, cache size, pipelines,

etc.

Instruction Set Architecture

Organisation of storage: registers, memory Representations of data Instruction set Instruction formats Modes of addressing and accessing data Exceptional conditions

Instruction Set Architecture

Advantage: enables different implementations of the same architecture

Disadvantage: may prevent using new innovations

Machine Organisation

Implementation, capabilities and performance characteristics of functional units

Interconnections of these units Information flows between these units Control of information flow

Block Diagram of a Computer

Input

Unit

Output

Unit

Memory

CPU

ALU

Control

Unit

Register

Unit

So, let’s look at several ISA’s

Example ISAs (Instruction Set Architectures)IBM 360 (v1,v…) 1964 - ?

Digital PDP-11 (v1,v3) 1973-78 Vax-11 1978-92

Digital PRISM (v1) 1989-92

Digital Alpha (v1, v3) 1992-97

Sun Sparc (v8, v9) 1987-95

SGI MIPS (MIPS I, II, III, IV, V) 1986-96Intel (8086,80286,80386, 1978-00

80486,Pentium, MMX, ...)Itanium/I64 2002-

Defines the Mainframe Generation

Defines the MinicomputerGeneration

Defines the PC Generation

Evolution of Instruction SetsSingle Accumulator (EDSAC 1950)

Accumulator + Index Registers(Manchester Mark I, IBM 700 series 1953)

Separation of Programming Model from Implementation

High-level Language Based Concept of a Family(B5000 1963) (IBM 360 1964)

General Purpose Register Machines

Complex Instruction Sets Load/Store Architecture

RISC

(PDP-11, Vax, Intel 432 1977-80) (CDC 6600, Cray 1 1963-76), FP-11

(Mips,Sparc,HP-PA,IBM RS6000, . . .1987)

Instruction Set Architecture:What Must be Specified?

Instruction

Fetch

Instruction

Decode

Operand

Fetch

Execute

Result

Store

Next

Instruction

Instruction Format or EncodingHow is it decoded?

Location of operands and resultWhere other than memory?How many explicit operands?How are memory operands located?Which can or cannot be in memory?

Data type and Size – 16, 32, 64- bit, …Operations

What are supportedSuccessor instruction

Jumps, conditions, branchesFetch-decode-execute is implicit! –

Von Neumann

Two well known ISA’s in further detail

MIPS R3000 Instruction Set Architecture (Summary) – Supposedly a True RISC Instruction Categories

Load/Store Computational Jump and Branch Floating Point

coprocessor

Memory Management Special

R0 - R31

PCHI

LO

OP

OP

OP

rs rt rd sa funct

rs rt immediate

jump target

3 Instruction Formats: all 32 bits wide

Registers

Q: How many already familiar with MIPS or ALPHA ISA?

A "Typical" RISC – 32 bit

32-bit fixed format instruction (3 formats)32 32-bit GPR (R0 contains zero, DP

take pair of Registers)3-address, reg-reg arithmetic instructionSingle address mode for load/store:

base + displacementno indirection

Simple branch conditionsDelayed branch -

ALPHA AXP Instruction Set Architecture (Summary) – 1st True 64 bit Arch True 64-bit (RA’s are 64 bit, VA is 64-bit) Instruction Categories

Load/Store Computational Jump and Branch Floating Point – both VAX-11, IEEE Memory Management & MP lock Special, e.g. Vax-11 modes

R0 - R31

PCLPAR

LFR

OP

OP

OP

RA RB function RC

RA Displacement

number

4 Instruction Formats: all 32 bits wide

Registers

Palcode Instr

Branch Instr

OP RA RB Displacement Load/Store

045151620212532

064

Operate Intr

Lock Flag Reg

Lock Phy Adr Reg

ALPHA AXP Load/Store architecture (means separate memory references from execution

stream) E.g., PDP-11 and Vax-11’s you have ADD RA, Mem instructions

True 64-bit architecture 32 64-bit integer and 32 64-bit Floating Point registers – all operations

are done on 64-bit Memory is addressed via 64-bit little-endian byte addresses Four floating point data types supported

VAX F_floating (32 bit) VAX G_floating, VAX D_floating (64 bit) IEEE single (32 bit) IEEE double (64 bit)3-address, reg-reg arithmetic instruction

Single address mode for load/store: base + displacement

no indirection Simple branch conditions Instruction Set can be subset (e.g., no Floating Point)