dead time elimination for voltage source inverter

NEHA KARDAMM.TECH (PPS)

11 /PPS/010

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Dead-Time Elimination For Voltage Inverter

Introduction

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To avoid shoot-though in voltage source inverters (VSI),dead-time is introduced. However, it can cause problems such as output waveform distortion and fundamental voltage loss in VSI’s, especially when the output voltage is low.

This method is based on decomposing of a generic phase-leg into two basic switching cells, which are configured with a controllable switch in series with an uncontrollable diode. Therefore, dead-time is not needed.

Dead-Time Effect3

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Decomposing of a generic phase lag into equivalent switch cells

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Detection of load current direction depends on anti parallel diode conduction

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Diode conduction detector (DCD)7

Control scheme8

Proposed switch control flowchart9

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H-bridge voltage source inverter

Load = 8mH, 2.4 Ω

Vdc= 250 V

Switching frequency = 10 kHz

Fundamental frequency = 60 Hz

Simulated output current waveform

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Experimental circuit block diagram

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Experimental waveform of the proposed dead time elimination method

Modulation index = 0.2

A0 to A3 = DCD circuit output

A4 to A7 = gate drive signals

Output current = 8.5 A

Total harmonic distortion (THD) = 1.3 %

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Experimental waveform with 2μs dead-time effect

Total harmonic distortion (THD) = 6.02 %

Modified switch control flowchart to overcome zero current issue

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Experimental waveform when the load current cross zero

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Conclusion 17Reduces the output distortion and regains the

output RMS value.Minimizes switching loss since switches are

only active for half of each fundamental cycle.simple circuit and low cost.simple control logic and flexible

implementation.

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References

L. Ben Brahim, “On the compensation of dead time and zero-current

crossing for a PWM-inverter-controlled AC servo drive,” IEEE Trans.

Ind. Electron., vol. 51, no. 5, pp. 1113–1118, Oct. 2004.

A. Cichowski and J. Nieznanski, “Self-tuning dead-time compensation

method for voltage-source inverters,” IEEE Power Electron. Lett., vol.

3, no. 2, pp. 72–75, Jun. 2005.

Y. Lai and F. Shyu, “Optimal common-mode Voltage reduction PWM

technique for inverter control with consideration of the dead-time effects-

part I: basic development,” IEEE Trans. Ind. Appl., vol. 40, no. 6,pp. 1605–1612, Nov.–Dec. 2004.

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Thank you