data sheet mb86r24 mb86r26 - socionext.com · mb86r24 mb86r26 rev1.00 | december 21, 2018 socionext...
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Data Sheet
MB86R24MB86R26
Rev1.00 | December 21, 2018Socionext Europe GmbH
Graphic Competence Center – GCC
mb86r24-Ballassign.xlsx
mb86r24-Pinlist+PinmuxConfigurator.xlsxmb86r26-Ballassign.xlsxmb86r26-Pinlist+PinmuxConfigurator.xlsx
Socionext Europe GmbH MB86R24/MB86R26Graphic Competence Center - GCC Data Sheetds-mb86r24/26-rev1.00 GCC-0299-Ehttps://www.eu.socionext.com/ Copyright 2018
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Socionext Europe GmbH ii MB86R24/MB86R26Graphic Competence Center - GCC Data Sheetds-mb86r24/26-rev1.00 Prefacehttps://www.eu.socionext.com/ Rev1.00 | December 21, 2018
Preface
Intention and Target Audience of this Document
This document describes and gives you detailed insight to the stated Socionext Europe GmbH product.The MB86R24/26 devices belong to the Blueline SoC Family used for graphics applications.
The target audience of this document are engineers developing products that use the MB86R24/26 devices. Itdescribes the function and operation of the device. Please read this document carefully.
Trademarks
ARM is a registered trademark of ARM Limited in UK, USA and Taiwan. ARM is a trademark of ARM Limited in Japan and Korea. ARM Powered logo is a registered trademark of ARM Limited in Japan, UK, USA, and Taiwan.
ARM Powered logo is a trademark of ARM Limited in Korea. OpenGL ES is a registered trademark of the Khronos Group
System names and product names which appear in this document are the trademarks of the respective companyor organization.
Licenses
Under the conditions of Philips corporation I2C patent, the license is valid where the device is used in an I2Csystem which conforms to the I2C standard specification by Philips Corporation.The purchase of Socionext I2C components conveys a license under the Philips I2C Patent Rights to use thesecomponents in an I2C system, provided that the system conforms to the I2C Standard Specification as defined byPhilips.
Please acquire license of MediaLB from SMSC and request the following document: OS62420 MediaLB DeviceInterface Macro Advanced Product Data Sheet.
Important Note
A 3D graphics core unit previously used in many SoCs and chips originally designed and marketed by FujitsuSemiconductors is now used in Socionext's designs. The units original name was 'Iris'. The same unit is nowimplemented in Socionext designs under a new name: 'SEERIS'. The name 'Iris' is currently being replaced inHardware Manuals that are being released. For technical reasons, the name has NOT been changed in theRegister Descriptions!Please therefore be aware that Iris and SEERIS refer to the same functional unit used in the chip's design!
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Socionext Europe GmbH iii MB86R24/MB86R26Graphic Competence Center - GCC Data Sheetds-mb86r24/26-rev1.00 Historyhttps://www.eu.socionext.com/ Rev1.00 | December 21, 2018
History
Revision Date Author Description1.00 12.13.2018 ML Release up to date with HM Rev1.63
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Table of Contents
1. General Information ........................................................................................................................ 1-11.1. Overview ................................................................................................................................... 1-11.2. Key Features ............................................................................................................................. 1-11.3. Block Diagram ........................................................................................................................... 1-41.4. MB86R24 Package Dimensions ............................................................................................... 1-51.5. MB86R26 Package Dimensions ............................................................................................... 1-61.6. Ball Assignment ........................................................................................................................ 1-71.7. Pin Functions and Description .................................................................................................. 1-71.8. Pin Multiplexing ......................................................................................................................... 1-7
1.8.1. Pin Multiplex Limitations ................................................................................................... 1-71.9. Pin Power Supply ...................................................................................................................... 1-8
2. Electrical Characteristics ............................................................................................................... 2-12.1. Maximum Ratings ..................................................................................................................... 2-1
2.1.1. Maximum Ratings of USB PHY ........................................................................................ 2-22.1.2. Maximum Rating of Flat Panel Display (FPD) .................................................................. 2-22.1.3. Maximum Rating of MIPI .................................................................................................. 2-2
2.2. Temperature Conditions ........................................................................................................... 2-32.3. Thermal Design ......................................................................................................................... 2-32.4. Recommended Operating Conditions ....................................................................................... 2-32.5. Power ON ................................................................................................................................ 2-6
2.5.1. Recommended Power ON/OFF Sequence ...................................................................... 2-62.5.2. Power ON Timing Chart .................................................................................................... 2-7
2.6. DC Characteristics .................................................................................................................... 2-82.6.1. 3.3V Standard CMOS I/O ................................................................................................. 2-8
2.6.1.1. 3.3V Standard CMOS I/O V-I Characteristic (Driving Capability 2mA)...................... 2-92.6.1.2. 3.3V Standard CMOS I/O V-I Characteristic (Driving Capability 4mA).................... 2-102.6.1.3. 3.3V Standard CMOS I/O V-I Characteristic (Driving Capability 6mA).................... 2-112.6.1.4. 3.3V Standard CMOS I/O V-I Characteristic (Driving Capability 8mA).................... 2-12
2.6.2. SSTL15 I/O ..................................................................................................................... 2-132.6.3. SSCG I/O ........................................................................................................................ 2-18
2.6.3.1. PLL Clock Jitter ....................................................................................................... 2-192.6.3.2. Difference Permission Level of the Crystal.............................................................. 2-19
2.6.4. I2C Bus Fast Mode I/O ................................................................................................... 2-202.6.4.1. I2C IO V-I Characteristic Chart ................................................................................ 2-21
2.6.5. USB I/O ........................................................................................................................... 2-222.6.6. FPD I/O ........................................................................................................................... 2-232.6.7. MIPI D-PHY I/O .............................................................................................................. 2-242.6.8. ADC I/O .......................................................................................................................... 2-25
2.7. AC-Characteristics .................................................................................................................. 2-272.7.1. External Bus Controller Signal Timing ............................................................................ 2-272.7.2. DDR Controller Signal Timing ......................................................................................... 2-302.7.3. Display Controller Unit Signal Timing ............................................................................. 2-41
2.7.3.1. Clock........................................................................................................................ 2-412.7.3.2. Input Signal.............................................................................................................. 2-412.7.3.3. Output Signal........................................................................................................... 2-422.7.3.4. TCON Active Display Timing DISP1 Interface ........................................................ 2-44
2.7.4. FPD Unit Signal Timing .................................................................................................. 2-462.7.4.1. Output Signal........................................................................................................... 2-46
2.7.5. Video Capture Signal Timing .......................................................................................... 2-472.7.5.1. Clock........................................................................................................................ 2-472.7.5.2. Input Signal.............................................................................................................. 2-48
2.7.6. MIPI D-PHY Signal Timing ............................................................................................. 2-502.7.7. I2S Signal Timing ............................................................................................................ 2-53
Socionext Europe GmbH iv MB86R24/MB86R26Graphic Competence Center - GCC Data Sheetds-mb86r24/26-rev1.00 Table of Contentshttps://www.eu.socionext.com/ Rev1.00 | December 21, 2018
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Table of Contents
2.7.8. UART Signal Timing ....................................................................................................... 2-562.7.9. I2C Bus Timing ............................................................................................................... 2-572.7.10. SFI Signal Timing ......................................................................................................... 2-592.7.11. CAN Signal Timing ....................................................................................................... 2-602.7.12. USB Signal Timing ........................................................................................................ 2-612.7.13. USART Signal Timing .................................................................................................. 2-632.7.14. Ethernet Signal Timing ................................................................................................ 2-65
2.7.14.1. GMII Timing ........................................................................................................... 2-652.7.14.2. MII Timing.............................................................................................................. 2-662.7.14.3. RMII Timing ........................................................................................................... 2-672.7.14.4. MDIO Timing ......................................................................................................... 2-68
2.7.15. HS_SPI Signal Timing .................................................................................................. 2-692.7.16. Host Interface ............................................................................................................... 2-702.7.17. SDIO Signal Timing ...................................................................................................... 2-71
Socionext Europe GmbH v MB86R24/MB86R26Graphic Competence Center - GCC Data Sheetds-mb86r24/26-rev1.00 Table of Contentshttps://www.eu.socionext.com/ Rev1.00 | December 21, 2018
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1. General Information
Note: The content of this document is subject to changes without prior warning. Please review theHistory page for significant changes to the last version.
1.1. Overview
‘Blueline’ is the name of Socionext’s third generation of the application processor family which succeeds the‘Emerald’ product family. The term ‘Blueline’ is a preliminary working name for multiple System-on-Chip (SoC)application processor variants. The MB86R24/26 are the new devices in the family.The MB86R24/26 devices are high-end application processors that combine the latest ARM® Cortex™ A9 dualCPU core with state-of-the-art, embedded 2D and 3D graphics cores. SEERIS-MDP, the advanced 2D GraphicsEngine was designed in-house and is also used in other Socionext devices. Achieving outstanding rendering performance thanks to independent 2D and 3D graphics engines, the MB86R24/26 devices will be positioned as an embedded graphics performance industry leaders for automotive and industrialapplications. The SoCs also combine multiple video inputs and support three parallel display outputs.Furthermore, the chips provide various standard and automotive-specific peripheral interfaces for a wide range ofapplications.
The chip architecture has been optimized for the simultaneous use of all functional blocks, virtually eliminatingperformance gaps. The MB86R24/26 devices’ harmonized structure permits the simultaneous rendering ofindependent 2D and 3D graphics, capturing of multiple video streams and display of content to multiple targets.
1.2. Key Features
Key features and interfaces of MB86R24 and MB86R26 are listed below.
TechnologyCMOS 55 nmPower supply voltage:IO: 3.3±0.3 V Core: 1.2±0.1 V DDR3: 1.5±0.075VDDR3L: 1.35+0.1V / 1.35-0.067VFPD: 1.8±0.15V
PackageMB86R24 Package: FCBGA-67627mm x 27mm, 1.0 Pitch
MB86R26 Package: BGA783 23mm x 23mm, 0.08 Pitch
Memory External SDRAM InterfaceUnified 16/32/64(2x32)-bit DDR3/3L memory interface
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DDR3/3L: 800/1066Mbit/s
External Bus Interfacefor NOR and NAND (serial Flash) Flash
SDIO InterfaceManaged NAND (eMMC)
Internal SRAM1x 32k, 1x64k built-in SRAM
SoC Technical DetailsCentral processor cores ARM Cortex A9, dual core 533 MHz per core 2.5 DMIPS/MHz32 kB instruction cache / 32 kB data cache, 512 kB L2-cacheARM NEON™ SIMD EngineJTAG ICE interfaceJava acceleration (Jazelle technology)VFP instruction set (VFPv3)
Multi-layer AXI/AHB bus architectureExternal Bus (16 bit)Graphics cores2D Graphics Engine: ‘SEERIS-MDP’3D Graphics Engine: PowerVR™, SGX543-MP1Tile-based deferred rendering (TBDR)OpenGL® ES 2.0
Display controller3 independent parallel display controllersDisplay layers per controller: 8 + 4 alpha + cursor (Display0, Display1), up to 3 display layers
(Display2)Gamma correction unit (color LUT)Dithering unit Display resolution up to WUXGAOutput formats/channels: Up to 2x single channel DRGB8881x single and dual channel FPD
Support for dual-view display Warping on the fly (Display2)
Video capture6 independent channelsSPI slave (Host interface) – 1 channelITU-R BT.656, SMPTE 293M-2003, SMPTE 296M-2001, SMPTE 274M-2005YCbCr 4:2:2 interlaced, YCbCr 4:2:2 progressiveRGB888 – 1 channelColor conversionHistogram unit, Histogram Equalization
Socionext Europe GmbH 1 - 2 MB86R24/MB86R26Graphic Competence Center - GCC Data Sheetds-mb86r24/26-rev1.00 General Informationhttps://www.eu.socionext.com/ Rev1.00 | December 21, 2018
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Peripherals and moreADC - 1 x support (12bit 1MS/s, 4 input ports)MIPI CSI2SPI master (SFI) – 2 channelsHigh-speed (quad) SPI - 1 channelEthernet MAC10/100/1000 MbpsIEEE 1588 support
USB 2.0 host or function – 1 channelSDIO/MMC – 1 channelUART – 6 channelsUSART – 6 channelsI2S – 3 portsI2C – 2 channelsPWM – 8 channelsGPIOTimer 16/32 bit - 2 channelsSignature Unit (signature and checksum calculation for display content, intended use: ASIL)Watchdog TimerExternal Interrupt – 4 channelsDMAC – 16 channelsPower Managing Unit
DebugJTAG16bit TRACE port
Automotive InterfacesCAN (I/O voltage: 3.3 V) - 2 channelsMediaLB(R) 3-pin support
Software SupportLinux Board Support Package (BSP) includingKernel 3.x (incl. dual core support)U-Boot (boot loader)Peripherals driversTool Chain
Graphics Software Stack providing APIs for Multiple Capture and Display Units3D Graphics:OpenGL® ES 2.0EGL 1.4, OpenGL® ES Shading Language 1.02D Pixel Graphics: SEERIS-MDP functionality (incl. warping-on-the-fly)
ToolingSocionext Developer Suite for setup, debugging and application support
Socionext Europe GmbH 1 - 3 MB86R24/MB86R26Graphic Competence Center - GCC Data Sheetds-mb86r24/26-rev1.00 General Informationhttps://www.eu.socionext.com/ Rev1.00 | December 21, 2018
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CGI Studio (2D & 3D)
1.3. Block Diagram
Figure 1.1. : MB86R2x Series Block Diagram
Memory
SRAM32k/64k
16ch DMANAND/Nor
ARM® Neon SMID
Main Processor
ARM® Cortex-A9ARMv7
ARM® Cortex-A9ARMv7
D-Cache32kB
2D and Video Processing
ADC 12bit
Connectivity
SDIO/MMC
HS-SPISPI Master
USB 2.0
UARTUSART
MediaLB
Watchdog
System
Timer
MB86R2x Series
PowerVR SGX 543 Shading Engine
OpenGL ES 1.x/2.0
3D Graphics Processor
ARM® Neon SMID
I-Cache32kB
L2-Cache512kB
I-Cache32kB
D-Cache32kB
DDR3/3L 800/106616/32/64-bit
I2CI2S
PWMGPIO
CAN ETH
JTAGTrace port
Command Sequencer
PowerMgmt.
Security
SignatureUnit
Co-ProcessorTilling, Pixel,
Texturing
Capture Engine SEERIS® 2D Engine Display EngineMIPI-CSI2, DRGB888,
ITU-R BT.656SMPTE, YCbCr, Histogram
Capture
Capture
Fill, Copy, Blend, Rop2/3, Scale,
Rotate, FIR
1920x1080, 24Bit, up to 8 layers, Dithering, DualView, TCON
DRGB888,FPD-Link (LVDS)
Capture
Capture
Capture
Capture
Pixel Engine
1920x1080, 24Bit,up to 8 layers, Warping,
Dithering, DualView
Display Engine
DRGB888DRGB888
Socionext Europe GmbH 1 - 4 MB86R24/MB86R26Graphic Competence Center - GCC Data Sheetds-mb86r24/26-rev1.00 General Informationhttps://www.eu.socionext.com/ Rev1.00 | December 21, 2018
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Socionext Europe GmbH 1 - 5 MB86R24/MB86R26Graphic Competence Center - GCC Data Sheetds-mb86r24/26-rev1.00https://www.eu.socionext.com/ Rev1.00 | December 21, 2018
1.4. MB86R24 Package Dimensions
Figure 1.2. : FCBGA-676P-M18 Package
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Socionext Europe GmbH 1 - 6 MB86R24/MB86R26Graphic Competence Center - GCC Data Sheetds-mb86r24/26-rev1.00https://www.eu.socionext.com/ Rev1.00 | December 21, 2018
1.5. MB86R26 Package Dimensions
Figure 1.3. : BGA-783-C-01 Package
Dimensions in millimeters
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1.6. Ball Assignment
For each device, a detailed graphic showing the ball assignment is attached to this document.Refer to file mb86r24-Ballassign.xlsx / mb86r26-ballAssign.xlsx.
1.7. Pin Functions and Description
An extended table containing more information about pinning and pinmux, is attached to this document.
Refer to file mb86r24-Pinlist+PinmuxConfigurator.xlsx / mb86r26-Pinlist+PinmuxConfigurator.xlsx.
1.8. Pin Multiplexing
Note: As there are some limitations in the use of the pin multiplex functionality, please refer to Table 1.1 forprohibited settings.
1.8.1. Pin Multiplex Limitations
Please refer to Table 1.1 for prohibited settings. Included in the attached files mb86r24/26-Pinlist+PinmuxConfigurator.xlsx, the Pinmux Configuration Tool can beused to check whether specific combinations of pinmux group and mode are allowed.
Table 1.1. : Pin multiplex prohibited settingsSetting (Pinmux Group, Mode) Prohibited (Pinmux Group, Mode) Module
(A,1) (E,1), (J,1), (K,1) HS_SPI
(A,2) (J, 0),(G,4) USART1
(E,0) (G,4) USART0
(E,1)(A,1)
(J,0),(J,2),(J,3),(J,4),(J,5)(K,0),(K,2),(K,3),(K,4),(K,5)
HS_SPI
(E,2)(J,0),(J,1),(J,3),(J,4),(J,5)
(K,0),(K,1),(K,3),(K,4),(K,5)(L,0),(L,1),(L,3),(L,4),(L,5)
PTM
(E,3)
(J,0),(J,1),(J,2),(J,4),(J,5)(K,0),(K,1),(K,2),(K,4),(K,5)(L,0),(L,1),(L,2),(L,4),(L,5)
(F,0),(F,4),(F,6)
SDIO
(F,0) (E,3),(J,3),(K,3),(L,3) SDIO
(F,4) (E,3),(J,3),(K,3),(L,3) SDIO
(F,6) (E,3),(J,3),(K,3),(L,3) SDIO
(G,4)
(E,0) USART0
(A,2), (J,0) USART1
(K,0) USART2
(J,0) (A,2),(G,4) USART1
Socionext Europe GmbH 1 - 7 MB86R24/MB86R26Graphic Competence Center - GCC Data Sheetds-mb86r24/26-rev1.00 General Informationhttps://www.eu.socionext.com/ Rev1.00 | December 21, 2018
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1.9. Pin Power Supply
(J,1)(A,1)
(E,0),(E,2),(E,3),(E,4),(E,5)(K,0),(K,2),(K,3),(K,4),(K,5)
HS_SPI
(J,2)(E,0),(E,1),(E,3),(E,4),(E,5)(K,0),(K,1),(K,3),(K,4),(K,5)(L,0),(L,1),(L,3),(L,4),(L,5)
PTM
(J,3)
(E,0),(E,1),(E,2),(E,4),(E,5)(K,0),(K,1),(K,2),(K,4),(K,5)(L,0),(L,1),(L,2),(L,4),(L,5)
(F,0),(F,4),(F,6)
SDIO
(K,0) (G,4) USART2
(K,1)(A,1)
(E,0),(E,2),(E,3),(E,4),(E,5)(J,0),(J,2),(J,3),(J,4),(J,5)
HS_SPI
(K,2)(E,0),(E,1),(E,3),(E,4),(E,5)(J,0),(J,1),(J,3),(J,4),(J,5)(L,0),(L,1),(L,3),(L,4),(L,5)
PTM
(K,3)
(E,0),(E,1),(E,2),(E,4),(E,5)(J,0),(J,1),(J,2),(J,4),(J,5)(L,0),(L,1),(L,2),(L,4),(L,5)
(F,0),(F,4),(F,6)
SDIO
(L,2)(E,0),(E,1),(E,3),(E,4),(E,5)(J,0),(J,1),(J,3),(J,4),(J,5)
(K,0),(K,1),(K,3),(K,4),(K,5)PTM
(L,3)
(E,0),(E,1),(E,2),(E,4),(E,5)(J,0),(J,1),(J,2),(J,4),(J,5)
(K,0),(K,1),(K,2),(K,4),(K,5)(F,0),(F,4),(F,6)
SDIO
Table 1.2. : Power supply(Global)External Pin Name Module Description Input Voltage
VSS General Ground 0V
VDDE General IO Power 3.3V
VDD General Internal Power 1.2V
SSCG0VDD CRG(PLL0) PLL Power 0 1.2V
SSCG0VSS CRG(PLL0) PLL Ground 0 0V
SSCG1VDD CRG(PLL1) PLL Power 1 1.2V
SSCG1VSS CRG(PLL1) PLL Ground 1 0V
Table 1.1. : Pin multiplex prohibited settings (Continued)Setting (Pinmux Group, Mode) Prohibited (Pinmux Group, Mode) Module
Socionext Europe GmbH 1 - 8 MB86R24/MB86R26Graphic Competence Center - GCC Data Sheetds-mb86r24/26-rev1.00 General Informationhttps://www.eu.socionext.com/ Rev1.00 | December 21, 2018
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Table 1.3. : Power supply(Interface specific)External Pin Name Module Description Voltage
DDRVDE DDR DDR Power 1.35V(DDR3L)/1.5V(DDR3)
MIPI_VDD MIPI MIPI IO Power 1.2V
VDH FPD(PLL) FPD Power 3.3V
VDU FPD(PLL) FPD Power 1.2V
VDP FPD FPD Power 1.8V
VDN FPD FPD Power 1.2V
VSN FPD FPD Ground 0V
AD_AVD ADC ADC Power 3.3V
AD_AVS ADC ADC Ground 0V
AD_VRH ADC High reference voltage input 3.3V
AD_VRL ADC Low reference voltage 0V
AVSP USB USB Ground 0V
AVDP USB USB Power 1.2V
AVDF1 USB USB Power 3.3V
AVSF1 USB USB Ground 0V
AVDF2 USB USB Power 1.2V
Table 1.4. : Reference powerExternal
Pin Name Module Description Formula Voltage
MVREF1_0 DDR0 DDR0 reference voltage input DDRVDE/2 0.75V(DDR3)/0.675V(DDR3L)
MVREF2_0 DDR0 DDR0 reference voltage input DDRVDE/2 0.75V(DDR3)/0.675V(DDR3L)
MVREF1_1 DDR1 DDR1 reference voltage input DDRVDE/2 0.75V(DDR3)/0.675V(DDR3L)
MVREF2_1 DDR1 DDR1 reference voltage input DDRVDE/2 0.75V(DDR3)/0.675V(DDR3L)
AD_VRO ADC ADC reference output (AD_VRH+AD_VRL)/2 1.65V
Table 1.5. : External resistanceExternal Pin Name Module Description Resistance
MZQRES_0 DDR0 DDR0 external registance 240 ohm to ground
MZQRES_1 DDR1 DDR1 external registance 240 ohm to ground
USB_EXT12K USB USB external registance 12K ohm to ground
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2. Electrical Characteristics 2.1. Maximum Ratings
Table 2.1 show the maximum ratings.
Note: • Applying stress exceeding the maximum ratings (voltage, current, temperature, etc.) may cause
damage to semiconductor devices. Never exceed the ratings above.• Never connect IC outputs or I/O pins directly, or connect them to VDD or VSS directly; otherwise
thermal destruction of elements will result, but which does not apply to pins designed to prevent signal collision.
• Provide ESD protection, such as grounding when handling the product; otherwise externally-charged electric charge flows inside the IC and discharges, which may result in damage to the circuit.
• Applying voltage higher than VDD or lower than VSS to I/O pins of CMOS IC, or applying voltage higher than the ratings between VDD and VSS may cause latch up. The latch up increases supply current, resulting in thermal destruction of elements. When handling the product, never exceed the maximum ratings.
Table 2.1. : Maximum ratingParameter Symbol Rating Unit
Supply voltage
VDDSSCG0VDDSSCG1VDD
VDDEDDRVDE
-0.5 to 1.8 (*1)-0.5 to 1.8 (*2)-0.5 to 1.8 (*2)-0.5 to 4.0 (*3)-0.5 to 2.5 (*4)
V
Input voltage VI-0.5 to VDD + 0.5 (< 1.8V)
-0.5 to VDDE + 0.5 (< 4.0V)-0.5 to DDRVDE + 0.5 (< 2.5V)
V
Output voltage VO-0.5 to VDD + 0.5 (< 1.8V)
-0.5 to VDDE + 0.5 (< 4.0V)-0.5 to DDRVDE + 0.5 (< 2.5V)
V
Storage temperature TST -55 to 125 C
Junction temperature TJ -40 to 125 C
Supply current ID
VDD: 3620VDDE: 50
DDRVDE(1.5V,1066Mbps, 1ch): 320DDRVDE(1.5V,1066Mbps, 2ch): 640
MIPI_VDD: 45.7VDH:2.7
VDP: 77.9VDN: 12.3VDU: 20.1
mA
*1: Internal power supply*2: Power supply for PLL*3: Power supply for I/O*4: Power supply for SSTL_15 I/O
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2.1.1. Maximum Ratings of USB PHY
The maximum ratings of USB PHY are shown below.
The maximum ratings are the limits that must not be exceeded. As long as USB PHY is used within the rangepredetermined in the maximum ratings, it never suffers permanent damage. However, this does not assure normallogic operation.
2.1.2. Maximum Rating of Flat Panel Display (FPD)
The maximum ratings of FPD are given in Table 2.3 .
2.1.3. Maximum Rating of MIPI
The maximum ratings of MIPI are given in Table 2.4 .
Table 2.2. : USB maximum ratingsParameter Symbol Rating Unit
Supply voltageAVDF1 VSS-0.5 to 4.0 V
AVDF2, AVDP VSS-0.5 to 1.8 V
Junction temperature TJ -40 to 125 C
Supply current
AVDF1 Total 37.5 mA
AVDF2 19.2 mA
AVDP 13.0 mA
Table 2.3. : FPD maximum ratingsParameter Symbol Rating Unit
Supply voltage
VDH -0.5 to 4.6 V
VDP -0.5 to 2.5 V
VDN,VDU -0.5 to 1.8 V
Junction temperature TJ -40 to 125 C
Table 2.4. : MIPI maximum ratingsParameter Symbol Rating Unit
Supply voltage MIPI_VDD -0.5 to 1.8 V
Input voltage VI -0.5 to MIPI_VDD + 0.5 (< 1.8V) V
Output voltage VO -0.5 to MIPI_VDD + 0.5 (< 1.8V) V
Storage temperature TST -55 to 125 C
Junction temperature TJ -40 to 125 C
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2.2. Temperature Conditions
The temperature conditions are given in Table 2.5
Note: Both conditions (Tc, and TJ) are required.
2.3. Thermal Design
Under following conditions:PCB MB86R24: JEDEC / 114.3 x 101.6 x 1.6 mm / 6 layer
MB86R26: JEDEC / 114.3 x 101.6 x 1.6 mm / 8 layer
2.4. Recommended Operating Conditions
Note: • The recommended operating conditions are primarily intended to assure the normal operation of
semiconductor device. • The values of electrical characteristics are guaranteed under the requirements above, so use the
product accordingly.
Table 2.5. : Temperature conditionsParameter Symbol Value Unit
MB86R24 Operating case temperature TC 116C
MB86R26 Operating case temperature TC 117
Junction temperature TJ -40 to 125
Table 2.6. : Thermal DesignPackage Wind θJA[K/W] ψJT[K/W]
FCBGA6760 m/s 11.2 0.90
3 m/s 7.0 0.97
FCBGA783
0 m/s 10.37 0.86
1 m/s 7.87 0.87
3 m/s 6.65 0.89
5 m/s 6.14 0.90
Package θJC[K/W]FCBGA676 1.41FCBGA783 1.31
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• Using the product without observing the conditions may affect the product’s reliability.• Performance of this product is not guaranteed if used under unspecified conditions and by an
unspecified combination of logic.
• Be sure to contact us when using the product under such conditions.
Table 2.7. : 3.3V standard CMOS I/O recommended operating conditions
Parameter SymbolValue
UnitMin. Typ. Max.
Power supply voltage
VDDE 3.0 3.3 3.6 V
VDDSSCG0VDDSSCG1VDD
1.1 1.2 1.3 V
Input voltage(High level)
3.3V CMOSVIH
2.0 - VDDE + 0.3 V
3.3V CMOS Schmitt 2.1 - VDDE + 0.3 V
Input voltage(Low level)
3.3V CMOSVIL
-0.3 - 0.8 V
3.3V CMOS Schmitt -0.3 - 0.7 V
Schmitt hysteresis voltage VH 0.2 - 1.4 V
Junction temperature TJ -40 - 125 C
Table 2.8. : SSTL15 IO(SSTL15 mode) recommended operating conditions
Parameter SymbolValue
UnitMin. Typ Max.
Power supply voltageDDRVDE 1.425 1.500 1.575 V
VDD 1.10 1.20 1.30 V
Reference voltage VREF DDRVDEx0.49 DDRVDEx0.5 DDRVDEx0.51 V
Termination voltage VTT - DDRVDE/2 - V
H level input Single (DC) VIH(DC) VREF+0.1 - DDRVDE V
L level input Single (DC) VIL(DC) VSS - VREF-0.1 V
H level input Single (AC) VIH(AC) VREF+0.175 - *1 V
L level input Single (AC) VIL(AC) *1 - VREF-0.175 V
H level input Differential (DC) VIHdiff(DC) 0.2 - *1 V
L level input Differential (DC) VILdiff(DC) *1 - -0.2 V
H level input Differential (AC) VIHdiff(AC) 0.35 - *1 V
L level input Differential (AC) VILdiff(AC) *1 - -0.35 V
Junction temperature TJ -40 - 125 CStandard SSTL15 recommended operating conditions (excerpt from JESD79-3E)*1: Overshoot / Undershoot rule of JESD79-3E.
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Table 2.9. : SSTL15 IO(SSTL135 mode) recommended operating conditions
Parameter SymbolValue
UnitMin. Typ. Max.
Power supply voltageDDRVDE 1.283 1.35 1.45 V
VDD 1.10 1.20 1.30 V
Reference voltage VREF DDRVDEx0.49 DDRVDEx0.5 DDRVDEx0.51 V
Termination voltage VTT - DDRVDE/2 - V
H level input Single (DC) VIH(DC) VREF+0.09 - DDRVDE VL level input Single (DC) VIL(DC) VSS - VREF-0.09 VH level input Single (AC) VIH(AC) VREF+0.135 - *1 VL level input Single (AC) VIL(AC) *1 - VREF-0.135 VH level input Differential (DC) VIHdiff(DC) 0.180 - *1L level input Differential (DC) VILdiff(DC) *1 - -0.180H level input Differential (AC) VIHdiff(AC) 0.270 - *1L level input Differential (AC) VILdiff(AC) *1 - -0.270
Junction temperature TJ -40 - 125 CStandard SSTL15(SSTL135 mode) recommended operating conditions (except from JESD79--3-1)*1: Overshoot / Undershoot rule of JESD79-3-1.
Table 2.10. : USB recommended operation condition
Parameter SymbolValue
UnitMin. Typ. Max.
Supply voltage
AVDF1 3.0 3.3 3.6 V
AVDF2 1.1 1.2 1.3 VAVDP 1.1 1.2 1.3 V
Junction temperature TJ -40 - 125 CThe clock input to USB_CRYCLK48 should meet the following requirements. Clock of 48MHz ± 200ppmJitter of 50ps or less
Table 2.11. : FPD recommended operation condition
Parameter SymbolValue
UnitMin. Typ. Max.
Supply voltage
VDU
VDN1.11.1 1.2 1.3 V
VDP 1.65 1.8 1.95 VVDH 3.0 3.3 3.6 V
Junction temperature TJ -40 - 125 C
Table 2.12. : MIPI recommended operation condition
Parameter SymbolValue
UnitMin. Typ. Max.
Supply voltage MIPI_VDD 1.1 1.2 1.3 V
Junction temperature TJ -40 - 125 C
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2.5. Power ON
2.5.1. Recommended Power ON/OFF Sequence
The recommended order of power supply by power-on/power-off is:
[Power on]: (1) VDD, SSCG0VDD, SSCG1VDDAVDF2, AVDP, VDU, VDN, MIPI_VDD(1.2V)DDRVDE, VDP, AD_AVD, VDDE, AVDF1, AD_VRH, VDH (1.5V, 1.8V, 3.0V, 3.3V) * in random orderGeneric signal
[Power off]: (1) Generic signal(2) DDRVDE, VDP, AD_AVD, VDDE, AVDF1, AD_VRH, VDH (1.5V, 1.8V, 3.0V, 3.3V) * in random order(3) VDD, SSCG0VDD, SSCG1VDDAVDF2, AVDP, VDU, VDN, MIPI_VDD(1.2V)
Figure 2.1. : Recommended power supply order (1)
There is no limitation on the sequence of the power ON/OFF of VDD, VDDE, and DDRVDE. But to avoid possiblebus conflicts, please:
Do not supply VDDE longer than 1sec continuously, when VDD is not supplied. Do not supply DDRVDE longer than 0.1sec (=100ms) continuously, when VDD is not supplied. (see
Figure 2.2.):
Figure 2.2. : The order of recommended power supply (2)
1 sec. or less
VDD
1 sec. or less
VDDE
0.1 sec or less
VDD
DDRVDE
0.1 sec or less
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And please keep also in mind:
Supply power ON/OFF so that power for SSCG0VDD/SSCG1VDD does not exceed VDD.It is mandatory to turn ON all powers. Turning part of power ON is prohibited.CMOS IC is unstable immediately after power ON. Perform a reset immediately.Set the reset pins (XTRST, XRST) to Low, when power ON.Input REFCLK immediately after power ON.At least 100 clocks of REFCLK is required for the reset signal “L” applied to the XRST pin to be
transmitted to all the internal circuits.
2.5.2. Power ON Timing Chart
Figure 2.3. : Power on timing chart
Note: • Please input the XTRST, XRST, pins to Low when power ON.• Please keep the XTRST and XRST pins High after inputting "L" for 2 µs or more.• Please access other registers or memory controller after PLL LockUp Time.• Please input XTRST as well as XRST when JTAGSEL="H".
VDDE
DDRVDE
XRST
XTRST
Note: The clock is an image and no actual cycle
REFCLK
Input “L” when power ON
Input clock immediately after power ON
PLL Lock-up time (max:200μs)
VDD
2μs or more
XSRST Output “L” during resetPlease Input XSRST after XRST is ̒H’
When JTAGSEL = ̔H’, the XTRST input is necessary
Input “L” when power ON
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2.6. DC Characteristics
2.6.1. 3.3V Standard CMOS I/O
Table 2.13 shows 3.3V Standard CMOS I/O DC characteristics.
Measurement conditions: VDDE = 3.3 ±0.3 V, VSS = 0 V, Tj = -40 to 125°C
Table 2.13. : Standard CMOS I/O DC characteristics
Parameter Symbol ConditionRating
UnitMin Typ Max
H level input voltage VIH 2.0 - VDDE + 0.3 V
L level input voltage VIL -0.3 - 0.8 V
H level output voltage VOH IOH = -100mA VDDE - 0.2 - VDDE V
L level output voltage VOL IOL = 100mA 0 - 0.2 V
H level output V-I characteristic -
Driving capability 2mA IOH = 2mA
Refer to Figure 2.4, Figure 2.4, Figure 2.6, and Figure 2.7.
-Driving capability 4mA IOH = 4mA
Driving capability 6mA IOH = 6mA
Driving capability 8mA IOH = 8mA
L level output V-I characteristic -
Driving capability 2mA IOL = 2mA
Driving capability 4mA IOL = 4mA
-Driving capability 6mA IOL= 6mA
Driving capability 8mA IOL= 8mA
Input leakage current IL - - 10 A
Pull-up/pull-down resistance RpPull-up VIL=0VPull-down VIH= VDDE
15 33 70 kΩ
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2.6.1.1. 3.3V Standard CMOS I/O V-I Characteristic (Driving Capability 2mA)
ConditionsMIN: Process = SlowTJ = 125CVDDE = 3.0 VTYP: Process = TypicalTJ = 25CVDDE = 3.3 VMAX: Process = FastTJ = -40CVDDE = 3.6 V
Figure 2.4. : 3.3V standard CMOS I/O V-I characteristic (Driving capability 2mA)
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2.6.1.2. 3.3V Standard CMOS I/O V-I Characteristic (Driving Capability 4mA)
ConditionsMIN: Process = SlowTJ = 125CVDDE = 3.0 VTYP: Process = TypicalTJ = 25CVDDE = 3.3 VMAX: Process = FastTJ = -40CVDDE = 3.6 V
Figure 2.5. : 3.3V standard CMOS I/O V-I characteristic (Driving capability 4mA)
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2.6.1.3. 3.3V Standard CMOS I/O V-I Characteristic (Driving Capability 6mA)
ConditionsMIN: Process = SlowTJ = 125CVDDE = 3.0 VTYP: Process = TypicalTJ = 25CVDDE = 3.3 VMAX: Process = FastTJ = -40CVDDE = 3.6 V
Figure 2.6. : 3.3V standard CMOS I/O V-I characteristic (Driving capability 6mA)
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2.6.1.4. 3.3V Standard CMOS I/O V-I Characteristic (Driving Capability 8mA)
ConditionsMIN: Process = SlowTJ = 125CVDDE = 3.0 VTYP: Process = TypicalTJ = 25CVDDE = 3.3 VMAX: Process = FastTJ = -40CVDDE = 3.6 V
Figure 2.7. : 3.3V standard CMOS I/O V-I characteristic (Driving capability 8mA)
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2.6.2. SSTL15 I/O
Table 2.14. : Output Driver DC Characteristics, assuming RZQ=240Ω by SSTL15 mode
RONnom Resistor Vout Min Nom Max Unit Notes
34
RON34pd
VOLdc=0.2xDDRVDE 0.6 1.0 1.1 RZQ/7 *1
VOMdc=0.5xDDRVDE 0.9 1.0 1.1 RZQ/7 *1
VOHdc=0.8xDDRVDE 0.9 1.0 1.4 RZQ/7 *1
RON34pu
VOLdc=0.2xDDRVDE 0.9 1.0 1.4 RZQ/7 *1
VOMdc=0.5xDDRVDE 0.9 1.0 1.1 RZQ/7 *1
VOHdc=0.8xDDRVDE 0.6 1.0 1.1 RZQ/7 *1
40
RON40pd
VOLdc=0.2xDDRVDE 0.6 1.0 1.1 RZQ/6 *1
VOMdc=0.5xDDRVDE 0.9 1.0 1.1 RZQ/6 *1
VOHdc=0.8xDDRVDE 0.9 1.0 1.4 RZQ/6 *1
RON40pu
VOLdc=0.2xDDRVDE 0.9 1.0 1.4 RZQ/6 *1
VOMdc=0.5xDDRVDE 0.9 1.0 1.1 RZQ/6 *1
VOHdc=0.8xDDRVDE 0.6 1.0 1.1 RZQ/6 *1
48
RON48pd
VOLdc=0.2xDDRVDE 0.6 1.0 1.1 RZQ/5 *1
VOMdc=0.5xDDRVDE 0.9 1.0 1.1 RZQ/5 *1
VOHdc=0.8xDDRVDE 0.9 1.0 1.4 RZQ/5 *1
RON48pu
VOLdc=0.2xDDRVDE 0.9 1.0 1.4 RZQ/5 *1
VOMdc=0.5xDDRVDE 0.9 1.0 1.1 RZQ/5 *1
VOHdc=0.8xDDRVDE 0.6 1.0 1.1 RZQ/5 *1
60
RON60pd
VOLdc=0.2xDDRVDE 0.6 1.0 1.1 RZQ/4 *1
VOMdc=0.5xDDRVDE 0.9 1.0 1.1 RZQ/4 *1
VOHdc=0.8xDDRVDE 0.9 1.0 1.4 RZQ/4 *1
RON60pu
VOLdc=0.2xDDRVDE 0.9 1.0 1.4 RZQ/4 *1
VOMdc=0.5xDDRVDE 0.9 1.0 1.1 RZQ/4 *1
VOHdc=0.8xDDRVDE 0.6 1.0 1.1 RZQ/4 *1
Mismatch between pull-up and pull-down, MMPuPd
VOMdc0.5xDDRVDE
-10 - +10 % *1,*2
*1: The tolerance limits are specified after calibration with stable voltage and temperature.*2: Mismatch specification between pull-up and pull-down output impedances. Both the RONpu and RONpd are defined by 0.5 x DDRVDE.
(See the equation below.)
MMPuPdRONPu RONPd–
RONNom----------------------------------------- 100=
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under the condition that RONPd is turned off.
under the condition that RONPu is turned off.
Table 2.15. : Output Driver DC Characteristics, assuming RZQ=240Ω by SSTL135 modeRONnom Resistor Vout min nom max Unit Notes
34
RON34pd
VOLdc=0.2xDDRVDE 0.6 1.0 1.15 RZQ/7 *1
VOMdc=0.5xDDRVDE 0.9 1.0 1.15 RZQ/7 *1
VOHdc=0.8xDDRVDE 0.9 1.0 1.45 RZQ/7 *1
RON34pu
VOLdc=0.2xDDRVDE 0.9 1.0 1.45 RZQ/7 *1
VOMdc=0.5xDDRVDE 0.9 1.0 1.15 RZQ/7 *1
VOHdc=0.8xDDRVDE 0.6 1.0 1.15 RZQ/7 *1
40
RON40pd
VOLdc=0.2xDDRVDE 0.6 1.0 1.15 RZQ/6 *1
VOMdc=0.5xDDRVDE 0.9 1.0 1.15 RZQ/6 *1
VOHdc=0.8xDDRVDE 0.9 1.0 1.45 RZQ/6 *1
RON40pu
VOLdc=0.2xDDRVDE 0.9 1.0 1.45 RZQ/6 *1
VOMdc=0.5xDDRVDE 0.9 1.0 1.15 RZQ/6 *1
VOHdc=0.8xDDRVDE 0.6 1.0 1.15 RZQ/6 *1
48
RON48pd
VOLdc=0.2xDDRVDE 0.6 1.0 1.15 RZQ/5 *1
VOMdc=0.5xDDRVDE 0.9 1.0 1.15 RZQ/5 *1
VOHdc=0.8xDDRVDE 0.9 1.0 1.45 RZQ/5 *1
RON48pu
VOLdc=0.2xDDRVDE 0.9 1.0 1.45 RZQ/5 *1
VOMdc=0.5xDDRVDE 0.9 1.0 1.15 RZQ/5 *1
VOHdc=0.8xDDRVDE 0.6 1.0 1.15 RZQ/5 *1
60
RON60pd
VOLdc=0.2xDDRVDE 0.6 1.0 1.15 RZQ/4 *1
VOMdc=0.5xDDRVDE 0.9 1.0 1.15 RZQ/4 *1
VOHdc=0.8xDDRVDE 0.9 1.0 1.45 RZQ/4 *1
RON60pu
VOLdc=0.2xDDRVDE 0.9 1.0 1.45 RZQ/4 *1
VOMdc=0.5xDDRVDE 0.9 1.0 1.15 RZQ/4 *1
VOHdc=0.8xDDRVDE 0.6 1.0 1.15 RZQ/4 *1
Mismatch between pull-up and pull-down,MMPuPd
VOMdc0.5xDDRVDE
-10 - +10 % *1,*2
*1: The tolerance limits are specified after calibration with stable voltage and temperature.*2: Mismatch specification between pull-up and pull-down output impedances. Both the RONpu and RONpd are defined by 0.5 x DDRVDE. (See the equation below.)
MMPuPdRONPu RONPd–
RONNom----------------------------------------- 100=
RONPuDDRVDE VOut–
IOut------------------------------------------=
RONPdVOutIOut------------=
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Figure 2.8. : Output Driver DC Characteristics Definition
Table 2.16. : ODT DC Characteristics, assuming RZQ=240Ω by SSTL15 modeRTT Resistor Vout Min Nom Max Unit Notes
120
RTT120pd240
VOLdc=0.2xDDRVDE 0.6 1.0 1.1 RZQ *1
0.5xDDRVDE 0.9 1.0 1.1 RZQ *1
VOHdc=0.8xDDRVDE 0.9 1.0 1.4 RZQ *1
RTT120pu240
VOLdc=0.2xDDRVDE 0.9 1.0 1.4 RZQ *1
0.5xDDRVDE 0.9 1.0 1.1 RZQ *1
VOHdc=0.8xDDRVDE 0.6 1.0 1.1 RZQ *1
RTT120 VIL(ac) to VIH(ac) 0.9 1.0 1.6 RZQ/2 *1,*2
60
RTT60pd120
VOLdc=0.2xDDRVDE 0.6 1.0 1.1 RZQ/2 *1
0.5xDDRVDE 0.9 1.0 1.1 RZQ/2 *1
VOHdc=0.8xDDRVDE 0.9 1.0 1.4 RZQ/2 *1
RTT60pu120
VOLdc=0.2xDDRVDE 0.9 1.0 1.4 RZQ/2 *1
0.5xDDRVDE 0.9 1.0 1.1 RZQ/2 *1
VOHdc=0.8xDDRVDE 0.6 1.0 1.1 RZQ/2 *1
RTT60 VIL(ac) to VIH(ac) 0.9 1.0 1.6 RZQ/4 *1,*2
40
RTT40pd80
VOLdc=0.2xDDRVDE 0.6 1.0 1.1 RZQ/3 *1
0.5xDDRVDE 0.9 1.0 1.1 RZQ/3 *1
VOHdc=0.8xDDRVDE 0.9 1.0 1.4 RZQ/3 *1
RTT40pu80
VOLdc=0.2xDDRVDE 0.9 1.0 1.4 RZQ/3 *1
0.5xDDRVDE 0.9 1.0 1.1 RZQ/3 *1
VOHdc=0.8xDDRVDE 0.6 1.0 1.1 RZQ/3 *1
RTT40 VIL(ac) to VIH(ac) 0.9 1.0 1.6 RZQ/6 *1,*2
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Deviation of VM w.r.t VDE/2, DVM -7 - +7 % *1,*3*1: Defined as the specification after calibration under stable voltage and temperature. *2: Definition of RTT measurement.
*3: DVM definition. In the DRAM specification, it is specified as ±5%. However, for the SSTL15 I/O buffers, it is specified as ±7%. The values are calculated from the intermediate voltage (VM) when the ODT impedances of the test pins without load are balanced.
Table 2.17. : ODT DC Characteristics, assuming RZQ=240Ω by SSTL135 modeRTT Resistor Vout min nom max Unit Notes
120
RTT120pd240
VOLdc=0.2xDDRVDE 0.6 1.0 1.15 RZQ *1
0.5xDDRVDE 0.9 1.0 1.15 RZQ *1
VOHdc=0.8xDDRVDE 0.9 1.0 1.45 RZQ *1
RTT120pu240
VOLdc=0.2xDDRVDE 0.9 1.0 1.45 RZQ *1
0.5xDDRVDE 0.9 1.0 1.15 RZQ *1
VOHdc=0.8xDDRVDE 0.6 1.0 1.15 RZQ *1
RTT120 VIL(ac) to VIH(ac) 0.9 1.0 1.65 RZQ/2 *1,*2
60
RTT60pd120
VOLdc=0.2xDDRVDE 0.6 1.0 1.15 RZQ/2 *1
0.5xDDRVDE 0.9 1.0 1.15 RZQ/2 *1
VOHdc=0.8xDDRVDE 0.9 1.0 1.45 RZQ/2 *1
RTT60pu120
VOLdc=0.2xDDRVDE 0.9 1.0 1.45 RZQ/2 *1
0.5xDDRVDE 0.9 1.0 1.15 RZQ/2 *1
VOHdc=0.8xDDRVDE 0.6 1.0 1.15 RZQ/2 *1
RTT60 VIL(ac) to VIH(ac) 0.9 1.0 1.65 RZQ/4 *1,*2
40
RTT40pd80
VOLdc=0.2xDDRVDE 0.6 1.0 1.15 RZQ/3 *1
0.5xDDRVDE 0.9 1.0 1.15 RZQ/3 *1
VOHdc=0.8xDDRVDE 0.9 1.0 1.45 RZQ/3 *1
RTT40pu80
VOLdc=0.2xDDRVDE 0.9 1.0 1.45 RZQ/3 *1
0.5xDDRVDE 0.9 1.0 1.15 RZQ/3 *1
VOHdc=0.8xDDRVDE 0.6 1.0 1.15 RZQ/3 *1
RTT40 VIL(ac) to VIH(ac) 0.9 1.0 1.65 RZQ/6 *1,*2
Table 2.16. : ODT DC Characteristics, assuming RZQ=240Ω by SSTL15 modeRTT Resistor Vout Min Nom Max Unit Notes
RTTVIH ac VIL ac –
I VIH ac I VIL ac –-----------------------------------------------------=
VM2 VMDDRVDE------------------------- 1– 100=
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under the condition that RTTPd is turned off.
under the condition that RTTPu is turned off.
Figure 2.9. : ODT DC Characteristics Definition
Deviation of VM w.r.t VDE/2, DVM -10 - +10 % *1,*3*1: Defined as the specification after calibration under stable voltage and temperature. *2: Definition of RTT measurement.
*3: VM definition. In the DRAM specification, it is specified as ±5%. And, for the SSTL15 I/O buffers, it is specified as ±10%. The values are calculated from the intermediate voltage (VM) when the ODT impedances of the test pins without load are balanced.
Table 2.17. : ODT DC Characteristics, assuming RZQ=240Ω by SSTL135 mode (Continued)
RTTVIH ac VIL ac –
I VIH ac I VIL ac –-----------------------------------------------------=
VM2 VMDDRVDE------------------------- 1– 100=
RTTPuDDRVDE VOut–
IOut------------------------------------------=
RTTPdVOutIOut------------=
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2.6.3. SSCG I/O
These Recommended SSCG PLL Operation Conditions are settled to guarantee correct operation of SSCG PLL.SSCG PLL Spec (Table 2.19 ) is guaranteed under the recommended PLL operation conditions.
The values are specified under the condition that Power Supply has no noise.In this PLL, VCO do no oscillate free-running. The output frequency of SSCG PLL becomes 0Hz when
input clock CK is assumed to be 0Hz. Moreover, SSCG PLL operation at this time (CK=0Hz) is not guaranteed.
(*1) Depend on multiples.
(*2) Depends on Input frequency
Table 2.18. : Recommended operating conditionsParameter Symbol Conditions Min Typ Max Unit
Power voltage V - 1.1 1.2 1.3 V
Junction temperature Tj - -40 25 125 deg.
Reference clock frequency Fref - 20 - 33.33 MHz
Input clock pulse widthThigh High pulse 1.5 - - ns
Tlow Low pulse 1.5 - - ns
Reset enable time Treset - 3 - - us
Table 2.19. : SSCG characteristic
Parameter SymbolSpecification
UnitMin Typ Max
1 Lock-up Time TL - 200 us
2 Current Consumption I - 2 4 mA
3 Stand-by Current Ioff - 3 500 µA
4 Output frequency Fcore 400 - 1600 MHz
5 VCO Output frequency Fout 800 - 1600 MHz
6 Modulation rate Om 0.5 5 (*1) %
7 Modulation frequency Fmod Fref/4096 Fref/1024 (*2) Hz
Multiple MAX Modulation Rate8 - 120 1%8 - 96 2%8 - 62 3%8 - 46 4%8 - 36 5%
Multiple MAX Modulation Rate20 - 25MHz Fref/1024
25 - 33.33MHz Fref/2048
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2.6.3.1. PLL Clock Jitter
PLL clock jitter is calculated by the following formula.Please confirm the permissible input jitter of the outer moduleto its manufacturer.
(1)Modulation off * CRG_P or SSCGCTL.SSEN=0(CCNT Register)
f:PLL frequency n:divide
(1-a)CRPLC.PSMODE=1(CRG Register) Jitter=0.03*sqrt(n)/f [sec] (1-b) CRPLC.PSMODE=0(CRG Register)
Jitter=0.05*sqrt(n)/f [sec]
(2)Modulation on *SSCGCTL.SSEN=1(CCNT Register)
f:PLL frequency n:divide
(2-a)CRPLC.PSMODE=1(CRG Register) Jitter=0.03*n/f [sec] (2-b) CRPLC.PSMODE=0(CRG Register)
Jitter=0.05*n/f [sec]
[example]
SSCGCTL.SSEN=1(Modulation on) CRPLC.PSMODE=1 Modulation rate 0.5%
PLL frequency 1600MHz Calculation CLK0(400MHz) Jitter
Jitter=0.03*4/(1600*10^6)=75*10^(-12)=75[ps] Modulation=12.5[ps] 0.5% of 400MHz Jitter'=Modulation+Jitter=12.5[ps]+75[ps]87.5[ps]
2.6.3.2. Difference Permission Level of the Crystal
Please make the difference of CLKX0 and CLKX1 less than 100ps.
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2.6.4. I2C Bus Fast Mode I/O
Note: Pins in the I2C IO buffer is as follows: I2C0_SCLI2C0_SDAI2C1_SCLI2C1_SDA
Table 2.20. : I2C I/O direct current characteristic
Parameter & Condition SymbolStandard Mode Fast Mode(*1)
UnitMin Max Min Max
"L" level input voltage VIL -0.5 0.3 VDDE -0.5 0.3 VDDE V
"H" level input voltage VIH 0.7 VDDE (*2) 0.7 VDDE (*2) V
Schmitt trigger hysteresisVDDE > 2[v]
Vhys n/a n/a 0.05 VDDE - V
"L" level output voltageSink current 3[mA]VDDE > 2[V]
VOL1 0 0.4 0 0.4 V
Output slew rate (Tfall)Bus capacitance 10[pF] ~ 400[pF]VIH (min.) to VIL (max.)
tof - 25020 + 0.1Cb
(*3)250 ns
Data line leakageInput voltage 0.1 ~ 0.9 VDDE (max.) Ii -10 10 -10 10 A
I/O pin capacitance Ci - 10 - 10 pF*1: This I2C Bus Fast Mode I/O buffer is downward compatible with Standard Mode. *2: 65 nm technology: Complies with the maximum ratings 4[V]. *3: Cb: Capacitance of one bus line(unit: pF)*4: The I2C Bus Fast Mode I/O Buffer itself has no function to prevent a spike of 50 ns pulse width (max.). Therefore, provide any input filter
to prevent a spike for both internal or external semiconductor device.
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2.6.4.1. I2C IO V-I Characteristic Chart
Figure 2.10. : I2C V-I characteristic chart
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2.6.5. USB I/O
Table 2.21. : Recommended operating conditions (High-speed)
Parameter SymbolValue
UnitMin Typ Max
Input levels for high-speed:High-speed squelch detection threshold (differential signal amplitude) VHSSQ 100 - 200 mVHigh-speed disconnect detection threshold (differential signal amplitude) VHSDSC 525 - 625 mV
High-speed differential input signaling levels (this spec is based on "Tem-plate 6")
150(the absolute
value)- - mV
High-speed data signaling common mode voltage range (guideline for receiver) VHSCM -50 - 500 mV
Output levels for high-speed:High-speed idle level VHSOI -10.0 - 10.0 mVHigh-speed data signaling high VHSOH 360 - 440 mVHigh-speed data signaling low VHSOL -10.0 - 10.0 mVChirp J level (differential voltage) VCHIRPJ 700 - 1100 mVChirp K level (differential voltage) VCHIRPK -900 - -500 mV
Terminations in high-speed:Termination voltage in high-speed VHSTERM -10 - 10 mV
Table 2.22. : Recommended operating conditions (Full-speed/Low-speed)
Parameter SymbolValue
UnitMin Typ Max
Input levels for full-speed/low-speed:High (driving) VIH 2.0 - - VHigh (floating) VIHZ 2.7 - 3.6 VLow VIL - - 0.8 VDifferential input sensitivity VDI 0.2 - - VDifferential common mode range VCM 0.8 - 2.5 V
Output levels for full-speed/low-speed:Low VOL 0.0 - 0.3 VHigh (driven) VOH 2.8 - 3.6 VSE1 VOSE1 0.8 - - VOutput signal crossover voltage VCRS 1.3 - 2.0 V
Input capacitance for full-speed/low-speed:
Downstream facing port (being shared with upstream facing port at device mode, so the less value is selected as the maximum spec)
CIND(CINUB)
- - 100 pF
Transceiver edge rate control capacitance CEDGE - - 75 pFTerminations in full-speed/low-speed:
Bus pull-up resistor on upstream port (idle bus) (this is used only in the device mode (HOSTMODE = "0" setting).) RPUI 0.9 - 1.575 kΩ
Bus pull-up resistor on upstream port (upstream port receiving) (this is used only in the device mode (HOSTMODE = "0" setting).) RPUA 1.425 - 3.090 kΩ
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2.6.6. FPD I/O
The LVDS driver signal levels are defined in Figure 2.12
Figure 2.11. : LVDS driver signal levels
Figure 2.12. : Measurement circuit of LVDS driver signal levels
Input impedance exclusive of pull-up/pull-down ZINP 300 - - kΩTermination voltage on upstream port pull-up VTERM 3.0 - 3.6 V
Table 2.23. : FPD DC specificationsSymbol Parameter Conditions Min Typ Max Unit
LVDS driver
Voh Output voltage high Rload=100 Ohm 1.55 V
Vol Output voltage low Rload=100 Ohm 0.85 V
|Vod| Output differential voltage Rload=100 Ohm 250 450 mV
Vos Output offset voltage Rload=100 Ohm 1.075 1.325 V
Table 2.22. : Recommended operating conditions (Full-speed/Low-speed) (Continued)
Parameter SymbolValue
UnitMin Typ Max
V(posi)
V(nega)
Vol_min
Single-ended
GND
Vod = V(posi)-V(nega)
Differential
Voh_max
Vos = [V(posi)+V(nega) ]/2
|Vod|_min
|Vod|_max
0V diff.
V(posi)
V(nega)
VRload
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2.6.7. MIPI D-PHY I/O
Table 2.24. : MIPI D-PHY DC specificationsParameter Symbol Conditions Min Typ Max Unit
HSRX Mode
Common-mode voltage HS receive mode VCMRX(DC)
1) 2) 70 - 330 mV
Differential input high threshold VIDTH - - - 70 mV
Differential input low threshold VIDTL - -70 - - mV
Single-ended input high voltage VIHHS 1) - - 460 mV
Single-ended input low voltage VILHS 1) -40 - - mV
Single-ended threshold for HS termi-nation enable VTERM-EN - - - 450 mV
Differential input impedance ZID - 80 100 125 ohm
Notes:1) Excluding possible additional RF interference of 100mV peak sine wave beyond 450MHz.2) This table value includes a ground difference of 50mV between the transmitter and the receiver, the static common-mode level toler-
ance and variations below 450MHz.
LPRX Mode
Logic 1 input voltage VIH - 880 - - mV
Logic 0 input voltage, not in ULP State VIL - - - 470 mV
Logic 0 input voltage, ULP State VIL-ULPS - - - 300 mV
Input hysteresis VHYST - 20 - - mV
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2.6.8. ADC I/O
Table 2.25. : Recommended operating conditions
Parameter Symbol Pin NameValue
UnitsMin Typ Max
Power Supply VoltageVvd VDD 1.10 1.20 1.30 V
Vavd AD_AVD 2.70 3.30 3.60 V
Reference Voltage (H) Vrh AD_VRH Vavd V
Reference Voltage (L) Vrl AD_VRL Vss (*1) V
Decoupling Capacitor Cref (*2) AD_VRO 0.1 - - µF
Analog Input Voltage Vin AD_VIN0 -AD_VIN3 Vrl - Vrh V
Analog Input Frequency Fvin AD_VIN0 -AD_VIN3 0 - Hz
Conversion Rate Fs (*3) - - - 93.75 KS/s
Sampling Cock Frequency Fc (*3) - 2.M - 24M Hz
Number of Sampling Clock Ns (*3) - 240 - - Cycle
Number of Conversion Clock Nc (*3) - 16 - - Cycle
Junction Temperature Tj - -40 - 125 degree C*1 Vss = AVS (Analogue GND).*2 Outputs incorrect result at the instant following power on or at the resumption from power down mode.
Resumption Time (tRS) has a relationship with the capacity value of external capacity.tRS = 2.5ms * Cref / 0.1uF
*3 Fc = Fs * (Ns + Nc)The conversion rate is dependent on output impedance drive the AD_VIN(x).Choose the Fc or Ns to satisfy the expression [ Sampling time > tA ] . (tA : Analogue input aperture time)Rimp is output impedance of the driver drives AD_VIN(x).To put the error of the sampled analog input in 0.5LSB or less, the relation between tA and Rimp is shownin the following figure.
Fs2-----
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The relation between INL and Rimp is shown in the following table:
Table 2.26. : ADC characteristic
Parameter Symbol Pin Name ConditionsValue
UnitsMin Typ Max
Resolution BIT - - 12 Bits
Supply current
IVD VDD - - 0.03 mA
IAVD AD_AVDVRH=AVDH, VRL=AVS 1.8 3.1 mA
IDS VDD, AD_AVD Power down 0 - 60 µA
Input Leak Current IVINonAD_VIN0 -AD_VIN3 Selected AD_VIN(x) -1.0 1.0 µA
Reference Voltage (M) VR AD_VR0 -2.0 2.0 V%
Reference Resistance RRAD_VRH AD_VRL
Between AD_VRH and AD_VRL 4.1 6.6 10.2 K
Zero Transmission Voltage*1
VZT - Between 0 and 1 Typ-20 Typ+20 mV
Full Scale Transmission Voltage*1
VFST -Between 4094 and 4095 Typ-20 Typ+20 mV
Integral Non-linearity *2 INL - End Point Method -3.0 - 3.0 LSB
Differential Non-linearity *2 DNL - End Point Method -2.0 - 2.0 LSB*1: VZT and VFST are dependent on chip LAYOUT and wiring resistance. VZT and VFST are dependent on output impedance of the driver drives VIN (Rimp). The relation between VZT / VFST and Rimp is shown in the following table:
Rimp()
VZT VFSTMin Typ Max Min Typ Max
1000 Typ - 20 Typ+20 Typ - 20 Typ+20
10000 Typ - 30 Typ+20 Typ - 20 Typ+25
100000 Typ - 100 Typ+20 Typ - 20 Typ+50
*2: 1LSB=(VFST - VZT)/4094, INLn=(Vn-(1LSB×(n-1)+VZT))/1LSB, DNLn=(Vn+1-Vn)/1LSB-1 INL is dependent on output impedance of the driver drives VIN (Rimp).
Rimp ()INL
Min Typ Max1000 -3 - 310000 -8 - 8100000 -38 - 38
AD_VIN(x)Vavd
2-----------=
Vrh Vrl+2
----------------------
VrlVrh Vrl–
4096--------------------------+
VrlVrh Vrl–
4096--------------------------–
Vrl Vrh Vrl– +
4096-------------------------------------------
Vrh Vrh Vrl– –
4096--------------------------------------------
Vrl Vrh Vrl– +
4096-------------------------------------------
Vrh Vrh Vrl– –
4096--------------------------------------------
Vrl Vrh Vrl– +
4096-------------------------------------------
Vrh Vrh Vrl– –
4096--------------------------------------------
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2.7. AC-Characteristics
This chapter explains the AC timing of external terminals.
2.7.1. External Bus Controller Signal Timing
Figure 2.13. : SRAM/NOR Flash Read
Table 2.27. : Memory controller signal timing
Signal Name Symbol DescriptionValue
UnitMin Typ Max
MEM_XCS[2:0] Tcso Chip Select delay time - - 13 ns
MEM_EA[26:1] Tao Address delay time - - 13 ns
MEM_ED[31:0]
Tdo Data output delay time - - 13 ns
Tdoz Data output HiZ time - - 13 ns
Tdsr SRAM/NOR Flash data setup time 13.5 - - ns
Tdhr SRAM/NOR Flash data hold time 0 - - ns
Tdsp NOR Flash page Read data setup time 13.5 - - ns
Tdhp NOR Flash page Read data hold time 0 - - ns
MEM_RDY Tdri RDY delay time 0.5 ns
MEM_XRD Trdo XRD delay time - - 13 ns
MEM_XWR[3:0] Twro XWR delay time - - 13 nsOutput DeLay's standard clock is an internal clock. A standard clock of MEM_RDY is an internal clock. TRACC : Timing Register[3:0].RACC[3:0]TRADC : Timing Register[7:4].RADC[3:0]TWADC : Timing Register[23:20].WADC[3:0]
MEM_CLK(AHBCLK)
MEM_XCS0, 1, 2
MEM_EA[26:1]
MEM_ED[31:0]
Tcso
Tao
MEM_XRD
Trdo
Tdsr Tdhr
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Figure 2.14. : SRAM/NOR Flash Write
Figure 2.15. : Low speed device Read
MEM_CLK(AHBCLK)
MEM_XCS0, 1, 2
MEM_EA[26:1]
MEM_ED[31:0]
Tcso
Tao
MEM_XWR[1:0]
Twro
Tdo Tdoz
X
MEM_ED[31:0]
Tcso
Tao
2 Cycle
Trdo
Tao
Tcso
TdhrTdsr
Trdo
Trdi
TRACC + TCSO
MEM_CLK(AHBCLK)
MEM_XCS0, 1, 2
MEM_EA[26:1]
MEM_RDY
MRDY(Internal signal)
MEM_XRD TRADC + Trdo
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Figure 2.16. : Low speed device Write
Figure 2.17. : NOR Flash Page Read
Tdo Tdo Tdo
X
Tcso
Tao
2 Cycle
Twro
Tao
Tcso
Twro
Trdi
TWADC + Twro
TWACC + Tcso
MEM_ED[31:0]
MEM_CLK(AHBCLK)
MEM_XCS0, 1, 2
MEM_EA[26:1]
MEM_RDY
MRDY(Internal signal)
MEM_XRD
MEM_ED[31:0]
MEM_CLK(AHBCLK)
MEM_XCS0, 1, 2
MEM_EA[26:1]
MEM_RDY
MEM_XRD
Tdsp Tdhp
Tcso
Tao Tao
Tcso
Trdo
Tao
Tdsp Tdhp
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2.7.2. DDR Controller Signal Timing
Table 2.28. : DDR Controller(DDR3-1066) signal timing by SSTL15 mode
Signal Name Symbol DescriptionValue
UnitMin Max
MA*_0MBA*_0,MCKE*_0,MODT*_0, MXCAS*_0,MXCS*_0,MXRAS*_0,MXWE*_0
tphy_IS_CA Control and Address setup time - 661 ps
tphy_IH_CA Control and Address hold time - 857 ps
MA*_1MBA*_1,MCKE*_1,MODT*_1, MXCAS*_1,MXCS*_1,MXRAS*_1,MXWE*_1
tphy_IS_CA Control and Address setup time - 611 ps
tphy_IH_CA Control and Address hold time - 895 ps
MDQS0_0,MDQS1_0,MXDQS0_0,MXDQS1_0
tphy_CKDQS_min DQS output access time from CLK -349 - ps
tphy_CKDQS_max DQS output access time from CLK - 216 ps
tphy_RTT_Gate_min Round Trip time from CLK out to Read DQS 74 - ps
tphy_RTT_Gate_max Round Trip time from CLK out to Read DQS - 982 ps
MDQS2_0,MDQS3_0,MXDQS2_0,MXDQS3_0
tphy_CKDQS_min DQS output access time from CLK -236 - ps
tphy_CKDQS_max DQS output access time from CLK - 320 ps
tphy_RTT_Gate_min Round Trip time from CLK out to Read DQS 206 - ps
tphy_RTT_Gate_max Round Trip time from CLK out to Read DQS - 1,125 ps
MDQS0_1,MDQS1_1,MXDQS0_1,MXDQS1_1
tphy_CKDQS_min DQS output access time from CLK -361 - ps
tphy_CKDQS_max DQS output access time from CLK - 210 ps
tphy_RTT_Gate_min Round Trip time from CLK out to Read DQS 70 - ps
tphy_RTT_Gate_max Round Trip time from CLK out to Read DQS - 969 ps
MDQS2_1,MDQS3_1,MXDQS2_1,MXDQS3_1
tphy_CKDQS_min DQS output access time from CLK -217 - ps
tphy_CKDQS_max DQS output access time from CLK - 356 ps
tphy_RTT_Gate_min Round Trip time from CLK out to Read DQS 186 - ps
tphy_RTT_Gate_max Round Trip time from CLK out to Read DQS - 1084 ps
MDQ[7:0]_0,MDQ[15:8]_0,MDM0_0,MDM1_0
tphy_WDS DQ and DM setup time for Write - 343 ps
tphy_WDH DQ and DM hold time for Write - 276 ps
tphy_RDS DQ setup time for Read - 337 ps
tphy_RDH DQ hold time for Read 588 - ps
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MDQ[23:16]_0,MDQ[31:24]_0,MDM2_0,MDM3_0
tphy_WDS DQ and DM setup time for Write - 343 ps
tphy_WDH DQ and DM hold time for Write - 276 ps
tphy_RDS DQ setup time for Read - 337 ps
tphy_RDH DQ hold time for Read 588 - ps
MDQ[7:0]_1, MDQ[15:8]_1,MDM0_1,MDM1_1
tphy_WDS DQ and DM setup time for Write - 343 ps
tphy_WDH DQ and DM hold time for Write - 276 ps
tphy_RDS DQ setup time for Read - 337 ps
tphy_RDH DQ hold time for Read 588 - ps
MDQ[23:16]_1, MDQ[31:24]_1,MDM2_1,MDM3_1
tphy_WDS DQ and DM setup time for Write - 343 ps
tphy_WDH DQ and DM hold time for Write - 276 ps
tphy_RDS DQ setup time for Read - 337 ps
tphy_RDH DQ hold time for Read 588 - ps
Table 2.29. : DDR Controller (DDR3-800) signal timing by SSTL15 mode
Signal Name Symbol DescriptionValue
UnitMin Max
MA*_0MBA*_0,MCKE*_0,MODT*_0, MXCAS*_0,MXCS*_0,MXRAS*_0,MXWE*_0
tphy_IS_CA Control and Address setup time - 958 ps
tphy_IH_CA Control and Address hold time - 1162 ps
MA*_1MBA*_1,MCKE*_1,MODT*_1, MXCAS*_1,MXCS*_1,MXRAS*_1,MXWE*_1
tphy_IS_CA Control and Address setup time - 908 ps
tphy_IH_CA Control and Address hold time - 1200 ps
MDQS0_0,MDQS1_0,MXDQS0_0,MXDQS1_0
tphy_CKDQS_min DQS output access time from CLK -371 - ps
tphy_CKDQS_max DQS output access time from CLK - 238 ps
tphy_RTT_Gate_min Round Trip time from CLK out to Read DQS -207 - ps
tphy_RTT_Gate_max Round Trip time from CLK out to Read DQS - 1282 ps
MDQS2_0,MDQS3_0,MXDQS2_0,MXDQS3_0
tphy_CKDQS_min DQS output access time from CLK -258 - ps
tphy_CKDQS_max DQS output access time from CLK - 341 ps
tphy_RTT_Gate_min Round Trip time from CLK out to Read DQS -65 - ps
tphy_RTT_Gate_max Round Trip time from CLK out to Read DQS - 1435 ps
Table 2.28. : DDR Controller(DDR3-1066) signal timing by SSTL15 mode (Continued)
Signal Name Symbol DescriptionValue
UnitMin Max
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MDQS0_1,MDQS1_1,MXDQS0_1,MXDQS1_1
tphy_CKDQS_min DQS output access time from CLK -354 - ps
tphy_CKDQS_max DQS output access time from CLK - 261 ps
tphy_RTT_Gate_min Round Trip time from CLK out to Read DQS -221 - ps
tphy_RTT_Gate_max Round Trip time from CLK out to Read DQS - 1259 ps
MDQS2_1,MDQS3_1,MXDQS2_1,MXDQS3_1
tphy_CKDQS_min DQS output access time from CLK -239 - ps
tphy_CKDQS_max DQS output access time from CLK - 377 ps
tphy_RTT_Gate_min Round Trip time from CLK out to Read DQS -104 - ps
tphy_RTT_Gate_max Round Trip time from CLK out to Read DQS - 1375 ps
MDQ[7:0]_0,MDQ[15:8]_0,MDM0_0,MDM1_0
tphy_WDS DQ and DM setup time for Write - 502 ps
tphy_WDH DQ and DM hold time for Write - 423 ps
tphy_RDS DQ setup time for Read - 474 ps
tphy_RDH DQ hold time for Read 731 - ps
MDQ[23:16]_0,MDQ[31:24]_0,MDM2_0,MDM3_0
tphy_WDS DQ and DM setup time for Write - 481 ps
tphy_WDH DQ and DM hold time for Write - 444 ps
tphy_RDS DQ setup time for Read - 474 ps
tphy_RDH DQ hold time for Read 731 - ps
MDQ[7:0]_1, MDQ[15:8]_1,MDM0_1,MDM1_1
tphy_WDS DQ and DM setup time for Write - 502 ps
tphy_WDH DQ and DM hold time for Write - 423 ps
tphy_RDS DQ setup time for Read - 474 ps
tphy_RDH DQ hold time for Read 731 - ps
MDQ[23:16]_1, MDQ[31:24]_1,MDM2_1,MDM3_1
tphy_WDS DQ and DM setup time for Write - 481 ps
tphy_WDH DQ and DM hold time for Write - 444 ps
tphy_RDS DQ setup time for Read - 474 ps
tphy_RDH DQ hold time for Read 731 - ps
Table 2.30. : DDR Controller(DDR3L-1066) signal timing by SSTL135 mode
Signal Name Symbol DescriptionValue
UnitMin Max
MA*_0MBA*_0,MCKE*_0,MODT*_0, MXCAS*_0,MXCS*_0,MXRAS*_0,MXWE*_0
tphy_IS_CA Control and Address setup time - 659 ps
tphy_IH_CA Control and Address hold time - 851 ps
Table 2.29. : DDR Controller (DDR3-800) signal timing by SSTL15 mode (Continued)
Signal Name Symbol DescriptionValue
UnitMin Max
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MA*_1MBA*_1,MCKE*_1,MODT*_1, MXCAS*_1,MXCS*_1,MXRAS*_1,MXWE*_1
tphy_IS_CA Control and Address setup time - 609 ps
tphy_IH_CA Control and Address hold time - 891 ps
MDQS0_0,MDQS1_0,MXDQS0_0,MXDQS1_0
tphy_CKDQS_min DQS output access time from CLK -377 - ps
tphy_CKDQS_max DQS output access time from CLK - 191 ps
tphy_RTT_Gate_min Round Trip time from CLK out to Read DQS 114 - ps
tphy_RTT_Gate_max Round Trip time from CLK out to Read DQS - 977 ps
MDQS2_0,MDQS3_0,MXDQS2_0,MXDQS3_0
tphy_CKDQS_min DQS output access time from CLK -235 - ps
tphy_CKDQS_max DQS output access time from CLK - 324 ps
tphy_RTT_Gate_min Round Trip time from CLK out to Read DQS 246 - ps
tphy_RTT_Gate_max Round Trip time from CLK out to Read DQS - 1120 ps
MDQS0_1,MDQS1_1,MXDQS0_1,MXDQS1_1
tphy_CKDQS_min DQS output access time from CLK -360 - ps
tphy_CKDQS_max DQS output access time from CLK - 214 ps
tphy_RTT_Gate_min Round Trip time from CLK out to Read DQS 81 - ps
tphy_RTT_Gate_max Round Trip time from CLK out to Read DQS - 935 ps
MDQS2_1,MDQS3_1,MXDQS2_1,MXDQS3_1
tphy_CKDQS_min DQS output access time from CLK -245 - ps
tphy_CKDQS_max DQS output access time from CLK - 330 ps
tphy_RTT_Gate_min Round Trip time from CLK out to Read DQS 227 - ps
tphy_RTT_Gate_max Round Trip time from CLK out to Read DQS - 1079 ps
MDQ[7:0]_0,MDQ[15:8]_0,MDM0_0,MDM1_0
tphy_WDS DQ and DM setup time for Write - 338 ps
tphy_WDH DQ and DM hold time for Write - 273 ps
tphy_RDS DQ setup time for Read - 325 ps
tphy_RDH DQ hold time for Read 599 - ps
MDQ[23:16]_0,MDQ[31:24]_0,MDM2_0,MDM3_0
tphy_WDS DQ and DM setup time for Write - 322 ps
tphy_WDH DQ and DM hold time for Write - 292 ps
tphy_RDS DQ setup time for Read - 325 ps
tphy_RDH DQ hold time for Read 599 - ps
MDQ[7:0]_1,MDQ[15:8]_1,MDM0_1,MDM1_1
tphy_WDS DQ and DM setup time for Write - 338 ps
tphy_WDH DQ and DM hold time for Write - 273 ps
tphy_RDS DQ setup time for Read - 325 ps
tphy_RDH DQ hold time for Read 599 - ps
Table 2.30. : DDR Controller(DDR3L-1066) signal timing by SSTL135 mode (Continued)
Signal Name Symbol DescriptionValue
UnitMin Max
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MDQ[23:16]_1,MDQ[31:24]_1,MDM2_1,MDM3_1
tphy_WDS DQ and DM setup time for Write - 338 ps
tphy_WDH DQ and DM hold time for Write - 273 ps
tphy_RDS DQ setup time for Read - 325 ps
tphy_RDH DQ hold time for Read 599 - ps
Table 2.31. : DDR Controller(DDR3L-800) signal timing by SSTL135 mode
Signal Name Symbol DescriptionValue
UnitMin Max
MA*_0MBA*_0,MCKE*_0,MODT*_0, MXCAS*_0,MXCS*_0,MXRAS*_0,MXWE*_0
tphy_IS_CA Control and Address setup time - 956 ps
tphy_IH_CA Control and Address hold time - 1156 ps
MA*_1MBA*_1,MCKE*_1,MODT*_1, MXCAS*_1,MXCS*_1,MXRAS*_1,MXWE*_1
tphy_IS_CA Control and Address setup time - 906 ps
tphy_IH_CA Control and Address hold time - 1195 ps
MDQS0_0,MDQS1_0,MXDQS0_0,MXDQS1_0
tphy_CKDQS_min DQS output access time from CLK -370 - ps
tphy_CKDQS_max DQS output access time from CLK - 242 ps
tphy_RTT_Gate_min Round Trip time from CLK out to Read DQS -206 - ps
tphy_RTT_Gate_max Round Trip time from CLK out to Read DQS - 1239 ps
MDQS2_0,MDQS3_0,MXDQS2_0,MXDQS3_0
tphy_CKDQS_min DQS output access time from CLK -257 - ps
tphy_CKDQS_max DQS output access time from CLK - 345 ps
tphy_RTT_Gate_min Round Trip time from CLK out to Read DQS -64 - ps
tphy_RTT_Gate_max Round Trip time from CLK out to Read DQS - 1391 ps
MDQS0_1,MDQS1_1,MXDQS0_1,MXDQS1_1
tphy_CKDQS_min DQS output access time from CLK -392 - ps
tphy_CKDQS_max DQS output access time from CLK - 226 ps
tphy_RTT_Gate_min Round Trip time from CLK out to Read DQS -180 - ps
tphy_RTT_Gate_max Round Trip time from CLK out to Read DQS - 1255 ps
MDQS2_1,MDQS3_1,MXDQS2_1,MXDQS3_1
tphy_CKDQS_min DQS output access time from CLK -238 - ps
tphy_CKDQS_max DQS output access time from CLK - 381 ps
tphy_RTT_Gate_min Round Trip time from CLK out to Read DQS -64 - ps
tphy_RTT_Gate_max Round Trip time from CLK out to Read DQS - 1370 ps
Table 2.30. : DDR Controller(DDR3L-1066) signal timing by SSTL135 mode (Continued)
Signal Name Symbol DescriptionValue
UnitMin Max
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MDQ[7:0]_0,MDQ[15:8]_0,MDM0_0,MDM1_0
tphy_WDS DQ and DM setup time for Write - 497 ps
tphy_WDH DQ and DM hold time for Write - 419 ps
tphy_RDS DQ setup time for Read - 462 ps
tphy_RDH DQ hold time for Read 742 - ps
MDQ[23:16]_0,MDQ[31:24]_0,MDM2_0,MDM3_0
tphy_WDS DQ and DM setup time for Write - 478 ps
tphy_WDH DQ and DM hold time for Write - 441 ps
tphy_RDS DQ setup time for Read - 462 ps
tphy_RDH DQ hold time for Read 742 - ps
MDQ[7:0]_1, MDQ[15:8]_1,MDM0_1,MDM1_1
tphy_WDS DQ and DM setup time for Write - 497 ps
tphy_WDH DQ and DM hold time for Write - 419 ps
tphy_RDS DQ setup time for Read - 462 ps
tphy_RDH DQ hold time for Read 742 - ps
MDQ[23:16]_1, MDQ[31:24]_1,MDM2_1,MDM3_1
tphy_WDS DQ and DM setup time for Write - 478 ps
tphy_WDH DQ and DM hold time for Write - 441 ps
tphy_RDS DQ setup time for Read - 462 ps
tphy_RDH DQ hold time for Read 742 - ps
Table 2.31. : DDR Controller(DDR3L-800) signal timing by SSTL135 mode (Continued)
Signal Name Symbol DescriptionValue
UnitMin Max
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Figure 2.18. : MB86R24/26 tphy_IS_CA/tphy_IH_CA timing
*1) DRAM SPEC.tIS/tIH changes by derating.Measure the slew rate of the simulation waveform at the DRAM and derate the DRAM spec accordingly.
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Figure 2.19. : MB86R24/26 tphy_CKDQS timing
*1) tphy_CKDQS defines positive when DQS arrival is later than CLK.*2) Skew of CK-DQS can be adjusted by the MCR_64 and MCR_65 register (ITXDQS_SFT[7:0]). AC SPEC.(tphy_CKDQS) changes according as the resister setting.
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Figure 2.20. : MB86R24/26 tphy_WDS/tphy_WDH timing
*1) DRAM SPEC.tDS/tDH changes by derating. Measure slew rate of the simulation waveform at DRAM on the customer PCB, and derate the DRAM spec.*2) Skew of DQS-DQ(WRITE) can be adjusted by the REG_TDS0-3 register (ITXDQ_SFT[7:0]). AC SPEC.(tphy_WDS/tphy_WDH) changes according as the register setting.
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Figure 2.21. : MB86R24/26 tphy_RDS/tphy_RDH timing
*1) AC SPEC.(tphy_RDS/tphy_RDH) does not depend on input slew rate and be constant. (Derating like tDS/tDH of DRAM SPEC is unnecessary.)*2) Use tQHmin = tCK(avg) * 0.38. Input clk jitter is already derated in AC SPEC.(tphy_RDH), customer does notneed to consider.*3) Skew of DQS-DQ(READ) can be adjusted by the REG_TDS0-3 register (IRXDQS_SFT[5:0]). AC SPEC.(tphy_RDS/tphy_RDH) changes according as the register setting.
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Figure 2.22. : MB86R24/26 tphy_RTT_Gate timing
*1) Apply DRAM SPEC(max)=max(tLZmax, tDQSCKmax) and DRAM SPEC(min)= tDQSCKmin*2) tphy_RTT_Gate can be adjusted by the MCR_73, MCR_76, MCR_80 and MCR_83 register (IRXRTT_SFT[7:0]). AC SPEC.(tphy_RTT_Gate) changes according as the resister setting.
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2.7.3. Display Controller Unit Signal Timing
2.7.3.1. Clock
2.7.3.2. Input Signal
1. Application only in case of PLL synchronous mode (CKS = 0)(clock output from internal standard clock= PLL)
2. Application only in case of DCLKI synchronous mode (CKS = 1)(standard clock = DCLKI)
Table 2.32. : AC timing of video interface clock signal
Signal Symbol DescriptionValue
UnitMin Typ Max
DISPnCLKI
Fdclki DCLKI frequency - - 133 MHz
Thdclki DCLKI H width 5 - - ns
Tldclki DCLKI L width 5 - - ns
DCLK (internal) Tldclk DCLK frequency (*1) - - 133 MHz
DISPnCLKO Fdclko DCLKO frequency - - 133 MHz
DISPnCLKO Thdclko DCLKO H width typ-0.7 *4 typ+0.7 ns*1: The internal display clock of PLL synchronous mode is generated with internal PLL and display clock prescaler. *2: DCLKI or PLL internal display clock is output. *3: "m" of DISPm shows the figure. *4: H pulse width of DISPnCLKO is described as follow. Thdclko(typ) = (PLL cycle time)*n ; dual edge mode Thdclko(typ) = (PLL cycle time)*n/2; single edge mode, n is even number Thdclko(typ) = (PLL cycle time)*(n-1)/2; single edge mode, n is odd number Thdclko(typ) = Thdclki; DISPnCLKI is used as DCLK source n is divide ratio defined by SC field of DCLKConfig register, i.e, n = SC+1 PLL cycle time varies if SSCG is used but does not get shorter than standard cycle time*5 For faster clock operation, setup time of output data is dominating.
Table 2.33. : AC timing of video interface input signal(1)
Signal Symbol DescriptionValue
UnitMin Typ Max
DISPnHSYNC (i) Twhsync HSYNC input pulse width 3.0 - - Clock
DISPnVSYNC (i) Twvsync VSYNC input pulse width 1 - - HSYNC
Table 2.34. : AC timing of video interface input signal(2)
Signal Symbol DescriptionValue
UnitMin Typ Max
DISPnHSYNC (i)
Twhsync HSYNC input pulse width 3.0 - - Clock
Tshsync HSYNC Input setup time 6.0 - - ns
Thhsync HSYNC Input hold time 1.0 - - ns
DISPnVSYNC (i) Twvsync VSYNC input pulse width 1 - - HSYNC
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Figure 2.23. : Display input signal timing
2.7.3.3. Output Signal
Table 2.35. : AC timing of video interface output signal
Signal Symbol Description ConditionValue
UnitMin Typ Max
DISPLAY CONTROLLER 0 (clone mode =1 1)
DISP1R[7:0],DISP1G[7:0], DISP1B[7:0]DISP1HSYNC(oDISP1VSYNC(o)DISP1DE(o)DISP1CSYNCDISP1GV
Tdrgb0 RGB output delay time
Single edge mode 0.3 - 4.2 ns
Dual edge mode 0.3 - 4.2 ns
Delay mode 3) 0.4 - 4.2 ns
DISPLAY CONTROLLER 1
DISP1R[7:0],DISP1G[7:0], DISP1B[7:0]DISP1HSYNC(o)DISP1VSYNC(o)DISP1DE(o)DISP1CSYNCDISP1GV
Tdrgb1 RGB output delay time
Single edge mode 0.4 - 4.3 ns
Dual edge mode 0.4 - 4.3 ns
Delay mode 3) 0.4 - 4.3 ns
Dual pixel mode 0.4 - 4.3 ns
DISPLAY CONTROLLER 1 (SEERIS_SEL=1 2))
Twvsync
DISPn CLKI
DISPn HSYNC (i)
Tshsync Thhsync
Thdclki Tldclki1/Fdclki
DISPn VSYNC (i)
Tsvsync Thvsync
Twhsync
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Figure 2.24. : Display output signal timing
The AC-characteristic is not defined about the analog signal.
DISP2R[7:0],DISP2G[7:0], DISP2B[7:0]DISP2HSYNC(o)DISP2VSYNC(o)DISP2DE(o)DISP2GV
Tdrgb2 RGB output delay time
Single edge mode 0.4 - 4.3 ns
Dual edge mode 0.4 - 4.3 ns
Delay mode 3) 0.4 4.3 ns
Dual edge mode 0.4 - 4.3 nsSingle edge mode : DCK edge =0Dual edge mode : DCKedge = 1Dual pixel mode : DPIX = 1Delay mode : DCKdel > 0*1 Clone mode=1: Display0 output. CCNT_GLBLCTL Register setting*2 SEERIS_DEL=1: Display1 output. CCNT_SEERIS_OUT Register setting.*3 Digital delay is added to this delay value*4 When the holding time is insufficient, reversing the DCLKO clock is recommended.
Table 2.35. : AC timing of video interface output signal
Signal Symbol Description ConditionValue
UnitMin Typ Max
DISPnGV
1/Fdclko
Tddrgb
Tdhsync
Tdvsync
Tdcsync
Tdgv
DISPnCLKO
DISPnCLKO(inverted)
DISPnR[7:0]DISPnG[7:0]DISPnB[7:0]
DISPnHSYNC (o)
DISPnVSYNC (o)
DISPnCSYNC
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2.7.3.4. TCON Active Display Timing DISP1 Interface
Note: If TCON is not used, please refer to Section 2.7.3.3 as specs of DISPLAY1.
In Duty cycle is 50, Clock setting of Display1 should be frequency divide by even number. If clock setting ofDisplay1 is frequency divide by odd number, duty cycle is not 50.For example:800/9 = 88.88MHz. High period 5/955.6%, Low period 4/944.4%
Figure 2.25. : TTL operation output timing (1)
Table 2.36. : AC timing of tcon output signal
Signal Symbol DescriptionValue
Unit ConditionMin Typ Max
TCON_R0-7,TCON_G0-7, TCON_B0-7
DISPSU Setup time 2.5 - - ns C_L=20pF, Delay[i]=0
DISPHD Hold time 2.5 - - ns C_L=20pF, Delay[i]=0
TCON_CLKO
f_TTLCK Frequency - - 88 MHz
t_TTLCK Period 11.25 - - ns
TTLCKH High Period 5.625 - - ns C_L=20pF
TTLCKL Low Period 5.625 - - ns C_L=20pF
Duty cycle - 50 - %
t_rise/fall Rise/Fall Time - - 1.0 ns
TCON_TSIG0-11TSIGSU Setup time 2.5 - - ns C_L=20pF, SSWITCH[i]=0
TSIGHD Hold time 2.5 - - ns C_L=20pF, SSWITCH[i]=0
TTLCK (pin DISP[j])Register DIR_Pin_ctrl[j].Delay=0
TTLCKH TTLCKL
50%
TTLDAT (pins DISP[i])Registers DIR_Pin_ctrl[i].Delay=0
DISPHDDISPSU
Pins TSIG[i]Register Dir_SSwitch.SSwitch =0
TSIGHDTSIGSU
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Figure 2.26. : TTL operation output timing (2)
TTLCKH TTLCKL
50%
TTLDAT (pins DISP[i])Registers DIR_Pin_ctrl[i].Delay=0
DISPHDDISPSU
Pins TSIG[i]Register Dir_SSwitch.SSwitch =0
TSIGHDTSIGSU
TTLCK (pin DISP[j])Register DIR_Pin_ctrl[j].Delay=0
Register DIR_Pin_Ctrl[j].Polarity=1
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2.7.4. FPD Unit Signal Timing
2.7.4.1. Output Signal
Figure 2.27. : FPD output signal timing
Signal Symbol DescriptionValue
UnitMin. Typ. Max.
EXPnEXNn
Fdout Output data rate 140 - 931 Mbps
Tskew Output data skew -0.2 - 0.2 ns
EXP5,EXN5(ch0)EXP4,EXN4(ch1)
(Differential)
EXP9,EXN9(ch0)EXP3,EXN3(ch1)
EXP8,EXN8(ch0)EXP2,EXN2(ch1)
EXP7,EXN7(ch0)EXP1,EXN1(ch1)
EXP6,EXN6(ch0)EXP0,EXN0(ch1)
G0 R5 R4 R3 R2 R1 R0
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