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10CS 33 LOGIC DESIGN UNIT – 3 Data Processing Circuits
Page 1
Data-Processing Circuits
Objectives
• Design of multiplexer circuits
• Discuss multiplexer applications
• Realization of higher order multiplexers using lower orders (multiplexer trees)
Introduction
Data-processing circuits are logic circuits that process binary data. Such circuits may be multiplexers,
demultiplexers, encoder, decoder, EX-OR gates. First we consider multiplexers.
Multiplexer
Multiplex means many into one. In digital computer networks, multiplexing is a method by which
multiple digital data streams are combined into one signal over a shared medium. A digital circuit that
performs the multiplexing of digital signals is called a multiplexer (or MUX in short). Multiplexer is a
combinational logic circuit that can select one of many inputs. Multiplexer is also called a data selector.
A simple 2-to-1 multiplexer block diagram and the switch equivalent circuit are as shown:
It has two inputs but only one output. By suitable control input or select input (sel) we can steer any
input to the output.
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The general multiplexer block diagram is as shown below:
Design of 4-to-1 Multiplexer
The 4-to-1 multiplexer has four data inputs.
control inputs. The block diagram is as shown below:
The truth table describing the behavior of the 4
10CS 33 LOGIC DESIGN UNIT – 3 Data Processing Circuits
The general multiplexer block diagram is as shown below:
1 multiplexer has four data inputs. To steer the four data inputs to the output we need two
am is as shown below:
The truth table describing the behavior of the 4-to-1 multiplexer is as shown below:
Control Inputs Output
A B Y
0 0 D0
0 1 D1
1 0 D2
1 1 D3
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to the output we need two
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From the truth table we obtain the logic equation
Y = A’B’D0 + A’BD1 + AB’D2 + ABD
The equation cannot be further simplified
The 74150
The 74150 is a 16-to-1 TTL multiplexer
disables or enables the multiplexer. If
The block diagram is as shown below:
The 74151
The 74151 is an 8-to-1 TTL multiplexer
10CS 33 LOGIC DESIGN UNIT – 3 Data Processing Circuits
From the truth table we obtain the logic equation
+ ABD3
The equation cannot be further simplified. The logic circuit realization is as shown below:
Y = A’B’D0 + A’BD1 + AB’D
TTL multiplexer. It has active low output. It has a STROBE, an input signal that
. If STROBE = 0, MUX is enabled and if STROBE = 1, MUX is disabled
The block diagram is as shown below:
1 TTL multiplexer. It has complementary outputs.
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. The logic circuit realization is as shown below:
+ AB’D2 + ABD3
It has a STROBE, an input signal that
STROBE = 1, MUX is disabled.
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The block diagram is as shown below:
The 74153
The 74153 is a dual 4-to-1 TTL multiplexer
multiplexer and common select lines
The 74157
The 74157 is a quad 2-to-1 TTL multiplexer IC
10CS 33 LOGIC DESIGN UNIT – 3 Data Processing Circuits
low:
1 TTL multiplexer. It has non-inverting outputs. It has separate enable for each
ommon select lines.
1 TTL multiplexer IC. The block diagram is as shown below:
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eparate enable for each
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Multiplexer Applications
Multiplexer’s important application is in sharing the circuits, ports, devices and resources
can be used in design of combinational logic circuits
Nibble Multiplexer
Nibble Multiplexer is used when we want to
nibbles, A3A2A1A0 and B3B2B1B0. The 74157 IC is used to realize the nibble multiplexer as shown below:
The control signal SELECT determines which nibble is transmitted to output
When SELECT is low, the left nibble is steered to the o
Y3Y2Y1Y0 = A3A2A1A0
When SELECT is high, the right nibble is steered to the output.
Y3Y2Y1Y0 = B3B2B1B0
Multiplexer Logic
We can use multiplexer to realize a given
because a 2n-to-1 multiplexer can be used to design solution for any n
Example 1:
Realize Y = A’B + B’C’ + ABC using an 8
Solution:
First we express Y in canonical SOP form
10CS 33 LOGIC DESIGN UNIT – 3 Data Processing Circuits
Multiplexer’s important application is in sharing the circuits, ports, devices and resources
can be used in design of combinational logic circuits.
Nibble Multiplexer is used when we want to select one of two input nibbles. Consider the two input
The 74157 IC is used to realize the nibble multiplexer as shown below:
The control signal SELECT determines which nibble is transmitted to output. STROBE input is
When SELECT is low, the left nibble is steered to the output. We have,
nibble is steered to the output. We have,
We can use multiplexer to realize a given Boolean equation. Multiplexer is called universal logic circuit
1 multiplexer can be used to design solution for any n-variable truth table
using an 8-to-1 multiplexer
in canonical SOP form
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Multiplexer’s important application is in sharing the circuits, ports, devices and resources. Multiplexers
. Consider the two input
The 74157 IC is used to realize the nibble multiplexer as shown below:
STROBE input is made 0.
Multiplexer is called universal logic circuit
variable truth table.
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Y = A’B + B’C’ + ABC
= A’B.1 + 1.B’C’ + ABC
= A’B.(C’ + C) + (A’ + A).B’C’ + ABC
= A’BC’ + A’BC + A’B’C’ + AB’C’ + ABC
= Σ m (2, 3, 0, 4, 7)
= Σ m (0, 2, 3, 4, 7)
Consider the 8-to-1 multiplexer truth table as shown below:
A B C Y
0 0 0 D0
0 0 1 D1
0 1 0 D2
0 1 1 D3
1 0 0 D4
1 0 1 D5
1 1 0 D6
1 1 1 D7
From the truth table we have,
Y = A’B’C’D0 + A’B’CD1 + A’BC’D2 + A’BCD3 + AB’C’D4 + AB’CD5 + ABC’D6 + ABCD7
Y = moD0 + m1D1 + m2D2 + m3D3 + m4D4 + m5D5 + m6D6 + m7D7
The given equation is Y = f(A, B, C) = Σ m (0, 2, 3, 4, 7). The variables A, B, & C are used as select inputs.
Comparing multiplexer output expression with the given logic equation in canonical SOP form we find by
substituting D0 = D2 = D3 = D4 = D7 = 1 and D1 = D5 = D6 = 0 we have the realization as shown.
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The truth table for the given logic equation is shown below:
Example 2:
Realize Y = A’B + B’C’ + ABC using 4-
Solution:
We consider variables A and B as selector
input. Given logic equation Y = A’B + B’C’ + ABC in canonical form
is as shown.
10CS 33 LOGIC DESIGN UNIT – 3 Data Processing Circuits
The truth table for the given logic equation is shown below:
A B C Y
0 0 0 1
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
-to-1 multiplexer.
as selector inputs in 4-to-1 multiplexer and variable C in given as data
Given logic equation Y = A’B + B’C’ + ABC in canonical form is Y= Σ m (0, 2, 3, 4, 7)
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1 multiplexer and variable C in given as data
m (0, 2, 3, 4, 7). The truth table
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A B C Y
0 0 0 1
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
Similar to procedure adopted in entered variable map, output Y is written in terms of variable C.
A B C Y Y
0 0 0 1 C’
0 0 1 0
0 1 0 1 1
0 1 1 1
1 0 0 1 C’
1 0 1 0
1 1 0 0 C
1 1 1 1
Comparing with equation of 4-to-1 multiplexer we see
D0 = C’
D1 = 1
D2 = C’
D3 = C
generate the given logic function.
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The given logic equation is realized using the 4
Example 3:
Realize Y = Σ m(0, 2, 3, 4 ,5, 8, 9, 10, 11, 12, 13, 15) using 8
Solution:
The truth table for the given expression is as shown below:
10CS 33 LOGIC DESIGN UNIT – 3 Data Processing Circuits
The given logic equation is realized using the 4-to-1 multiplexer as shown below:
A B Y
0 0 C’
0 1 1
1 0 C’
1 1 C
m(0, 2, 3, 4 ,5, 8, 9, 10, 11, 12, 13, 15) using 8-to-1 multiplexer.
The truth table for the given expression is as shown below:
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The logic expression is realized using 8
Multiplexer Trees
A number of m-to-1 multiplexers can be arranged in tree topology to obtain a bigger n
(n > m).
Example 1:
Design a 4-to-1 multiplexer using 2
Solution:
The 2-to-1 multiplexer truth table is as
Two units of 2-to-1 multiplexers are used together to realize 4 inputs, and another unit of 2
multiplexer is used to steer the inputs to a single output. The multiplexer tree is realized as shown:
10CS 33 LOGIC DESIGN UNIT – 3 Data Processing Circuits
The logic expression is realized using 8-to-1 multiplexer as shown below:
1 multiplexers can be arranged in tree topology to obtain a bigger n
1 multiplexer using 2-to-1 multiplexers.
1 multiplexer truth table is as shown:
1 multiplexers are used together to realize 4 inputs, and another unit of 2
multiplexer is used to steer the inputs to a single output. The multiplexer tree is realized as shown:
A B Y
0 0 D0
0 1 D1
1 0 D2
1 1 D3
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-to-1 multiplexer
1 multiplexers are used together to realize 4 inputs, and another unit of 2-to-1
multiplexer is used to steer the inputs to a single output. The multiplexer tree is realized as shown:
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Example 2:
Design a 32-to-1 multiplexer using two 16
Solution:
Questions
1. What is a multiplexer? Design 4
2. Implement the given Boolean function by using
f(A, B, C, D) = ∑m(0, 1, 3, 5, 7, 11, 12, 13, 14)
10CS 33 LOGIC DESIGN UNIT – 3 Data Processing Circuits
1 multiplexer using two 16-to-1 multiplexers and one 2-to-1 multiplexer
1. What is a multiplexer? Design 4-to-1 multiplexer and implement using gates.
2. Implement the given Boolean function by using 8:1 multiplexer.
∑m(0, 1, 3, 5, 7, 11, 12, 13, 14)
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1 multiplexer.
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3. Realize the Boolean expression f(w, x, y, z) = ∑m(4, 6, 7, 8, 10, 12, 15) using a 4 to 1 line multiplexer
and external gates.
4. Write the truth table of a 4-bit Binary to Gray code converter and realize the same using four 74151
ICs (8-to-1 multiplexer).
5. Show how two 1-to-16 demultiplexers can be connected to get a 1-to-32 demultiplexer.
6. Design a 32-to-1 multiplexer using two 16-to-1 multiplexer and one 2-to-1 multiplexer.
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Data Processing Circuits
Objectives
• Design of demultiplexers and demultiplexer t
• Understanding decoders
• Combinational logic design using d
• Understanding seven-segment d
Demultiplexers
Demultiplex means one into many.
input and many outputs. By applying control signals, we can steer the input signal to one of the output
lines. The block diagram of a simple
is as shown below:
Consider the block diagram of the general
33 LOGIC DESIGN UNIT – 3 Data Processing Circuits
Data Processing Circuits
and demultiplexer trees
Combinational logic design using decoders
segment decoders and encoders
. A demultiplexer (DEMUX) is a combinational logic circuit with one
By applying control signals, we can steer the input signal to one of the output
The block diagram of a simple 1-to-2 demultiplexer block diagram and its switch equivalent circuit
general demultiplexer as shown below:
3 Data Processing Circuits
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A demultiplexer (DEMUX) is a combinational logic circuit with one
By applying control signals, we can steer the input signal to one of the output
block diagram and its switch equivalent circuit
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It has one input signal, ‘m’ control input or select signals
Design of 1-to-2 Demultiplexer
The truth table of 1-to-2 demultiplexer
The output expressions are Y0 = D.A’ and
Demultiplexer ICs
The popular demultiplexer TTL ICs are listed below. They can also be used as decoders.
IC No.
74154
74138
74155
The TTL IC 74154
The 74154 is a 1-to-16 demultiplexer / decoder
must be low to activate the IC. Data is inverted at the input and again on any output
inversion, data passes through the circuit unchanged
33 LOGIC DESIGN UNIT – 3 Data Processing Circuits
‘m’ control input or select signals, and ‘n’ output signals (n <= 2
2 demultiplexer is as shown below:
Data
input
Select
input Outputs
D A Y0 Y1
0 0 0 0
1 0 1 0
0 1 0 0
1 1 0 1
= D.A’ and Y1 = A.D and the logic circuit realization is as shown below:
The popular demultiplexer TTL ICs are listed below. They can also be used as decoders.
IC No. DEMUX Type Decoder Type
74154 1-to-16 4-to-16
74138 1-to-8 3-to-8
74155 1-to-4 2-to-4
16 demultiplexer / decoder. G1 is used as data input. G2 is used as strobe input and
Data is inverted at the input and again on any output
through the circuit unchanged.
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(n <= 2m).
and the logic circuit realization is as shown below:
The popular demultiplexer TTL ICs are listed below. They can also be used as decoders.
G2 is used as strobe input and
Data is inverted at the input and again on any output. With double
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The pin out diagram is as shown:
Demultiplexer Tree
Example 1:
Realize 1-to-32 demultiplexer using two 1
Solution:
1-to-32 demux has 5 select variables A, B,C, D, E
32 outputs. If A = 0, the top IC is chosen
BCDE, data is directed to one of the outputs
33 LOGIC DESIGN UNIT – 3 Data Processing Circuits
using two 1-to-16 demultiplexers
32 demux has 5 select variables A, B,C, D, E. We use two units of 1-to-16 demultiplexers to obtain
If A = 0, the top IC is chosen, and if A = 1, the bottom IC is chosen. Depending on value of
BCDE, data is directed to one of the outputs. The 1-to-32 demultiplexer is realized as sh
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16 demultiplexers to obtain
Depending on value of
32 demultiplexer is realized as shown below:
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Decoder
Demultiplexer can be used as a decoder
logic 1. The decoder inputs are given to the control or select lines
one of the output lines. 1-to-n demult
lines will be high.
The block diagram of 1-of-n decoder is as shown below:
1-of-16 Decoder IC
74154 IC can be used as 1-of-16 decoder
block diagram is as shown below:
33 LOGIC DESIGN UNIT – 3 Data Processing Circuits
Demultiplexer can be used as a decoder. The data input of the demultiplexer is always connected to
The decoder inputs are given to the control or select lines. The inputs are decoded by activating
n demultiplexer converted in to 1-of-n decoder. Only one of the ‘n’ output
n decoder is as shown below:
16 decoder. 1-of-16 decoder is also called 4 line-to-16 line decoder
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The data input of the demultiplexer is always connected to
The inputs are decoded by activating
Only one of the ‘n’ output
16 line decoder. The
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Decoder Applications
Decoders can be used in combination logic circuit design
Example 1 :
Show how using a 3-to-8 decoder and multi
realized simultaneously:
f1(A, B, C) = Σ m(0, 4, 6)
f2(A, B, C) = Σ m(0, 5)
f3(A, B, C) = Σ m(1, 2, 3, 7)
Solution:
f1 = Σ m(0, 4, 6) = m0 + m4 + m6
f2 = Σ m(0, 5) = m0 + m5
f3 = Σ m(1, 2, 3, 7) = m1 + m2 + m3 + m7
We use OR gates to add the minterms.
Example 2:
Realize a full adder using 3-to-8 decoder IC 74138 and NAND gates
Solution:
The pin out diagram of the 3-to-8 decoder IC 74138 is as shown:
33 LOGIC DESIGN UNIT – 3 Data Processing Circuits
ombination logic circuit design.
8 decoder and multi-input OR gates following Boolean expressions can be
= m0 + m4 + m6
= m1 + m2 + m3 + m7
We use OR gates to add the minterms. The Boolean expressions are realized as shown below:
8 decoder IC 74138 and NAND gates.
8 decoder IC 74138 is as shown:
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input OR gates following Boolean expressions can be
The Boolean expressions are realized as shown below:
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The truth table of full adder is written as shown below:
Inputs Outputs
A B Ci S Co
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
The output expressions in SOP form:
S = Σ m(1, 2, 4, 7)
Co = Σ m(3, 5, 6, 7)
Full adder is realized as shown:
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BCD-to Decimal Decoders
BCD is an abbreviation for binary-coded decimal
number by its nibble equivalent.
Example: Decimal number 429 in its BCD form is
4
0100
The 7445 IC
The 7445 is a BCD to Decimal Decoder / Driver IC
diagram is as shown below:
33 LOGIC DESIGN UNIT – 3 Data Processing Circuits
coded decimal. The BCD code expresses each digit in a decimal
Decimal number 429 in its BCD form is
2 9
0100 0010 1001
Decoder / Driver IC. It is also called 1-of-10 decoder and its pin out
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The BCD code expresses each digit in a decimal
and its pin out
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Seven-Segment Decoders
A seven-segment decoder-driver is used to drive a seven
has 7 Light-emitting Diodes labeled a
It may be the common-anode or the common
display the decimal digits 0 -9.
The 7446 IC
The 7446 is a TTL IC decoder-driver that can be used to drive a common
It requires external current-limiting resistors
The 7448 IC
The 7446 is a TTL IC decoder-driver that can be used to drive a common
indicator. It has its own current-limiting resistors on the chip
Encoder
Encoding is the process of converting familiar numbers or symbols into some code format
is a digital circuit that receives digits (decimal, octal, etc.) or alphabets or special symbols and converts
them into their respective binary codes
input is converted to a coded binary output with ‘m’ bits
Encoder performs operation reverse to that of a
33 LOGIC DESIGN UNIT – 3 Data Processing Circuits
driver is used to drive a seven-segment indicator. A seven-segment indicator
labeled a – g as shown:
anode or the common-cathode type. By forward-biasing different LED’s, we can
driver that can be used to drive a common-anode seven-se
limiting resistors.
driver that can be used to drive a common-cathode seven
limiting resistors on the chip.
is the process of converting familiar numbers or symbols into some code format
is a digital circuit that receives digits (decimal, octal, etc.) or alphabets or special symbols and converts
them into their respective binary codes. It has ‘n’ input lines, only one of which is active
input is converted to a coded binary output with ‘m’ bits. Basically it is a combinational logic circuit
erforms operation reverse to that of a decoder. The block diagram is as shown:
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segment indicator
biasing different LED’s, we can
segment indicator.
cathode seven-segment
is the process of converting familiar numbers or symbols into some code format. An encoder
is a digital circuit that receives digits (decimal, octal, etc.) or alphabets or special symbols and converts
nput lines, only one of which is active. The active
Basically it is a combinational logic circuit.
The block diagram is as shown:
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Octal-to-Binary Encoder
It has 8 inputs, corresponding to 8 octal digits.
output. The truth table is as shown:
Inputs – Octal Digits
I0 I1
1 0
0 1
0 0
0 0
0 0
0 0
0 0
0 0
The output expressions are:
B0 = I1 + I3 + I5 + I7
B1 = I2 + I3 + I6 + I7
B2 = I4 + I5 + I6 + I7
The octal-to-binary encoder is realized as shown:
33 LOGIC DESIGN UNIT – 3 Data Processing Circuits
corresponding to 8 octal digits. It converts the selected octal digit into 3
The truth table is as shown:
Octal Digits Binary
Outputs
I2 I3 I4 I5 I6 I7 B2 B1 B0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 1
1 0 0 0 0 0 0 1 0
0 1 0 0 0 0 0 1 1
0 0 1 0 0 0 1 0 0
0 0 0 1 0 0 1 0 1
0 0 0 0 1 0 1 1 0
0 0 0 0 0 1 1 1 1
binary encoder is realized as shown:
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It converts the selected octal digit into 3-bit binary
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Decimal-to-BCD Encoder
It has 10 inputs, corresponding to 1
output.
The 74147 IC
The 74147 TTL IC is a decimal-to-BCD encoder
highest-order input.
Design of Priority Encoder
Example:
Design a priority encoder, the truth table of which is shown below. The order of priority for three inputs
is X1>X2>X3. However, if the encoder is not enabled by S or all the inputs are inactive the output
AB = 00.
33 LOGIC DESIGN UNIT – 3 Data Processing Circuits
It has 10 inputs, corresponding to 10 decimal digits. It converts the selected decimal digit into 4
BCD encoder. It is a priority encoder because it gives priority to the
Design a priority encoder, the truth table of which is shown below. The order of priority for three inputs
2>X3. However, if the encoder is not enabled by S or all the inputs are inactive the output
Inputs Outputs
S X1 X2 X3 A B
0 X X X 0 0
1 1 X X 0 1
1 0 1 X 1 0
1 0 0 1 1 1
1 0 0 0 0 0
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It converts the selected decimal digit into 4-bit BCD
It is a priority encoder because it gives priority to the
Design a priority encoder, the truth table of which is shown below. The order of priority for three inputs
2>X3. However, if the encoder is not enabled by S or all the inputs are inactive the output
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Simplification using K-map:
For output A:
We obtain A = SX1’X3’ + SX1’X2.
For output B:
We obtain B = SX1 + SX2’X3.
The output expressions are realized using logic gates.
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Questions
1. Define decoder. Draw logic diagram of 3:8 decoder with enable input.
2. Design a circuit that realizes the following two functions using a decoder and logic gates:
F1(A, B) = ∑m(0, 3) and F2(A, B) = ∑m(1, 2)
2. Define encoder. Design decimal-to-BCD encoder?
4. What is a priority encoder?
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Data Processing Circuits
Objectives
• Write the truth table for exclusive-OR (EX-OR) Gates
• Explain the purpose of Parity Checking
• Design Parity Generators and Checkers
• Show how a Magnitude Comparator works
• Design of n-bit Magnitude Comparator
• Describe a diode ROM
Exclusive-OR Gates
The exclusive-OR gate has a high output only when an odd number of inputs are high. The 2-input
Exclusive-OR (EX-OR) gate truth table is as shown:
Inputs Output
A B Y
0 0 0
0 1 1
1 0 1
1 1 0
The output expression is
Y = A’B + AB’.
The logic circuit of 2-input EX-OR gate is as shown:
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Its logic symbol is as shown:
The 7486 IC
The 7486 TTL IC is a quad 2-input Exclusive
performs the logic exclusive-OR function
Full Adder using EX-OR gates
The truth table of full adder is as shown:
10CS 33 LOGIC DESIGN UNIT – 3 Data Processing Circuits
input Exclusive-OR gate. It has four independent gates each of which
OR function. The pin out diagram is as shown below:
The truth table of full adder is as shown:
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It has four independent gates each of which
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Inputs
A
0
0
0
0
1
1
1
1
Full Adder Realizations:
a. Using 3-input EX-OR gate
b. Using 2-input EX-OR gates
Parity Generators and Checkers
In data communications, parity checking refers to the use of parity bits to check that data has been
transmitted accurately. The parity bit is added to every data unit that is transmitted
each data unit is set so that all bytes have either an odd number or even number of set bits
Even Parity
Even parity means an n-bit input has an even number of set bit (1’s)
Example:
Data unit 110011 has even parity. It has four set bits (1’s) i.e. even no. of 1’s
10CS 33 LOGIC DESIGN UNIT – 3 Data Processing Circuits
Inputs Outputs
A B Ci S Co
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Parity Generators and Checkers
In data communications, parity checking refers to the use of parity bits to check that data has been
parity bit is added to every data unit that is transmitted.
each data unit is set so that all bytes have either an odd number or even number of set bits
bit input has an even number of set bit (1’s).
It has four set bits (1’s) i.e. even no. of 1’s.
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In data communications, parity checking refers to the use of parity bits to check that data has been
. The parity bit for
each data unit is set so that all bytes have either an odd number or even number of set bits.
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Odd Parity
Odd parity means an n-bit input has an odd number of set bits (1’s)
Example:
Data unit 110001 has odd parity. It has three set bits (1’s) i.e. odd
Parity Checker
EX-OR gates are ideal for checking the parity of a binary number because they produce an output 1
when the input has an odd number of 1’s
Odd parity number
Even parity number
Parity Generation
An extra bit is added to the original binary number to produce a new binary number with even or odd
parity. The extra bit is called the parity bit
Odd-Parity Generation
10CS 33 LOGIC DESIGN UNIT – 3 Data Processing Circuits
bit input has an odd number of set bits (1’s).
It has three set bits (1’s) i.e. odd no. of 1’s.
OR gates are ideal for checking the parity of a binary number because they produce an output 1
when the input has an odd number of 1’s.
Input Output
Odd parity number 1
Even parity number 0
is added to the original binary number to produce a new binary number with even or odd
The extra bit is called the parity bit.
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OR gates are ideal for checking the parity of a binary number because they produce an output 1
is added to the original binary number to produce a new binary number with even or odd
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74180 Truth Table
Σ of 1’s at
A - H
Even
Odd
Even
Odd
X
X
Using a 74180 to generate odd parity
Σ of 1’s
at A -
Even
Odd
Odd parity generator
10CS 33 LOGIC DESIGN UNIT – 3 Data Processing Circuits
Inputs Outputs
of 1’s at
H EVEN ODD ΣEVEN ΣODD
Even 1 0 1 0
Odd 1 0 0 1
Even 0 1 0 1
Odd 0 1 1 0
1 1 0 0
0 0 1 1
odd parity
of 1’s
- H EVEN ODD ΣODD
Even 0 1
1
Odd 0
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Magnitude Comparator
Magnitude comparator compares magnitude of two n
three outputs: X > Y, X = Y, and X < Y
1-bit Magnitude Comparator
The truth table of 1-bit magnitude comparator is as shown below:
The output expressions are:
(X>Y) = XY’
(X=Y) = X’Y’ + XY = (X’Y + XY’)’
(X<Y) = X’Y
The logic circuit of 1-bit comparator is as shown:
10CS 33 LOGIC DESIGN UNIT – 3 Data Processing Circuits
Magnitude comparator compares magnitude of two n-bit numbers, say X & Y and activates one of the
X < Y. The logic diagram of n-bit comparator is as shown below:
bit magnitude comparator is as shown below:
Input Outputs
X Y X>Y X=Y X<Y
0 0 0 1 0
0 1 0 0 1
1 0 1 0 0
1 1 0 1 0
= (X’Y + XY’)’
bit comparator is as shown:
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say X & Y and activates one of the
bit comparator is as shown below:
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2-bit Magnitude Comparator
The truth table of 2-bit magnitude comparator is as shown below:
Inputs Outputs Inputs Outputs
X Y X>Y X=Y X<Y X Y X>Y X=Y X<Y
0 0 0 0 0 1 0 1 0 0 0 1 0 0
0 0 0 1 0 0 1 1 0 0 1 1 0 0
0 0 1 0 0 0 1 1 0 1 0 0 1 0
0 0 1 1 0 0 1 1 0 1 1 0 0 1
0 1 0 0 1 0 0 1 1 0 0 1 0 0
0 1 0 1 0 1 0 1 1 0 1 1 0 0
0 1 1 0 0 0 1 1 1 1 0 1 0 0
0 1 1 1 0 0 1 1 1 1 1 0 1 0
Comparator Design
We can obtain simplified logic equation for 4-variable expression and implement it using logic gates.
This procedure will become very complex when we try to design a comparator for 3-bits or more. The
solution steps are:
• Use a simple generic procedure
• Define
1. Bit-wise greater than terms (G):
G1 = X1Y1’ G0 = X0Y0’
2. Bit-wise less than terms (L):
L1 = X1’Y1 L0 = X0’Y0
3. Bit-wise equality terms (E):
E1 = (G1 + L1)’ E0 = (G0 + L0)’
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• From the definitions of G, L and E, we have
(X=Y) = E1E0 X= Y when both bits are equal
(X>Y) = G1 + E1G0 X>Y if MSB of X is higher than that of Y or if MSB is equal, then LSB of
X is higher
(X<Y) = L1 + E1L0 X<Y if MSB of X is lesser than that of Y or if MSB is equal, then LSB of X
is lesser
n-bit Magnitude Comparator
The output expressions are listed bel
(X=Y) = En-1En-2…. E0
(X>Y) = Gn-1 + En-1Gn-
(X<Y) = Ln-1 + En-1Ln-2
where Ei, Gi, Li represent for
respectively
The 7485 IC
It is a 4-bit magnitude comparator TTL IC. The functional diagram is as shown below:
The additional inputs (X=Y)in, (X>Y)
numbers having more than 4-bits. When 7485 is not used in cascade (X=Y)
10CS 33 LOGIC DESIGN UNIT – 3 Data Processing Circuits
From the definitions of G, L and E, we have 2-bit comparator output as follows:
X= Y when both bits are equal
Y if MSB of X is higher than that of Y or if MSB is equal, then LSB of
X is higher
X<Y if MSB of X is lesser than that of Y or if MSB is equal, then LSB of X
is lesser
The output expressions are listed below:
-2 + ……+ En-1En-2…E1G0
2 + ….. + En-1En-2…E1L0
represent for ith bit Xi = Yi, Xi > Yi, Xi < Yi terms
TTL IC. The functional diagram is as shown below:
, (X>Y)in, (X<Y)in are used to connect more than one 7485 to compare
When 7485 is not used in cascade (X=Y)in = 1, (X>Y) in
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bit comparator output as follows:
Y if MSB of X is higher than that of Y or if MSB is equal, then LSB of
X<Y if MSB of X is lesser than that of Y or if MSB is equal, then LSB of X
are used to connect more than one 7485 to compare
in = 0, (X<Y)in = 0.
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8-bit Comparator
The 8-bit comparator is realized using two 7485 ICs as shown below:
Read-Only Memory
A read-only memory (ROM) is used to store fixed data
be used to implement truth tables.
Diode ROM
We can build a diode circuit that stores binary numbers
Consider the binary numbers shown in the table:
10CS 33 LOGIC DESIGN UNIT – 3 Data Processing Circuits
bit comparator is realized using two 7485 ICs as shown below:
only memory (ROM) is used to store fixed data. ROM can be used as ‘look-up’ table
We can build a diode circuit that stores binary numbers.
Consider the binary numbers shown in the table:
Address Nibble
0 0111
1 1000
2 1011
3 1100
4 0110
5 1001
6 0011
7 0111
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up’ table. It can also
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The diode ROM matrix is as shown below:
When switch is
On-Chip Decoding
Switch that selects the addresses in diode ROM is replaced by on
3-to-8 decoder is used as shown:
10CS 33 LOGIC DESIGN UNIT – 3 Data Processing Circuits
The diode ROM matrix is as shown below:
When switch is
at position
Output
Y3Y2Y1Y0
0 0111
1 1000
2 1011
3 1100
4 0110
5 1001
6 0011
7 0111
Switch that selects the addresses in diode ROM is replaced by on-chip decoding. For this purpose a
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. For this purpose a
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TTL ROM ICs
Some popular TTL ROM ICs are listed below:
7488 256 bits organized as 32 x 8
74187 1024 bits organized as 256 x 4
74S370 2048 bits organized as 512 x 4
Generating Boolean Functions
Because the on-chip decoder of ROM produce all the fundamental products and the diodes OR some of
these products, diode ROM can be used to generate Boolean functions.
Questions
1. What is a parity generator?
2. Explain parity checking.
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3. What is a magnitude comparator? Write the truth table and circuit diagram of a 1-bit magnitude
comparator.
4. Write the (X>Y) output expression for a 4-bit comparator.
5. Draw a ROM diode circuit that produces the following output:
Y3 = A’BC’, Y2 = AB’C + ABC, Y1 = AB’C + A’BC + ABC, Y0 = A’BC’ + A’BC + ABC’ + ABC
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Data Processing Circuits
Objectives
• Review of Programmable ROM (PROM) and Erasable PROM (EPROM)
• Describe Programmable Logic Devices (PLDs): Programmable Array Logic (PAL) and
Programmable Logic Array (PLA)
Programmable ROMs
A programmable ROM (PROM) allows the user instead of the manufacturer to store the data. Mask
ROM (MROM) is a type of ROM whose contents are programmed by the IC manufacturer.
PROM
It is also called field programmable ROM (FPROM) or one-time programmable non-volatile memory
(OTP NVM).
PROM Programmer
User with the help of an instrument called a PROM programmer can program the PROM.
Programming a PROM
Consider the diode ROM. Originally, all diodes are connected at the cross points. Each of these diodes
has a fusible link ( a small fuse). The process of programming a PROM chip is called PROM ‘burning in’.
It involves burning or blowing out the fuses of selected memory cells whose value needs to be altered.
Programming like this is permanent. Data cannot be erased after it has been burned in.
The PROM programmer is first configured so that it contains the desired PROM burning instructions.
Next, the PROM chip is inserted into the ZIF socket. The PROM programmer sends a high voltage pulse
(12 to 21 V) only to the fuses belonging to memory cells whose value has to be changed from 1 to 0.
The high voltage causes the selected fuse to blow out or burn out. The burned out fuse no longer
connects a column to a row in a memory cell. The memory cell with a burned out fuse has a value 0
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Disadvantage of PROM
There is a limit on the number of input variables. Typically, PROMs have 8 inputs or less.
Drawing a PROM logic circuit
It is cumbersome to draw large PROM circuit with all the diodes. An alternative, streamlined drawing
procedure for PROMs is used. The simplified diagram of PROM is as shown:
Universal Logic Solution
PROM is an universal logic solution. The AND gates generate all the fundamental products and the user
can then OR these products as needed to generate any Boolean output.
Example:
Realize a full adder using a PROM.
Solution:
The truth table of the full adder is as shown:
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The full adder using PROM is realized as shown below:
Erasable PROMs
The erasable PROM (EPROM) uses metal
an array of floating-gate transistors individually programmed by an EPROM programmer
the memory requires selecting a given address and applying a higher voltage to the transistors
Erasing EPROM contents
10CS 33 LOGIC DESIGN UNIT – 3 Data Processing Circuits
Inputs Outputs
A B Ci S Co
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
The full adder using PROM is realized as shown below:
metal-oxide semiconductor field-effect transistors (MOSFETs)
gate transistors individually programmed by an EPROM programmer
the memory requires selecting a given address and applying a higher voltage to the transistors
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effect transistors (MOSFETs). It has
gate transistors individually programmed by an EPROM programmer. Storing data in
the memory requires selecting a given address and applying a higher voltage to the transistors.
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The stored data is erased by exposing the die to ultraviolet (UV) light. The UV light passes through the
quartz window in the IC package and releases all stored charges. The effect is to erase the stored
contents.
EPROM ICs
Some important EPROM IC types are listed below:
2716 16 K bits organized as 2048 x 8 (2 KB)
2732 32 K bits organized as 4096 x 8 (4 KB)
27256 256 K bits organized as 32768 x 8 (32 KB)
Importance of EPROM
The EPROM is useful in project development. The designer can modify the contents until the stored
data is perfect. When the design is finalized, the data can be burned into PROM.
Programmable Array Logic
Programmable Array Logic (PAL) is a programmable array of logic gates on a single chip. PAL is different
from a PROM. It has a programmable AND array and a fixed OR array. The structure of PAL is as shown
below:
Programming a PAL
With a PROM programmer, we can burn in the desired fundamental products, which are then ORed by
the fixed output connections.
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10CS 33 LOGIC DESIGN
Example:
Realize a full adder using PAL.
Solution:
The output expressions of a full adder are:
S = Σ m(1, 2, 4, 7)
Co = Σ m(3, 5, 6, 7)
Full adder is realized using PAL as shown below:
PAL ICs
Some important PAL IC types are listed below:
10H8 10 input and 8 output AND
16H2 6 input and 2 output AND
14L4 14 input and 4 output AND
10CS 33 LOGIC DESIGN UNIT – 3 Data Processing Circuits
The output expressions of a full adder are:
Full adder is realized using PAL as shown below:
IC types are listed below:
10 input and 8 output AND-OR
6 input and 2 output AND-OR
14 input and 4 output AND-OR-INVERT
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PAL - Pros and Cons
PALs are not an universal logic solution
ORed at the final outputs. But PALs have enough flexibility to produce all kinds of complicated logic
functions. PALs have the advantage of 16 inputs compared to the ty
Programmable Logic Arrays
In Programmable Logic Arrays (PLAs) both the AND array and the OR array are programmable
along with ROMs and PALs, are included in the more general classification of ICs called programmabl
logic devices (PLDs).
PLDs
The block diagrams of the three PLDs are as shown below:
10CS 33 LOGIC DESIGN UNIT – 3 Data Processing Circuits
universal logic solution. Only some of the fundamental products can be generated and
But PALs have enough flexibility to produce all kinds of complicated logic
PALs have the advantage of 16 inputs compared to the typical limit of 8 inputs for PROMs
Programmable Logic Arrays
In Programmable Logic Arrays (PLAs) both the AND array and the OR array are programmable
along with ROMs and PALs, are included in the more general classification of ICs called programmabl
The block diagrams of the three PLDs are as shown below:
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Only some of the fundamental products can be generated and
But PALs have enough flexibility to produce all kinds of complicated logic
pical limit of 8 inputs for PROMs.
In Programmable Logic Arrays (PLAs) both the AND array and the OR array are programmable. PLAs
along with ROMs and PALs, are included in the more general classification of ICs called programmable
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The structure of Programmable Logic Array
We can use PLA for combinational logic circuit design.
Example:
Realize a 7-segment decoder using PLA
Solution:
The truth table of 7-segment decoder is as shown:
10CS 33 LOGIC DESIGN UNIT – 3 Data Processing Circuits
Programmable Logic Array (PLA) is as shown below:
We can use PLA for combinational logic circuit design.
decoder using PLA.
segment decoder is as shown:
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BCD Input
A B
0 0
0 0
0 0
0 0
0 1
0 1
0 1
0 1
1 0
1 0
The 7-segment decoder is realized using PLA
10CS 33 LOGIC DESIGN UNIT – 3 Data Processing Circuits
BCD Input Outputs
C D a b c d e f g
0 0 1 1 1 1 1 1 0
0 1 0 1 1 0 0 0 0
1 0 1 1 0 1 1 0 1
1 1 1 1 1 1 0 0 1
0 0 0 1 1 0 0 1 1
0 1 1 0 1 1 0 1 1
1 0 1 0 1 1 1 1 1
1 1 1 1 1 0 0 0 0
0 0 1 1 1 1 1 1 1
0 1 1 1 1 0 0 1 1
using PLA as shown below:
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Questions
1. Mention different types of ROMs and explain each of them.
2. Implement the following Boolean functions using an appropriate PLA:
F1(A, B, C) = ∑m(0, 4, 7); F2 (A, B, C) = ∑m(4, 6).
3. What are the different types of PLDs? Implement the 7-segment decoder using PLA.
4. Implement the following function using PLA:
X = A’B’C + AB’C’ + B’C; Y = A’B’C + AB’C’; Z = B’C
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