consortial approach to electronics...

Consortial Approach to

Advance Electronics Packaging

Bob Pfahl, iNEMI

October 21, 2011

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Agenda

• Background

• Early Consortial Activities

• 2009 iNEMI and ITRS Packaging Roadmap

• Current iNEMI Consortial Research Activities

• Guidelines for Successful Consortial Projects

• Summary & Conclusions

1

Background

1950-1985

• Each Major Firm Developed their Own Complete Supply Chain

• Beam Leads and Gold Wire Bonding

• C3 Flip Chip Technology

• Tab Bonding

1950-85 Vertically Integrated Firms

3

Early Consortial Activities

1985-2009

• Matsushita recognized the potential of Tab Technology and made the

technology public

• 1983-1986

• Key step for industry adoption was developing reliability data

• Consortial activity at Sematech spurred the development of area array

packages

• 1994-1998

• SIA Roadmap (now ITRS) identified need in 1994

• iNEMI Developed low cost, high volume packaging technology for

handheld devices

• 1996-1999

• Needs were defined in the 1994 and 1996 iNEMI Roadmaps

• HDI project worked with board vendors to develop, qualify, and

confirm reliability

• Flip Chip project developed assembly processes and verified

reliability

• 2007 iNEMI Roadmap a Gap in Packaging Technology for SiP Packages

• Not enough OEM interest for a Consortial Approach

1985-2009 Early Consortial Activities

5

2009 iNEMI and ITRS Packaging

Roadmap

2009

2009-iNEMI and ITRS Packaging Roadmaps

• Recognized the More than Moore Model

• Acknowledged that System on Chip (SOC) and System

in Package (SIP) would continue into the future

• Recognized that functions would migrate from SIP to

SOC

• Identified that there were a number of technologies used

for SIP which had potentially different failure modes

7

Moore’s Law and More

2009- iNEMI

• Leading iNEMI firms identified that there was a need for a

consortial effort to develop system approaches to electronic

packaging for the next generation of SIP, SOC, TSV, and 3D

Packaging

• Optimizing at each level of supply chain would not

achieve the desired technology

• Cisco, TI, and Intel identified an impending technology gap in

organic substrates for advanced packages which would

impact the entire supply chain.

• Leadership Team Planned a 1 ½ day workshop to address

this need.

• Workshop was held in Nagoya Japan in November 2009

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Organic Packaging Substrate Workshop

10

Speakers and Companies– Jie Xue Cisco

– Hamid Azimi Intel

– Hirofumi Nakajima NEC

– Luis Rivera TI

– Bernd Appelt ASE

– JaeYoon Kim Amkor

– Kenny Lee STATS ChipPAC

– Masaru Takada Ibiden

– Koichi Nonomura Kyocera

– Kozo Yamasaki NTK

– Steve Yang NanYa

– Richard Sheridan UMTC

Represented Countries

– USA, Japan, Taiwan, Korea, Singapore, Europe, and China

Work Shop Objectives

• Main Objectives:

– Identify gaps in organic substrate technology that

need to be addressed to facilitate the continued

advancement of electronics packaging.

– Identify issues and needs that are potentially best

solved by consortium activities.

– Set the priorities and direction for future collaborative

efforts on organic packaging substrates.

– Form action groups to execute the required industrial

collaborative programs.

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Packaging Assembly

Companies

SubstrateProviders

OEMs and IC

Companies

Organic Substrate

Technology Gaps

and Roadmap

R&D Pre-Competitive Collaboration Model

Collaboration

iNEMI Provides the Opportunity for

International Consortial Collaboration12

Key Themes and Focus

• Three key themes were identified as a means to guide

speakers in preparing their presentations.

– Aligning Substrate Roadmaps and Bridging Gaps

– Standardized Evaluation of Key Substrate

Performance Outputs and Reliability

– Priorities for Consortial Activities

13

Current iNEMI Consortial Research Activities

2009-2011

2010-2011 Current Activities

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• Copper Wire Bonding Reliability, Phase 2

• Package Warpage Qualification Criteria

• Primary Factors in Component Warpage

• Wiring Density for Organic Packaging

Substrates

Copper Wire Bonding

Reliability Project

Project Leaders

Chair:

Peng Su,

Cisco Systems

Strategy Issues Graphics

Project Lead:

Project Co-Lead:

Tactics Milestones and/or Deliverables Plan Actual

Focus Area:

Nov-11TIG:

Goal:Understand key issues and concerns regarding reliability of fine-pitch Cu wire bonding for semiconductors.

• 2-phased project. The first phase will focus on collecting information from the industry regarding the key processing and reliability issues pertaining to Cu wire bonding. The second phase of the project will perform necessary experimental work in the areas defined by Phase 1.

• Copper bond wires are

increasingly being used for a wide

variety of components.

• Reliability needs to be collectively

assessed by the industry in a

quantitative manner.

• Standard reliability test methods

and durations for Au wire device

may not be sufficient for Cu.Peng Su, Cisco Systems, inc.

TBD

Phase 1• 1. Industry Survey• 2. Existing Data Review• 3. DOE Plan for Phase 2Phase 2• 1. Finalize DOE• 2. Procure Materials• 3. Package Assembly• 4. Reliability Tests• 5. Failure Analysis• 6. Summary

Miniaturization

Packaging

Copper Wire Bonding Reliability Project

Initiative Launch Date

Project Inauguration - Two PS Signers

Conduct survey, analyze inputs

Plan DoE for phase 2

Phase 2 open for sign up Sep-11

Mar-11 Dec-10

Jan-11Nov-10

Sep-10Sep-10

Mar-10Mar-10

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More information at: http://www.inemi.org/project-page/copper-wire-bonding-reliability

Cu Wire Bonding Reliability

Project Members Phase 1

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Wiring Density for Organic Packaging

Substrates –Phase 1

Project Chair:Luis Rivera, Texas

Instruments;Co-Chair:

Islam Salama, Intel

Strategy Issues Graphics

Project Lead:

Project Co-Lead:

Tactics Milestones and/or Deliverables Plan Actual

Thrust Area:

7 April

2011TIG:

Goal:Identify approaches that will meet wiring density needs for future generations of semiconductor packaging.

• Develop a wiring density roadmap applicable to multiple substrate technology spaces, able to accommodate future developments & advances, and inclusive of a variety of plated finishes and interconnect requirements

• The major goal of this phase is to get industry feedback (using a survey) on which substrate design features should be included in a roadmap that will accurately represent future wiring density needs from the perspective of Material Set, Low Cost Litho/Laser, Plating and Inspection/Test.

• Having a good technology roadmap is a gating item to moving forward.

• Initially take the ITRS Roadmap and overlay the HVM information.

• Clearly define what HVM is, e.g., 10M, 100M, etc.

• Try to capture what the design rules are for the majority of their volume.

• Identify where the edges are? Luis Rivera, Texas Instruments

Islam Salama, Intel

• Phase 1

– Plan the survey

– Prepare logistics of survey

– Conduct survey

– Collect and analyze results

• Prepare project plan for Phase 2

Miniaturization

Organic Pack. Substrates

Wiring Density for Organic Packaging

Substrates – Phase 1

Initiative Launch Date

Develop survey questions

Deploy Survey

Collect and analyze survey responses

Project Final Report 3Q-11

2Q-11

2Q-11

1Q-11

1Q-111Q-11

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Substrates Technology

Roadmap Tracking

• What we know how to do?

• What we think can be done?

• What we have no clue on what or how to do?

• What is claimed?

• Critical review of claims

• What gaps exists?

Guidelines for Successful Consortia

Projects

Guidelines for Successful Consortial Projects

• Involvement of major volume players in the supply

chain, particularly the OEM

– Work on those non-proprietary issues that accelerate

the adoption of new technology.

– Today iNEMI has five major OEMs and three major

packaging houses heavily engaged in leading these

packaging activities.

• The primary foci of the activities are:

– To verifying process/materials reliabilities of new

solutions

– To develop standards

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BoD: Byung Joon Han – STATS ChipPAC

Co-Chairs: Hamid Azimi – Intel; Jie Xue – Cisco

Leader: Bob Pfahl – iNEMI

John Savic – Cisco

Mahadevan Iyer– Texas Instruments

Charan Gurumurthy – Intel

Jim Wilcox, IBM

Sheldon Schwandt & Willie Henderson, RIM

Bernd Appelt – ASE

Lee Smith – Amkor

IBIDEN

NTK

Rolf Aschenbrenner, Fraunhofer IZM

Eric Beyne, imec

iNEMI Packaging Leadership Steering Committee

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Summary & Conclusions

25

The 2009 workshop and subsequent meetings of the

iNEMI Miniaturization Leadership Steering Committee

have identified areas best addressed by consortial efforts

and those areas best left for individual firms or teams to

develop.

Major packaging firms have declared that they will

address the implementation of the new technology.

The OEMs have agreed to define common technology

needs.

Summary

Conclusions

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The goal of the iNEMI packaging effort is to speed the

introduction of new packaging technology to meet the

performance needs and the cost objectives of the

electronics industry: a win-win for all participants.

The paradigm shift to a multi-firm collaborative system

will increase the performance and reduce the risk of

introducing new technology.

This effort is critical for the growth of our industry.

We welcome global participation in all projects

Overview of Following Presentations

• Thermal Cycle Testing and Alloy Test Standards

Development – iNEMI Pb-Free Alloy Characterization

Program Update, Sze Pei Lim, Indium Corporation

• Investigation of Factors That Influence Creep Corrosion,

Cherie Chen, IST

• Technology Needs to Meet Increasing Wiring Density

Requirements, Mostafa Aghazadeh, Intel Corporation

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www.inemi.orgEmail contacts:

Bob Pfahl

bob.pfahl@inemi.org