chipset programming on embedded ia (tunnel creek version) shi, steven 2011, july

Chipset Programming on Embedded IA(Tunnel Creek version)

Shi, Steven2011, July

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ObjectivesAt the end of this session, you will be able to:

Know the IA platform architecture trend SOC Review the methodology of general IA

programming Know some industry IO standards and

programming interfaces exposed on Intel Tunnel Creek

Know some key IO technologies for future Embedded/SOC chipset enabling

Get some practical Lab samples for college course

Agenda

The IA platform architecture trend Chipset architecture and Programming methodology review

(Multi-layers to enable devices) Usb Flash Disk (Lab) LPC (Lab)

New devices programming interface intro PCI/PCIE (Lab) Usb3.0 (Lab) SDIO (Lab) ACPI - CPU C/P states (Lab) I2C , SPI and CAN

Other embedded platform Some potential future topics

IA platform architecture trend

IA platform Architecture - Previous

CPU-North-South

Processor

FSBAnalogDisplayVGA

AGP orPCI Exp.Graphics

Card

SystemMemory

(G)MCH

ICH

DMI/Hub Interface

IDE (& SATA))

USB

GPIO

Power Management

Clock Generation

LAN

System Management

SMBus/I2C

Other ASIC(Optional)

Super IO

BIOS Support/ Firmware Hub

Low Pin Count (LPC) Interfaces

Key Board

Mouse

…

PCI Bus

G_Ethernet

PCI Exp.

AC’97 Codecs

IA platform Architecture - Menlow

CPU-SCH

Processor

FSBAnalogDisplayVGA

AGP orPCI Exp.Graphics

Card

SystemMemory

IDE (& SATA))

USB

GPIO

Power Management

Clock Generation

LAN

System Management

SMBus/I2C

Other ASIC(Optional)

Super IO

BIOS Support/ Firmware Hub

Low Pin Count (LPC) Interfaces

Key Board

Mouse

…

PCI Bus

G_Ethernet

PCI Exp.

AC’97 Codecs

SCH

IA platform Architecture - PineTrail

8

Legal text goes here in Verdana regular 7pt.BIOS Support

/ Firmware Hub

CPU-SCH

IA platform Architecture – TunnelCreek

IA platform Architecture – TunnelCreek

IA platform Architecture – TunnelCreek

Platform Controller

Hub EG20T

IA platform Architecture - Summary

SOC is coming

Exercise and questions(实验习题与思考 )

1.Will PC be SOC system? 2.How many major chip there will be in IA client system

(Embedded, Tablet, Netbook, Notebook, Desktop, Workstation)?

3.What will future PC looks like?4.Why future is SOC?5.What will become easier and hardier for development?

Programming methodology review

IA Programming methodology Review

IA device programming methodology is stable , despite of the platform Architecture change

“…each new kernel release sees about 70,000 new lines of ARM code, whereas there's roughly 5,000 lines of new x86 code added”

TunnelCreek Architecture

Different device types: OS virtual device

Not real hardware ACPI device

real hardware, not connected through PCI bus

PCI connected Device real hardware connected through PCI bus

PCI/PCIE programming interface device or leverage PCI/PCIE programming to control itself

Our Target devices: PCI connected Device

Standard and usually cross platform

Device has hierarchical connection relationship

TunnelCreek Architecture

Programming methodology

Chipset Programming methodology Identify device hierarchical relationship on the PCIE

bus Get the target device location

Program with orders/levels Get to know the init sequence and precondition Lower level device dependence on higher level

Traverse to all leaves

Chipset Programming Pattern Detect target device Get or enable higher level assigned resource Specific Interface Initialization and publish Interrupt/Polling Service Exception/Error Handling

Case Study

How could I enable my USB2.0 Flash disk?How could I enable the serial COM/UART

port?

Check the hierarchical location for below devices: How could I enable my

USB2.0 Flash disk? How could I enable the

serial COM/UART port?

Case Study

Programming methodology – Question’s answer

Enable the devices layer by layer:

EHCI

Super I/O

OHCI

PCI Bus

LPC

Usb Mouse

Usb Flash Disk

Layer1 :Init PCI Bus

Layer2:Init PCI/PCIE host device

Layer3:Init specific child device

COM

Layer1: Init PCI Bus – Bios roleLayer2: Init PCI/PCIE host device - Bios and

OS roleLayer3: Init specific child device - Bios and

OS role

Case Study

Layer1: Init PCI Bus – What need to do

Init or Enumerate PCI Bus:1.Search all PCI device.2.Assign PCI unique address (Bus number,

for plug in device under bridge)3.Assign device required system resource

PCI Bus

Step1:Init PCI Bus

PciRootBridge

Layer1: Init PCI Bus – How to do it in Bios

Go through whole PCI bus twice:First time: Detect the bridge, to assign the Bus number.

- ensure the PCI configuration transaction can go through related device.- Deep first, recursively

Second time: Detect system resource and assign the device system resource.- Bios Pci Bus driver will calculate whole required system resource firstly, then assign them to different PCI devices.- Bios Pci Bus also report whole required system resource to OS through ACPI table.

Layer1: Init PCI Bus – How to do it in Bios

After Layer1 PciBus init, all PCI device is enumerated and found out but we don’t know what specific PCI device

they are.

PciIO

PciIO

ICH8PCI Bus

PciIO

PciRootBridge

Layer1 :Init PCI Bus

Layer1 Lab : Init PCI Bus

Disconnect –rConnect Pcibusdriver HandleDH –p Pciio

Layer2: Init Host controller

Which device is EHCI host controller?Which device is LPC host controller?

PciIO

PciIO

ICH8PCI Bus

PciIO

PciRootBridge

Layer1 :Init PCI Bus

Layer2: Detect Host controller

EHCI : check the class code and program interface

of PCI configuration space

LPC: check the Base Class and Sub Class Code of

PCI configuration space

Layer2: USB Lab – Enable Host controller

Disconnect –rConnect Pcibusdriver HandleDh –p usbhc2Connect Ehcidriver HandleDh –p usbhc2

Layer2: Init Usb host device

After Layer2 Usb host controller init, the Usb host controller is init but we don’t whether there is USB device on

those USB bus.

EHCIICH8PCI Bus

PciIO

PciIO

Layer2:Init PCI/PCIE host device

PciRootBridge

Usb_HC

Layer1 :Init PCI Bus

Layer2 : USB Lab – Enable USB Bus

Disconnect –rConnect Pcibusdriver HandleConnect Ehcidriver HandleConnect UsbBusDriver Handle

Layer2: Init USB Bus

After Layer2 USB bus init, all USB device is enumerated and found out but we don’t know what specific Usb device

they are.

EHCIICH8PCI Bus

PciIO

PciIO

UsbIO

Layer1 :Init PCI Bus

Layer2:Init PCI/PCIE host device

PciRootBridgeUsb_HC

Usb_HC

Layer2: Programming Pattern

Detect target Pci/Pcie device - EHC Status = PciIo->Pci.Read ( PciIo, EfiPciIoWidthUint8, EHC_PCI_CLASSC, sizeof (USB_CLASSC) / sizeof (UINT8), &UsbClassCReg );

if (EFI_ERROR (Status)) { Status = EFI_UNSUPPORTED; goto ON_EXIT; } // // Test whether the controller belongs to Ehci type // if ((UsbClassCReg.BaseCode != PCI_CLASS_SERIAL) || (UsbClassCReg.SubClassCode != PCI_CLASS_SERIAL_USB) || (UsbClassCReg.PI != EHC_PCI_CLASSC_PI)) {

Status = EFI_UNSUPPORTED; }

Layer2: Programming Pattern

Get or enable higher level assigned resource - EHC

// // Open the PciIo Protocol, then enable the USB host controller // Status = gBS->OpenProtocol ( Controller, &gEfiPciIoProtocolGuid, &PciIo, This->DriverBindingHandle, Controller, EFI_OPEN_PROTOCOL_BY_DRIVER );

Status = PciIo->Attributes ( PciIo, EfiPciIoAttributeOperationEnable, EFI_PCI_DEVICE_ENABLE, NULL );

Layer2: Programming Pattern

Specific Interface Initialization and publish - EHC

// // Create then install USB2_HC_PROTOCOL // Ehc = EhcCreateUsb2Hc (PciIo);

Status = gBS->InstallProtocolInterface ( &Controller, &gEfiUsb2HcProtocolGuid, EFI_NATIVE_INTERFACE, &Ehc->Usb2Hc );

Layer2: Programming Pattern

Interrupt/Polling Service - EHC// // Start the asynchronous interrupt monitor // Status = gBS->SetTimer (Ehc->PollTimer, TimerPeriodic, EHC_ASYNC_POLL_INTERVAL);

Layer2: Programming Pattern

Exception/Error Handling - EHC

if (EFI_ERROR (Status)) { return EFI_DEVICE_ERROR; }

if (Ehc == NULL) { EHC_ERROR (("EhcDriverBindingStart: failed to create

USB2_HC\n"));

Status = EFI_OUT_OF_RESOURCES; goto CLOSE_PCIIO; }

if (EFI_ERROR (Status)) { EHC_ERROR (("EhcDriverBindingStart: failed to start async

interrupt monitor\n")); EhcHaltHC (Ehc, EHC_GENERIC_TIMEOUT); goto UNINSTALL_USBHC; }

UNINSTALL_USBHC: gBS->UninstallProtocolInterface ( Controller, &gEfiUsb2HcProtocolGuid, &Ehc->Usb2Hc );

FREE_POOL: EhcFreeSched (Ehc); gBS->CloseEvent (Ehc->PollTimer); gBS->FreePool (Ehc);

CLOSE_PCIIO: gBS->CloseProtocol ( Controller, &gEfiPciIoProtocolGuid, This->DriverBindingHandle, Controller );

return Status;

Layer3: Init specific child device

Which USB device is Usb Flash disk?Where is COM/UART port and how to

access it?

EHCI

OHCI

ICH8PCI Bus

PCIIO

UsbIO

UsbIO

Layer1 :Init PCI Bus

Layer2:Init PCI/PCIE host device

PciRootBridgeUsb_HC

Usb_HC

Layer3: USB device drivers

Usb Bus driver

Host controller driver

Usb Device driver

EHCI

PCI Bus

OHCI

Layer3: USB Lab – Start USB device

Disconnect –rConnect

Pcibusdriver Handle

Connect Ehci driver handle

Dh –p usbioConnect USBBus

driver handleDh –p usbio

Dh –p blkioConnect Usb Mass storage driver HandleDh –p blkio

Layer3: Programming Pattern

Detect target device – Usb Flash Disk// // Get the interface to check the USB class and find a transport // protocol handler. // Status = UsbIo->UsbGetInterfaceDescriptor (UsbIo, &Interface); if (EFI_ERROR (Status)) { goto ON_EXIT; }

Status = EFI_UNSUPPORTED;

if (Interface.InterfaceClass != USB_MASS_STORE_CLASS) { goto ON_EXIT; }

Layer3: Programming Pattern

Get higher level assigned resource – Usb Flash Disk

Status = gBS->OpenProtocol ( Controller, &gEfiUsbIoProtocolGuid, &UsbIo, This->DriverBindingHandle, Controller, EFI_OPEN_PROTOCOL_BY_DRIVER );

Status = UsbIo->UsbGetInterfaceDescriptor (UsbIo, &Interface); if (EFI_ERROR (Status)) { DEBUG ((mUsbMscError, "UsbMassInitTransport: UsbIo->UsbGetInterfaceDescriptor (%r)\n",

Status)); goto ON_EXIT; }

Layer3: Programming Pattern

Specific Interface Initialization and publish – Usb Flash Disk

UsbMass->Signature = USB_MASS_SIGNATURE; UsbMass->UsbIo = UsbIo; UsbMass->BlockIo.Media = &UsbMass->BlockIoMedia; UsbMass->BlockIo.Reset = UsbMassReset; UsbMass->BlockIo.ReadBlocks = UsbMassReadBlocks; UsbMass->BlockIo.WriteBlocks = UsbMassWriteBlocks; UsbMass->BlockIo.FlushBlocks = UsbMassFlushBlocks; UsbMass->OpticalStorage = FALSE; UsbMass->Transport = Transport; UsbMass->Context = Context; UsbMass->Lun = Index; // // Create a UsbMass handle for each lun, and install blockio and devicepath protocols. // Status = gBS->InstallMultipleProtocolInterfaces ( &UsbMass->Controller, &gEfiDevicePathProtocolGuid, UsbMass->DevicePath, &gEfiBlockIoProtocolGuid, &UsbMass->BlockIo, NULL );

Layer3: Programming Pattern

Exception/Error Handling – Usb Flash DiskON_ERROR: if (UsbMass->DevicePath != NULL) { gBS->FreePool (UsbMass->DevicePath); } if (UsbMass != NULL) { gBS->FreePool (UsbMass); } if (UsbIo != NULL) { gBS->CloseProtocol ( Controller, &gEfiUsbIoProtocolGuid, This->DriverBindingHandle, UsbMass->Controller );

}

Layer2: Init LPC/SuperIO

Layer2: Init Host controller

Which device is LPC host controller?

PciIO

PciIO

ICH8PCI Bus

PciIO

PciRootBridge

Layer1 :Init PCI Bus

Layer2: LPC/SuperIO - W83627DHG-PStep 1: Enumerate

PCI bus to get the LPC bridge PCI device

Step 2: Enables decoding on the LPC for the super I/O (skipped in SCH, always enabled by HW)

Step 3: Configure the SuperIo internal component according to platform policy

Step 4: Now, we can use the UART through IO 0x03F8-0x03FF register block

Layer2: Init LPC/SuperIO After Layer2 LPC init, all ISA device can be accessed directlyLPC device is hardcode IO device, no need to enumerate, so no Bus driver

EHCIICH8PCI Bus

LPC

Layer1 :Init PCI Bus

Layer2:Init PCI/PCIE host device

PciRootBridgeUsb_HC

Usb_HC

PciIO

Super I/O COM

Layer2: Programming Pattern

Detect target Pci/Pcie device - LPC// // Check whether the Pci device is the wanted LPC controller // Status = PciIo->Pci.Read ( PciIo, EfiPciIoWidthUint32, 0, sizeof (Pci) / sizeof (UINT32), &Pci ); if (!EFI_ERROR (Status)) { // // See if this is a standard PCI to ISA Bridge from the Base Code // and Class Code // if (Pci.Hdr.ClassCode[2] == PCI_CLASS_BRIDGE) { //Sub Class Code if (Pci.Hdr.ClassCode[1] == PCI_CLASS_ISA) { //Base Class Code Found = TRUE; break; } } }

Layer3: Lab Demonstration - UART

A simple driver to show how to enable the LPC UART part, and use the UART to output “hello word!”.

Programming methodology

Chipset Programming methodology Identify device hierarchical relationship on the PCIE

bus Get the target device location

Program with orders/levels Get to know the init sequence and precondition Lower level device dependence on higher level

Traverse to all leaves

Chipset Programming Pattern Detect target device Get or enable higher level assigned resource Specific Interface Initialization and publish Interrupt/Polling Service Exception/Error Handling

PCI/PCIE Device system resource Lab

实验目的 Know the basic concepts of PCI/PCIE device Know PCI/PCIE device programming interface Know how to get assigned resource of PCIE device

实验器材 Atom Lab platform Windows XP

实验预习要求 Review the IA platform Programming methodology

实验内容Manually programming PCIE/PCI configuration space to get the required system resourceManually read the PCIE/PCI configuration space to know the assigned system resource

PCI/PCIE Device Programming basic concept

PCI Express elements emulate PCI configuration environmentPCI Express elements emulate PCI configuration environment

PCI-XDevice

PCI-X Device

CPU

Host BridgeAGPGFX

PCIBridge

PCI

PCI-XBridge

PCIBridge

PCI-XBridge

PCI-XDevice

PCI-X Device

Memory

PCI System

Endpoint

LegacyEnd

point

Switch Switch

Switch

CPU

Root ComplexPCI Express

GFX

PCIBridge

PCI

LegacyEnd

point

Endpoint

Memory

PCI Express System

PCI/PCIE “3D” Address SpaceA PCI target can implement up to three different types

of address space Configuration Space

Stores basic information about the device Allows the central resource or O/S to program a device with optional

setting I/O Space

PCI device consumed system resource, permit device to map its internal registers to those IO address.

limited, used mainly with legacy peripherals, like Usb1.1 uhci, LPC/ ISA

Memory Space PCI device consumed system resource, permit device to map its

internal registers to those volatile memory address. Used for just about everything else, modern PCI device, like Usb2.0

ehci

PCI/PCIE Configuration Space

PCI ExpressExtended

ConfigurationSpace

(Not availableon legacy OS)

Extended configuration space for PCI Express parameters capabilities

(First extended capability begins at

offset 100h)

0x1000

PCI ConfigurationSpace

(Availableon legacy OS

through CF8/CFC)

PCI Express Capability Structure

0

0x100

PCI 2.x Compatible Configuration Header

0x40

PCI/PCIE Configuration Space

PCI ExpressExtended

ConfigurationSpace

(Not availableon legacy OS)

0x1000

PCI ConfigurationSpace

(Availableon legacy OS

through CF8/CFC)

0

0x100

0x40

PCI/PCIE IO Space

This space is where legacy peripherals (Keyboard, serial port, etc) are mapped.

The PCI spec allows an agent to request 4 bytes to 2GB of I/O space. But x86 processor only supports an 64K I/O port.

Modern PCI/PCIE device don’t prefer to consume the IO space any longer.

PCI/PCIE Memory Space

This space is used by most everything else – it’s the general purpose address space The PCI spec recommends that a device use

memory space, even if it is a peripheral.

An agent can request between 16 bytes and 2 GB of memory space The PCI Spec recommends that an agent use

at least 4K of memory space, to reduce the width of the agent’s address decoder.

System Resource Consumed

• Memory• IO• DMA (for legacy device only)• IRQ

PCIE & Chipset Programming methodology

Lab steps (实验步骤 )1. Find the target PCIE/PCI device through

DeviceID/VenderID2. Stop the PCIE/PCI device3. Preserve the original value4. Write the Bars with allone5. Read the Bars response values6. Write back the original value

PCIE & Chipset Programming methodology

Lab steps (实验步骤 )1. Find the target

PCIE/PCI device through DeviceID/VenderID

PCIE & Chipset Programming methodology

Lab steps (实验步骤 )2. Stop the PCIE/PCI device

PCIE & Chipset Programming methodology

Lab steps (实验步骤 )4. Write the Bars with allone5. Read the Bars response values

PCIE Programming methodology

Exercise and questions(实验习题与思考 )1.How a PCIE device expose its programming

interface(PI)? 2.What’s the same and different between System

Memory Address, MMIO and IO? 3.Since the IO address is old, why we still maintain it?4.How to know how many resource a PCIE device need

through its PI?5.Please summary what type system resource the below

devices need? Ehci, SATA, SMBus6.Please change the assigned resource to difference

range in BIOS or OS, and let it still work fine.

Usb3.0

Usb3.0 cable assembly

Usb3.0 cable assembly

Usb3.0 cable assembly

70

Physical Layer OverviewDefines the signaling technology for the SuperSpeed

bus. The physical layer function is to encode 8-bit data from the link layer

into 10-bit symbols and exchange the symbols between devices reliably.

The physical layer consists of a transmitter, a receiver, and the necessary clock sources for the transmitter and the receiver.

The channel can be FR4 stripline, microstrip, a cable, or a combination of these components.

Tx

Rx

Host Host Channel

Cable Conn

Tx

Rx

DeviceDevice Channel

Ref Clk A Ref Clk B

pinspads pads

Conn

Typical Channel topologyHost silicon Tx/Rx Device silicon Tx/Rx

Differences From High-SpeedHigh-Speed

480 MT/s No-SSC 2 wires for signaling

Tx and Rx use same wire

1 bi-directional link DC coupled bus NRZ encoding

SuperSpeed 5.0 GT/s SSC is required 4 wires for signaling

2 for Tx and 2 for Rx Each Uni-directional

AC coupled bus 8b10b encoded

Device BHOST

+

-

+

-

+-

+-

Tx

Rx

Rx

Tx

Tx

Rx

+-

+

-

+-

+

- Tx

Usb3.0 Bus Architecture

Usb3.0 Packet Flow

 Screen clipping taken: 2011/7/25, 10:10  

Usb3.0 Hub Architecture

Usb3.0 vs. Thunderbolt

USB overview

• Host, hub and device build up the topology map, one HC one Bus UHC/OHC: Usb1.1 EHC: Usb2.0 XHC: Usb3.0

• 4 transfer speeds: low (1.1), full(1.1), high(2.0), super high(3.0)

• 4 transfer types: control, bulk, interrupt, isochronous• Plug and play• Support power management • USB 1.1&2.0 is a polled bus, it is the host to device or

device to host transfer mode, not the point to point mode (But USB3.0 is PtP)

USB2.0 Basic programming concept

Usb Bus driver

Host controller driver

Usb Device driver

EHCI

PCI Bus

OHCI

USB Basic programming concept

Usb Bus driver

Host controller driver

Universal Serial Bus Specification 3.0Universal Serial Bus Specification 2.0

eXtensible Host Controller InterfaceEnhanced Host Controller Interface Specification Universal Host Controller Interface (UHCI) Design GuideOpen Host Controller Interface Specification

Device Class Definition for Human Interface DevicesMass Storage Class Bulk-Only Transport spec Usb Device driver

USB Basic programming concept

UsbMassStorage

Usb Bus driver

UsbKB

UsbIO

BLKIO TxtIn

EHC driver

UsbMouse

OHC driver

Pointer

UsbIOUsbIO

Usb2_HCUsb2_HCLayer2

USB Basic programming concept

80

USB Basic programming concept

Device States: Attached Powered Default Address Configured

81

USB Basic programming concept

usbview.exe

USB2.0 host controller drivers

Usb Bus driver

Host controller driver

Usb Device driver

EHCI

PCI Bus

OHCI

EHCI Programming interface

EHCI Programming interface

Memory Space

FrameList

Periodic QH

Async QH

MM IO

B0:D29:F7

PCI Configuration Space

EHC MMIO Op regs block

Architecture of EHCI

EHCI Programming interface

EHCI Programming interface

EHCI Programming interface

Memory Space

FrameList

Periodic QH

Async QH

MM IO

B0:D29:F7

PCI Configuration Space

EHC MMIO Op regs block

Control

Isochronous

Bulk

Interrupt

USB standard Transfer

USB Bus Enumeration

90

Usb Bus driver

Host controller driver

Usb Device driver

EHCI

ICH8PCI Bus

UHCI

USB Bus – How to do it in UEFI

Enumerate new Usb Bus steps: UsbGetMaxPacketSize UsbSetAddress UsbSelectConfig

All above steps need Usb control transferDemo in shell for the step sequence.

eXtensible Host Controller Interface

eXtensible Host Controller Interface

Usb Bus driver

Host controller driver

Usb Device driver

XHCI

PPTPCI Bus

EHCI

Usb3.0 and Usb2.0 Driver relations

UsbMassStorage

Usb Bus driver

xHC driver

UsbKB

UsbIO

BLKIO TxtIn

EHC driver

UsbMouse

UHC driverOHC driver

Pointer

Usb2_HC

UsbIOUsbIO

Usb2_HCUsb2_HCUsb2_HC

General Architecture of XHCI

Xhci v.s. Ehci/Uhci for programming

Ehci/Uhci Device states unrelated Hardware is simple Software own and track all

device info Software own the detail

transactions level schedule, need create every transaction for a transfer

Xhci Device states unrelated Hardware is complex Hardware own and track

device info Software only own the

transfer level schedule, need not create detail transaction for a transfer

Device BHOST

+

-

+

-

+-

+-

Tx

Rx

Rx

Tx

Tx

Rx

+-

+

-

+-

+

- Tx

Usb3.0 & Xhci host controllerLab goal (实验目的 )

Know the Usb3.0 and superspeed related concepts Know the host controller (Xhci) programming interfaces Know how to write the minimal Xhci driver to access Usb3.0

deviceLab devices(实验器材 )

Atom Lab platform NEC D720200F1 PCIE-Usb3.0 card Duet - Uefi driver development environment

Lab preparation requirement(实验预习要求 ) Review the Usb2.0 and high speed programming interface Review how to get assigned resource of PCIE device How to create Duet and boot shell

Lab context (实验内容 ) Write a basic Xhci driver to support Usb super speed and high

speed flash disk

实验步骤

Usb3.0 & Xhci host controller

Exercise and questions(实验习题与思考 )1.Does Usb3.0 equal SuperSpeed? 2.Does the Usb3.0 host controller support Usb2.0 high

speed device? How?3. Is the Usb interrupt transfer a real interrupt way?4.What transfer type a standard Usb flash disk need?

What about Usb Mouse and keyboard?5.What’s the programming interface design differences

among the Uhci/Ohci, Ehci and Xhci? Why?6.Please try to minimize and port the Uefi Xhci driver to

Meego/Vxworks/Linux to support a Usb KB or Usb Flash disk?

7.Please complete the Isochronous Transfer in UEFI

SDIO

SDIO

Two SDIO ports:Conforms to SD Host Controller Standard

Specification Ver1.0, speed class 6— SD memory card: SD Memory Card

Specifications Part 1 Physical Layer Specification Ver2.0

— SDIO card: SDIO Card Specification Ver1.10— MMC: MMC System Specification Ver4.1

SDIO Basic programming concept

SDIO Basic programming concept

Tunnel Creek SDIO programming interface

SDIO LabLab goal (实验目的 )

Know the Know the

Lab devices(实验器材 ) Atom Lab platform NEC D720200F1 PCIE-Usb3.0 card Duet - Uefi driver development environment

Lab preparation requirement(实验预习要求 ) Review the Usb2.0 and high speed programming interface Review how to get assigned resource of PCIE device How to create Duet and boot shell

Lab context (实验内容 ) Write a basic SDController and MMC drivesr to support SD card

实验步骤

Exercise and questions (实验习题与思考 )

ACPI & CPU C/P states

ACPI Structure

ACPI Description Tables Structures

ACPI Description Tables Structures

ACPI Global System Power States

Processor States

C States and P States

C StatesProcessor Power consumption and

thermal management statesReduces power consumption by stopping

the processor Code only executes in the C0 state

OS idle handlers maintain the C State policy and perform C State transitions

C States – Contd.C0 (Full On)

Active Working State Can throttle the CPU to reduce CPU power consumption

C1 (Auto-Halt) Entered via STI-HLT instruction sequence no hardware support is needed from the chipset has no software-visible effects maintain the context of the system caches

C2 (Stop Grant) a low-power state optimized around multiprocessor

and bus master systems has no software-visible effects has lower power and higher exit latency than the

C1 CPU keeping its caches coherent

C States

C4 (Deeper Sleep) (Stop-Clock with lower CPU voltage) shuts down its PLL and cannot handle snoop requests Deep Sleep plus reduction in core voltage continue to handle traffic to memory so long as this traffic

does not require a snoop

C6 (Deep Power Down Technology) flush its cache and save its core context to a dedicated on-die

SRAM core processor’s voltage can be completely shut off.

P StatesMultiple frequency and voltage points for optimal

performance and power efficiency eliminating the need for any coordination during the

frequency/voltage transition.

Offers differing levels of operational efficiency while still in C0 Core frequency and core voltage are changed in unison An incremental shift in voltage is required to increase

frequency for any given processor ƒ ~ V, P ƒ * V2 P ~ V3

Leakage power ~ V2 Thus, reducing performance by 20% can reduce power by

~50%

P States & Turbo Boost

ACPI & CPU C/P states Lab

实验目的 Know the ACPI, CPU C and P states concepts Know the how to test and control the C and P states

实验器材 Atom Lab platform WinXP

实验预习要求 Review the ACPI spec 4.0 chapter 8

实验内容 Use tools to see the C states Use tools and test case to see P states different performance

实验步骤

I2C, SPI and CAN

I2C, SPI and CAN

Please refer the programmer guide for the driver API

I2C (Programmer Guide)

SPI (Programmer Guide)

CAN (Programmer Guide)

Other embedded platform

Some potential future topics

• System resource – IO/Mem/MMIO – how the range layout comes from?

• GPIO – LED – How to create LED lab through Atom platform

• Timer/WatchDog – How to implement watchdog through Atom various timer

• IA interrupt – APIC and IOAPIC• Schematic analyze

Need you feedback

Uefi Bios, Dos, Linux, Meego, vxWorks?C, assemble?Software, peripheral device, EE

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What is DUETDUET – Intel Platform Developer UEFI EmulaTion

Why DUET? Provide IHV an EFI/UEFI environment above legacy BIOS, to help them develop and

debug their native EFI/UEFI drivers.

DUET Goal

Goal is … Export EFI/UEFI interface Support IA32 and X64 architecture Chipset/Platform independent Boot from Floppy Boot from USB (Legacy Free Consideration) Support boot to EFI/UEFI Shell

DUET Goal (Cont’d)

Goal is not: Not all Framework/PI interfaces are supported

(for example: No PEI phase) Not support IPF

DUET Pre-requisitePre-requisite:

Platform support USB boot. USB Key support USB boot.

How to verify that: Create DOS on USB. Boot to DOS on the platform by select USB boot.

DUET Lab SetupSystem requirements:

Microsoft Windows 2000/XP/2003/Win7 256MB+ System Memory 500MB+ Free Space on Hard Drive Visual Studio .NET 2003 or 2005 Professional MASM615

Unzip CD contains EDK and EFI-Shell (May have already been done in NT32 Lab First Day) Unzip the EDK-1.04.Zip to C:\Fw Unzip the EfiShell-1.04.Zip to C:\Fw\Edk\Other\Maintained\

Application

Use the Visual Studio command prompt to setup the proper compiler environment

Make sure MASM6.15 is installed in C:\MASM611.

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Duet Compiler environment

CD C:\FW\Edk\Sample\Platform\DUET\Build

Update the Config.env file for VS 2005 Only Set USE_VC8 = YES

Build the DUET x64 tip SET EDK_SOURCE=C:\FW\EDK CD C:\FW\Edk\Sample\Platform\DUET\ BUILD UEFI64

Wait for Build to finish …

Build DUET

Build Time stamp

Build DUET (Cont’d)

Create DUET Boot diskPlug Bootable USB disk to the system.Check USB drive number from “My Computer”, for example: E: (See below)In command line

• SET EFI_BOOT_DISK=E:• CD UEFI64• NMAKE CREATEUSB

Unplug this USB, then plug it again• NMAKE USB

Create DUET Boot disk (Cont’d)

Very important

Boot DUETPlug the USB to the target, and choose

boot from USB.Enjoy the EFI world on your legacy PC …

Below is my T61.