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CHAPTER-3
MEASUREMENT OF COMMON MODE VOLTAGE IN 2- LEVEL INVERTER FED INDUCTION MOTOR DRIVE
3.1. INTRODUCTION Induction Motor (IM) is considered as a constant speed motor with
certain limitations. Earlier days, speed control of IM was not as easy as it
demands simultaneous variation in voltage and frequency but by the
introduction of microprocessor this has become easier. CM voltage is a
natural result of PWM techniques used in adjustable speed control of IM
[7, 33]. It was found that the CM voltage in the drive system was
responsible for disturbance to the measuring circuits and
communication circuits connected to the same power line. Fig 3.1 shows
the block schematic diagram of adjustable speed drive (ASD) [7, 33].
Fig. 3.1. CM voltage as EMI source
CM voltage can be defined as follows [7, 8].
Vag = Van+Vng (3.1)
Vbg = Vbn + Vng (3.2)
Vcg = Vcn+ Vng (3.3)
Sum of all phase to neutral voltage is zero
47
Vng = [Vag +Vbg+ Vcg] (3.4)
CM current “Ilg” = C Where “C” is the total capacitance in the system [7,
8]. High frequency bearing currents are due to the flow of current in the
CM circuit from the shaft of the IM to ground. This chapter proposes the
experimental work on the 2-level inverter and measurement of the CM
voltage at the star point of stator winding of a modified squirrel cage IM
to the general ground. 2-level inverter is fabricated by using power
MOSFETs (2SK962) and the Undeland snubbers are used along with fast
recovery diodes. SVM scheme (as discussed in chapter-2) is used for the
generation of gating signals and the inverter is designed to operate at
40Hz frequency. The simulation is done by using the
MATLAB/SIMULINK software and the results are presented. By
conducting the experiment the DSO recorded Voltages/current and the
processed FFT results are presented.
3.2. LITERATURE SURVEY The most common method of speed control of IM utilizes the PWM [7,
22 & 60]. Though the speed control of IM gained popularity by the advent
of modern power electronics associated with high power devices like
power MOSFET /IGBT there is a lot of concern about the CM voltage and
the EMI is due to the high switching transients of the power devices,
which are harmful to the motor bearings, measuring and controlling
systems/instruments connected to the same mains. There are many
48
undesirable effects of the use of solid-state power converters/inverters,
due to its non-linear nature.
Based on the above reasoning it is very much essential to minimize
the CM voltage/current, there by the EMI interference, should be
reduced to the acceptable limits by the use of advanced electronics
instrumentation and control. The available techniques of CM voltage
reduction are 1) An active circuit for cancellation of CM voltage generated
by PWM, 2) A dual bridge inverter approach to eliminate CM voltages, 3)
The mitigation techniques of CM voltages in PWM inverter, 4) The
modulation technique used is characterized by a low switching frequency
which also helps to reduce the CM noises. In this work SVM modulation
scheme is used for MLIs to study and measure the CM voltage.
3.2.1. Generation, control and regulation of CM voltage and EMI from IM drives Adjustable speed IM drive (ASD) manufacturers now switched over to
IGBTs from BJT due to its merit [32, 33]. The merits are, the rise/fall
time of the switching capability is 5-10 times faster in IGBT, thereby
lowering of the device switching losses and also requires only low current
drive circuits. But the disadvantages are higher dv/dt transitions due to
the high switching frequencies and faster output. This increases the EMI
problems. There should be regulation standards on allowable conducted
emissions for the successful drive system installations.
The CM noise is an electrical noise induced on signals with respect to
general ground. CM noise problems imply a source of noise, a means of
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coupling noise by conduction or radiation from circuits/equipments,
susceptible to the magnitude, frequency and repetition rate of the noise
impressed.
Fig. 3.2. Potential CM noise problems
Fig.3.2. shows [7, 32&33] potential CM noise problems increase with
susceptible equipment present, system input voltage, system drive
quantity and length of motor cables. There are other factors such as
ground system and cabinet layout.
Higher drive carrier frequency (fc) increases the number of switch
transitions and sum of the CM noise current. Generally if the length of
the motor cable from the inverter is less than 20 feet [7, 33], which will
exhibit low line to ground capacitance and hence low CM noise risk from
capacitive dv/dt ground currents. As the cable length is long, the high
frequency oscillations of reflected wave voltage transients appear on the
motor terminals, which will weaken the insulation of the stator winding
and cable capacitance [33]. Hence the EMI reduction must involve the
50
safety, equipment grounding, signal grounding and the effect of
grounding system type depending on CM noise.
3.2.2. IM drive as an EMI noise generator The PWM inverter output voltage has abrupt voltage transitions to and
from the DC bus controlled by power MOSFET/IGBT [7, 33]. Switching
time and power are the main sources of conducted and radiated noise.
Generally IGBT rise times are of the order of 0.05 µs to 0.2 µs, while
BJTs are of the order of 1 µs to 2 µs, corresponding to “fn” of 6.4 – 1.6
MHz [7, 32] and 320 – 160 KHz, respectively, output dv/dt is now 20 to
40 times higher. Most drive related EMI [9] is due to conducted noise
currents hence it is obvious that the CM noise current increases with low
trise and higher bus voltages. Due to high carrier frequency “fc” increases
the EMI, since the CM power repetition rate is faster. The CM current
flows in the ground wire and hence it produces the CM voltages.
The issue of conducted CM current inducing CM voltage in system
noise coupling paths and some solutions to control EMI are well
discussed in literature [33, 63]. There are four basic important steps for
the mitigation of EMI [8, 9] and they are as follows.
(1) Proper grounding (2) attenuate the noise source (3) shield noise away
from sensitive equipment/instrument and (4) capture and return noise to
the source (drive). All the above four important steps are well explained
in the reference [21, 32] and are self-explanatory.
51
3.2.3. EMI in switching power converters The growth of power electronic equipments/systems in the recent years
is due to the advancement of power converters [7, 9]. In these the
switched mode power supplies, adjustable speed AC drives, utility
interface and the other power electronic equipments in the industries are
becoming increasingly common. These converter’s switching frequencies
are high due to advancement of power semiconductor devices. Due to
fast switching frequency of the power devices there exists the CM voltage
at the output of the converter [9]. This leads to the EMI and EMC
problem.
3.2.4. Nature of conducted emissions The conducted emissions of a power electronic circuit measured across
the line impedance stabilization network (LISN) can be broadly split up
into CM and differential mode (DM) emissions [22, 64]. This division is
distinctly due to different causes and noise current paths.
3.2.5. Causes of common mode emissions The normal operation of switching power converters requires the use
of switching states that tend to generate the potential to the load [7, 21].
Very often the rate at which this oscillations caused is equal to the
switching frequency of the converter. It is well known that PWM
operation at high frequencies produces voltages with spectral contents
extending to MHz. In the presence of parasitic coupling (capacitance) to
ground, this spectral energy causes CM currents to flow between the
52
power lines and the ground. This, in a fundamental sense, is the
mechanism by which CM EMI is generated [7, 21].
The magnitude of this current depends upon the value of the parasitic
coupling capacitance of the motor to ground. Further, the neutral
potential with respect to ground provides the CM excitation. This
potential is by definition as the CM potential (CM voltage) applied to the
load by the inverter. In the conventional PWM operation this potential
oscillates with amplitude of one sixth of the total dc bus voltage of the
inverter on either side of ground, and is never zero. As mentioned before
it has substantial high frequency spectral energy and therefore the CM
current resulting from this spectral energy is far from negligible. It is to
be noted that if the motor is excited by symmetrical 3-phase sinusoidal
source, the CM voltage applied to the load would be ideally zero, and no
emissions would result. It follows from this reasoning that if the
converter could be operated such that the neutral potential would be
ideally zero at all times, then the CM emissions could be seriously
attenuated. This method is popular for the active noise cancellation [7].
Although the discussion of CM emissions presented has focused on
the 3-phase drive systems, it is applicable to almost all power electronic
converters. In the practical implementations, the parasitic capacitance
to ground can never be eliminated. In addition to the parasitic coupling
of the load to the ground, the parasitic coupling between any part of the
system that has a high dv/dt and the ground causes CM emissions. The
53
mechanism of noise current generation is again very much same as that
discussed above. Fig.3.1 shows the schematic block diagram of a modern
power electronic drive which consists of secondary of the 3-phase
transformer, LISN, converter, PWM inverter and 3-phase IM. Vng is the
voltage between neutral to the general ground which is also called as star
point of stator winding of an IM to ground and also the direction of Ilg is
as shown in Fig.3.1[7].
3.3. SPACE VECTOR MODULATION SCHEME
Reference [54] Compared SPWM & SVPWM and concluded that the later
method yields 15% higher inverter output voltage. SVPWM is based on
space vector theory which has its origin in the generalized theory of
electrical machines. For a given minimum line side voltage SVPWM
control strategy requires less DC bus voltage, consequently the voltage
stress on the power devices is less, results in less EMI effects, further
SVPWM results in reduced harmonic distortion in the line currents. The
proposed scheme is said to have the merit over other PWM schemes in
terms of efficiency and can be easily implemented. In order to obtain
optimum performance and the minimum switching frequency for each of
the power devices, the switching state sequence is arranged such that
the transition from one state to the next is performed by switching only
one inverter leg. This condition is met if the sequence begins with one
zero state and the inverter poles are toggled until the other null state is
reached. To complete the cycle, the sequence is reversed ending with the
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first zero state. The pulse pattern arrangement of (right aligned sequence)
is shown in Fig.3.3. [12]. SVM scheme, procedure and principles are
already discussed in chapter-2.
Fig.3.3. Signal switching sequence pattern
3.4. SIMULATION MODEL OF3-PHASE 2-LEVEL INVERTER
Simulation is carried out using MATLAB/ SIMULINK software. Fig.3.4
Shows SIMULINK model for 2-level inverter fed IM drive using SPWM
technique. PWM signals are generated using a high frequency triangular
wave, called the carrier wave, is compared to a sinusoidal signal
representing the desired output, called the reference wave. Whenever the
carrier wave is less than the reference, a comparator produces a high
output signal, which turns the upper switch in one leg of the inverter ON
the lower switch OFF. In the other case the comparator sets the firing
signal low, which turns the lower switch ON and upper switch OFF.
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SIMULINK model also includes CM equivalent circuit with bearing model
for measurement of shaft voltage and bearing current. Method used in
modeling of IM and CM equivalent circuit parameters is as in the
reference [30]
Source Impedence
Cb Zb
Rb
Csr
Cg
TWO LEVEL SPWM INVERTER
Common mode equivalent ci rcuit with bearing model
Csf
Discrete,
Ts = 2e-006 s.
powergui
v+
-
v+
-
Shaft voltage
Phase Voltage
A
B
C
N
PWM Geneation for the
AC - DC - AC
Va
Vb
Vc
Van
Vbn
Vcn
A
B
C
Measurement
Line voltage
i+
-
Common mode voltage
Bearing current
A
B
C
a
b
c
AC - DC -AC
Conn1
Conn2
Conn3
3 -PHASE INDUCTION MOTOR
Fig.3.4.Simulink model of 2-Level inverter fed IM using SPWM.
Fig.3.5 shows the SIMULINK model for 2 level inverter fed IM drive using
SVPWM technique. Gating signals are generated using co-ordinate
transformation a-b-c to d-q. Switching time duration for each sector and
switching time of each switch is determined and applied to the switching
devices.
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2-Level Inverter Fed Induction motor (Space vector PWM )
Source Impedence
Cb Zb
Rb
Csr
CsfCg
Csf
Trig
Sector
a_b_vbus
Gate timing
switching time calculator
ramp
trig
ramp generator
Discrete,
Ts = 2e-006 s.
powergui
Vbus FVbus
low pass bus filter
ramp
gate_timing
L1a
L1b
L2a
L2b
L3a
L3b
gates logic
Angle Sector
ab vector sector
Vabc
Vbus
Angle
ab_Vbus
ab transform
v+
-
v+
-
A
B
C
B1
B2
Subsystem
Scope1
Scope
Neutral Voltages
g DS
Mosfet5
g DS
Mosfet4
g DS
Mosfet3
g DS
Mosfet2
g DS
Mosfet1
g DS
Mosfet
Va
Vb
Vc
Van
Vbn
Vcn
A
B
C
Measurement
Line voltage1
[s6]
[s5]
[s4]
[s3]
[s2]
[s1]
[s6]
From5
[s5]
From4
[s4]
From3
[s3]
From2
[s2]
From1
[s1]
From
i+ -
50
100
1
400
Common mode voltage1
Bearing voltage
Bearing current
Freq_com
Vcom
dir
Vabc
3phases sin generator
Conn1
Conn2
Conn3
3 -PHASE INDUCTION MOTOR LOAD
Fig.3.5. Simulink model of 2-Level inverter fed IM using SVPWM.
3.5. HARDWARE CIRCUIT DESCRIPTION
3.5.1. 3-Phase-half bridge converter: Fig. 3.6 shows the 3-phase half
controlled bridge converter. Three numbers of power diode and three
numbers of SCRs are used for forming the bridge of the converter.
Fig.3.6.The 3-phase half controlled bridge converter
57
3-numbers of line inductance (each of 0.8mH. not shown in the circuit)
which are connected in series with the supply line to the converter so as
to protect the converter bridge from di/dt effect and the snubbers used
are the resistor and capacitor (100 Ω, 0.1µF not shown in the circuit.)
across each SCR so as to protect it from dv/dt effect. The 3- phase AC
supply is connected to the system by using an isolation transformer [7].
The ON-OFF switch (not shown in the circuit) is interlocked with the
DC power supplies used for the converter and inverter. A filter capacitor
of 80µF (not shown in Fig. 3.6) is used after the converter. Before
connecting the converter output to the inverter circuit, a series
resistance of 10 Ω, 100W is connected in series so as to protect the
converter from dead short circuit in case of failure of the inverter devices.
3.5.2. Inverter circuit power module: In Fig.3.7 the insulated gate
bipolar transistor (IGBT) or a power MOSFET can be used as a switching
device for the inverter. The MOS devices are very sensitive to over-
voltages; hence some safety measures have to be taken during handling
the power MOSFET.
(1) Protection against the static charging during handling of the
components. (2) Protection against the over voltage in a circuit which
can be remedied by connecting a zener diode as closely as possible to
MOSFET module control circuit. (3) Fast recovery diode can be
connected across each of the power MOSFET with opposite polarity to
bypass the slow internal diodes for fast switching. (Power MOSFET will
58
have recovery diode built-in the structure). For the inverter circuit the
power MOSFET (2SK962) is used.
The gate drive circuit block diagram was discussed in the previous
chapter (Fig.2.10) and the µ-controller program is given in Appendix-4.
Fig.3.7. Power circuit diagram of 2- level inverter fed IM with undeland snubber circuit.(T1-T6 represents the power MOSFET)
3.5.3. Snubber circuit: The snubber circuit in Fig. 3.8 [35] is provided
across each leg of the inverter have the following advantages.
It reduces the stresses on the switching device during the switching
transients. As this reduces the power loss in the switching device the
switch ratings can be better utilized by using the snubber. A number of
configurations described by “Undeland” have been used to build the
inverter as this has the following advantages over the other snubbers. It
has fewer components and the snubber diodes do not cause difficulties
59
due to their reverse recovery and all the losses are dissipated in one
resistor.
Fig.3.8. The Undeland snubber circuit.
3.5.4. Design of LS, CS, C0 and RS: The inductor “LS” is used to limit the
rate of rise of current, when, either of the switches is turned ON. The
value of “LS” is decided by limiting the current through the switch at the
end of the rise time (tr) to 10% of the full load current. This value is
sufficient to consider the switching process of one device, as the
switching process of other device is almost similar. Voltage across the
device during rise time is
V = 1- t/tr X Vdc (3.5)
LS = Vdc X t / tr = 10 X 0.1 (Vdc +t) dt. (3.6)
LS = 1 / (10 X0.1) X (600X2X10-6)/2 = 600 X 10-6 H. (3.7)
This value of the inductance also decides the current build up in the
device after a short circuit and before the short circuit protection of all
the devices. An inductor of 500 µH has been used for this purpose.
60
Design of CS and C0: The value of CS is decided such that the capacitor
will be exactly recharged to Vdc at the end of current fall time during the
switching OFF of the top and bottom device of the same leg.
Cs = (IL/2Vdc) X tr = (10/2X600) X 2X10-6 = 0.016 µF (3.8)
CS is chosen as 0.05 µF as higher value will only further reduces the
stress in the switch. The value of C0 is recommended to be about 10
times the value of CS and it is taken as 0.5 µF.
Design of RS: The over voltage across the switching devices caused by
the snubber energy dissipation is analyzed by equivalent circuit shown in
Fig. 3.8. The value of “C” at turn ON of top device and turn OFF bottom
device of the same leg is (C0 + CS) and it is C0 for the other switching.
The initial inductor current I0 is Imax at turn ON and IL at turn OFF.
The circuit may be over damped or under damped depending on the
resistance value. The value of resistance for critical damping is
Rcrit = 0.5 (Ls)½ / C ~ 15.8 Ω. (3.9)
The value of RS is chosen as 2.5 Ω to keep the circuit over damped.
Power circuit: The 3-phase inverter shown in Fig.3.7 is used in the
power circuit driving the IM in adjustable speed operation. Power
MOSFET switches are used with fast recovery diodes connected across
each device so as to handle the inductive currents.
3.6. GATE DRIVE CIRCUIT IMPLEMENTATION
This section presents the hardware implementation of the gate drive
circuit. There are several steps involved in implementing the control
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circuit discussion and the block diagram are shown in Chapter-2
(Fig.2.10).
3.7. RESULTS
3.7.1. Simulation results of 3-phase 2-level inverter (SPWM)
0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.05-500
0
500
Line voltage
Time(s)
Voltage(V
)
(a)
0.01 0.015 0.02 0.025 0.03 0.035 0.04-400
-300
-200
-100
0
100
200
300
400
Phase voltage
Time(s)
Voltage(V
)
(b)
0.01 0.015 0.02 0.025 0.03 0.035 0.04-300
-200
-100
0
100
200
300
Common mode volatge
Time(s)
Voltage(V
)
(c)
Fig.3.9.(a) Line voltage ,(b) Phase voltage, (c) CM voltage
62
3.7.2. Simulation results of 3-phase 2-level inverter (SVPWM)
0.01 0.015 0.02 0.025 0.03 0.035 0.04-600
-500
-400
-300
-200
-100
0
100
200
300
400
500
600
Time(s)
Voltage(V
)
Line volatge
(a)
0.01 0.015 0.02 0.025 0.03 0.035 0.04-400
-300
-200
-100
0
100
200
300
400
Phase voltage
Time(s)
Voltage (V
)
(b)
0.01 0.011 0.012 0.013 0.014 0.015 0.016 0.017 0.018 0.019 0.02-200
-150
-100
-50
0
50
100
150
200
Common mode voltage
Time(s)
Voltage(V
)
(c)
Fig.3.10.(a) Line voltage ,(b) Phase voltage, (c)CM voltage
63
3.7.3. Experimental results of 3-phase 2-level inverter (SVM)
Fig.3.11. Input to Motor (20ms/Div). Ch 1: 200 : 1 Phase voltage to IM. Ch 2: 200 : 1 Line voltage to IM. Ch 3: 20 : 1 wave form of vector sum of current in terms of voltage.
Ch 4:1: 1 One phase current in terms of voltage.
Fig.3.12 Input to Motor (20ms/Div). Ch 1: 200 : 1 CM voltage. Ch 2: 200 : 1 Line voltage to IM.
Ch 3: 20 : 1 wave form of vector sum of Ph current in terms of voltage. Ch 4: 1 : 1 Phase current in terms of voltage
64
Fig.3.13.DSO recorded waveforms.ch.1.200:1 CM voltage. Ch.2. 200:1Line voltage.Ch.3.1:1.sum of phase current.
Ch.4. 1:1.one phase current.
The simulation is done using MATLAB/SIMULINK software for 2-level
inverter fed IM and the simulated results are as shown in Figs.3.9 &
3.10. The experimental CM voltage, line voltage, vector sum of phase
currents in terms of voltage using current probe and the phase current
in terms of voltage are recorded using 4-channel DSO is in Fig.3.11 to
3.13. Fig 3.14 shows the experimental set-up of 2-level inerter.
Table.3.1. shows the line voltage, phase voltage and CM voltage
values of the 2-level inverter fed IM by simulation using
MATLAB/SIMULINK software. Table.3.2. shows the experimental results
of line voltage, phase voltage and CM voltage of the 2-level inverter fed IM
drive with a DC link voltage of 450V.
66
Table-3.1: Simulated Results
Parameters
SPWM technique
SVM technique
Phase voltage Refer Fig 3.9(b) and
3.10(b)
330Vpeak 320Vpeak
Line voltage Refer Fig 3.9(a) and
3.10(a)
500Vpeak 515Vpeak
Common mode voltage Refer Fig 3.9(c) and
3.10(c)
250Vpeak 186Vpeak
Table-3.2. Experimental Results
Parameters
SVM
Phase voltage Refer Fig.3.11.
324Vpeak
Line voltage Refer Fig. 3.12.
538Vpeak
Common mode voltage Refer Fig. 3.13. DSO recording
185Vpeak
67
-100 0 100 200 300 400 500 600 700 800 900 1000
0
50
100
150
200
Frequency (Hz)
Am
plitu
de in
volt
s
Fig.3.15. FFT of Phase voltage to IM Note: (In the above FFT plot –ve scale of frequency is shown deliberately
for reading the zero frequency magnitude. Strictly there is no –ve
frequency will exist and the same Note is applicable for all FFT plots)
Explanation: The Fig.3.15, the FFT of phase voltage waveform is as
shown and its voltage magnitude is found to be 205Vpeak at zero
frequency, however observing the phase voltage DSO recorded waveform
(Fig.3.11,ch.1) there exists the steady state values (stair case) hence the
phase voltage magnitude is shown at zero frequency but it should be
considered as fundamental. It is seen from the above plot that at 40Hz
the voltage magnitude is around 7Vpeak. In real sense the fundamental
frequency voltage magnitude is around 212Vpeak (205+7). The even
harmonic components should not be considered since while doing the
FFT, the –ve values are changed as +ve as per Origin signal analysis
68
software (in the symmetry of waveform the even harmonic voltages will
get cancelled), and the triplen harmonic components will circulates
hence should not be considered. The 5th and the 7th harmonic
component is found to be 1V and 0.5V respectively. All the other higher
frequency magnitudes of voltages are negligible.
0 200 400 600 800 10000
200
400
600
Frequency (Hz)
Am
plit
ud
e in
dB
µ V
Fig.3.16.FFT of Phase voltage to IM in dBµV
Fig. 3.16 shows the FFT of phase voltage in dBµV.
(Note: All the frequency vs dBµV/dBµA plots in this thesis may be
utilized for comparison with FCC and CISPR standards which is not the
objective/scope of the thesis work)
69
0 500 1000 1500 2000 2500
0
100
200
300
Frequency (Hz)
Am
plit
ud
e in v
olts
Fig.3.17.FFT of Line voltage to IM (2-level Inverter)
Explanation: Fig.3.17 shows the FFT of line voltage waveform. The
voltage magnitude is found to be 320Vpeak at zero frequency, however
observing the line voltage DSO recorded waveform (Fig.3.12,ch.2) there
exists the steady state values (stair case) hence the line voltage
magnitude is shown at zero frequency but it should be considered as
fundamental. It is seen from the above plot that at 40Hz the voltage
magnitude is around 30Vpeak. In real sense the fundamental frequency
voltage magnitude is around 350Vpeak (320+30). The even harmonic
components should not be considered since while doing the FFT, the –ve
values are changed as +ve as per Origin signal analysis software and due
to symmetry of waveform the even harmonic voltages will get canceled
and the triplen harmonic components will circulate hence should not be
considered. The 5th and the 7th harmonic component are found to be
70
4.5V and 2V respectively. All the other higher frequency magnitudes of
voltages are negligible.
0 500 1000 1500 2000 2500
0
100
200
300
Frequency (Hz)
Am
plit
ud
e in
db
µV
Fig.3.18. FFT of Line voltage to IM in dB µV (2-level Inverter)
Fig 3.18 shows the FFT of line voltage in dB µV. The voltage magnitude is
found to be 280 dB µV.
-100 0 100 200 300 400 500 600 700 800 900 1000
0
20
40
60
Frequency (Hz)
Am
plit
ud
e in
volts
Fig.3.19.FFT of CM voltage
71
Explanation: Fig.3.19 shows the FFT of CM voltage waveform. The
voltage magnitude is found to be 60Vpeak at zero frequency; however it is
seen from the above plot that at 40Hz the voltage magnitude is around
8Vpeak. In real sense the fundamental frequency voltage magnitude may
be around 68Vpeak (60+8). From the explanation of Fig.3.19, the FFT of
CM voltage at the fundamental frequency is considered as 68 V.
The even harmonic components should not be considered since while
doing the FFT, the –ve values are changed as +ve as per Origin signal
analysis software and due to symmetry of waveform the even harmonic
voltages will get canceled. The 5th and the 7th harmonic component are
found to be 1 V and 0.5V respectively. All the other higher frequency
magnitudes of voltages are negligible.
0 500 1000 1500 2000 2500 3000
0
50
100
150
200
Frequency (Hz)
Am
plit
ud
e in
dB
µV
Fig.3.20. FFT of CM voltage in dBµV
Fig.3.20 shows the CM voltage in dBµV & its magnitude is found to be
190 dBµV.
72
3.8. CONCLUSION
In this chapter, the measurement of CM voltage is done for the 2-level
inverter fed IM. As indicated in the Table-3.1 the simulated CM voltage is
186Vpeak and as per Table-3.2 the CM voltage recorded by DSO (Fig.3.13,
ch.1) is 185Vpeak. The simulated and the experimentally recorded wave-
forms of CM voltage values are in good agreement. The FFT plot of CM
voltage at fundamental frequency (40Hz) is around 68V. However the FFT
plots gives the voltages of various frequency components. Other high
frequency FFT plots are given in appendix-1 for reference only. The
frequency Vs dBµV graphs can be utilized to check for Federal
Communication Commission (FCC) and International Special Committee
on Radio Interference (CISPR) standards for the acceptable limits which
are not under the preview of the thesis. Hence it is concluded that
measurement of CM voltage has been done and the various frequency
voltage components are plotted for 3-phase 2-level inverter fed IM drive.
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