built-in self-test of programmable i/o cells in virtex-4 fpgas
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Built-In Self-Test of Programmable Built-In Self-Test of Programmable I/O Cells in Virtex-4 FPGAsI/O Cells in Virtex-4 FPGAs
Bradley F. Dutton, Lee W. Lerner, and Charles E. StroudBradley F. Dutton, Lee W. Lerner, and Charles E. StroudDept. of Electrical & Computer EngineeringDept. of Electrical & Computer Engineering
Auburn UniversityAuburn University
B. Dutton 5/15/08B. Dutton 5/15/08 North Atlantic Test WorkshopNorth Atlantic Test Workshop 22
Outline of PresentationOutline of Presentation
Previous WorkPrevious WorkOverview of Virtex-4 I/O TilesOverview of Virtex-4 I/O TilesVirtex-4 I/O BIST architectureVirtex-4 I/O BIST architecture
ILOGIC/OLOGIC ILOGIC/OLOGIC (input/output logic)(input/output logic)
SERDES SERDES (serialization/deserialization)(serialization/deserialization)
I/O StandardsI/O Standards
Capabilities and LimitationsCapabilities and LimitationsConclusionConclusion
B. Dutton 5/15/08B. Dutton 5/15/08 North Atlantic Test WorkshopNorth Atlantic Test Workshop 33
Previous Work in I/O BISTPrevious Work in I/O BIST I/O BIST for Atmel AT94K (NATW’06)I/O BIST for Atmel AT94K (NATW’06)
Proposed BIST architecture for 100% stuck-at faultProposed BIST architecture for 100% stuck-at fault
Configure bi-directional Cell Under Test (CUT)Configure bi-directional Cell Under Test (CUT)23 BIST configurations to test all modes of operation23 BIST configurations to test all modes of operation
AT94K I/O Cells are simple compared to Virtex-4AT94K I/O Cells are simple compared to Virtex-42 Flip-Flops, 4 Multiplexors, 3 I/O standards2 Flip-Flops, 4 Multiplexors, 3 I/O standards
=TPG=ORA
I/O CellsUnder Test
B. Dutton 5/15/08B. Dutton 5/15/08 North Atlantic Test WorkshopNorth Atlantic Test Workshop 44
Virtex-4 I/O TilesVirtex-4 I/O TilesTwo I/O Cells form I/O TileTwo I/O Cells form I/O Tile
Dedicated shift routing for Dedicated shift routing for SERDES data width SERDES data width expansionexpansion
Routing to support Routing to support complementary differential complementary differential I/O standardsI/O standards
All I/O Cells are identicalAll I/O Cells are identical10 Flip-Flops10 Flip-Flops32 Multiplexors32 Multiplexors69 I/O Standards69 I/O Standards
More complicated than AtmelMore complicated than Atmel
Input/OutputBuffer
(I/O Buffer)
Input/OutputBuffer
(I/O Buffer)
To/from Device Resources
Input Logic
(ILOGIC)
OutputLogic
(OLOGIC)
From Device Resources
To/From Device Resources
Input Logic
(ILOGIC)
OutputLogic
(OLOGIC)
From Device Resources
I/O Cell
I/O Cell
BSCAN EXTEST Access
B. Dutton 5/15/08B. Dutton 5/15/08 North Atlantic Test WorkshopNorth Atlantic Test Workshop 55
Virtex-4 I/O BIST ArchitectureVirtex-4 I/O BIST ArchitectureDSPs configured as counters to address 18 Kbit DSPs configured as counters to address 18 Kbit
Block RAMsBlock RAMsBlock RAMs store deterministic and Block RAMs store deterministic and
pseudorandom test patternspseudorandom test patternsGreater controllability of test patternsGreater controllability of test patterns
Multiple TPGs address alternating rows of BUTsMultiple TPGs address alternating rows of BUTsBidirectional I/O buffers under test (BUTs)Bidirectional I/O buffers under test (BUTs)
=ORA=TPG =BUT
B. Dutton 5/15/08B. Dutton 5/15/08 North Atlantic Test WorkshopNorth Atlantic Test Workshop 66
Virtex-4 I/O BIST ArchitectureVirtex-4 I/O BIST Architecture
=ORA=TPG
=BUT
DSP
DSP
BRAMs
B. Dutton 5/15/08B. Dutton 5/15/08 North Atlantic Test WorkshopNorth Atlantic Test Workshop 77
ILOGIC/OLOGIC Fault CoverageILOGIC/OLOGIC Fault CoverageCan only test bi-directional buffer modesCan only test bi-directional buffer modes
Two undetected faults resultTwo undetected faults result
0
50
100
150
200
250
300
350
400
450
500
550
1 2 3 4 5 6 7
BIST Configuration #
# F
au
lts
De
tec
ted
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
% F
au
lt C
ov
era
ge
Individual FC
Cumulative FC
B. Dutton 5/15/08B. Dutton 5/15/08 North Atlantic Test WorkshopNorth Atlantic Test Workshop 88
SERDES OverviewSERDES OverviewOQ1Q2Q3Q4Q5Q6
ISERDES
D
D1D2D3D4D5D6
OSERDES
Q
T1T2T3T4
T
CLKCLKDIVOCEREVSHIFTIN1SHIFTIN2SRTCE
SHIFTOUT1SHIFTOUT2
SHIFTIN1SHIFTIN2
SHIFTOUT1SHIFTOUT2
CLKCLKDIVBITSLIP
CE1CE2
DLYCEDLYINCDLYRST
SROCLK
REV
TO FPGA INTERNAL
RESOURCES
FROM FPGA INTERNAL
RESOURCES
InputBuffer
OutputBuffer
PAD
I/O Buffer
FROM FPGA INTERNAL
RESOURCESTO OTHER ISERDES
IN I/O TILE
TO OTHER OSERDES IN I/O TILE
OSERDES:parallel to serial conversion
ISERDES:serial to parallel conversion
B. Dutton 5/15/08B. Dutton 5/15/08 North Atlantic Test WorkshopNorth Atlantic Test Workshop 99
SERDES BIST ConfigurationsSERDES BIST ConfigurationsSERDES requires more TPG and ORA linesSERDES requires more TPG and ORA lines
Solution: Block RAMs configured as 512x36bitSolution: Block RAMs configured as 512x36bitReduces total test vector count to 512Reduces total test vector count to 512
7 outputs per ISERDES require 7 ORAs7 outputs per ISERDES require 7 ORAsData serialization/deserialization requires high Data serialization/deserialization requires high
speed clockspeed clockSolution: instantiate clock divide circuitry and use the Solution: instantiate clock divide circuitry and use the
divided clock for TPGs and ORAsdivided clock for TPGs and ORAsAmount of clock division depends on the data widthAmount of clock division depends on the data width
Deserialized data must be identically aligned on Deserialized data must be identically aligned on ISERDES parallel outputsISERDES parallel outputsSolution: add a training pattern to vector set and a Solution: add a training pattern to vector set and a
Bitslip synchronizer circuitBitslip synchronizer circuit
B. Dutton 5/15/08B. Dutton 5/15/08 North Atlantic Test WorkshopNorth Atlantic Test Workshop 1010
SERDES BIST ConfigurationsSERDES BIST ConfigurationsBitslip operation Bitslip operation
reorders deserialized reorders deserialized data on inputsdata on inputsBitslip synchronizer Bitslip synchronizer
circuit aligns deserialized circuit aligns deserialized data prior to BISTdata prior to BIST
Synchronizer EN line Synchronizer EN line enables/disables circuitenables/disables circuit
D Q
CLR
D Q
CLR
D Q
CLRX Y Z
To ISERDESISERDES Q2
CLKDIV
Synchronizer Enable from TPG
TPG Bitslip
Clock CycleClock Cycle InitInit 11 22 33 44 55 66 77 88 99
ISERDES Q2ISERDES Q2 1 1 1 1 1 1 0 0 0 0
XX FFFF X 0 1 1 1 0 1 0 0 0
Y FFY FF X 0 0 1 1 0 0 1 0 0
Z FFZ FF 1 0 0 0 1 0 0 0 1 0
BITSLIPBITSLIP 0 0 0 1 0 0 0 0 0 0
B. Dutton 5/15/08B. Dutton 5/15/08 North Atlantic Test WorkshopNorth Atlantic Test Workshop 1111
I/O StandardsI/O Standards I/O Standards are tested I/O Standards are tested
with ILOGIC/OLOGIC with ILOGIC/OLOGIC architecturearchitecture 69 I/O standards, 9 are not 69 I/O standards, 9 are not
bidirectionalbidirectional Four classes of I/O Four classes of I/O
standardsstandards Single ended with Vref Single ended with Vref
require an external require an external reference voltage supplied reference voltage supplied to one I/O buffer per 16 I/Oto one I/O buffer per 16 I/O
DCI requires two external DCI requires two external reference resistors in each reference resistors in each I/O bank (64 I/O)I/O bank (64 I/O)
Complementary Complementary differential requires some differential requires some modification of the modification of the template architecturetemplate architecture
Source Lines Destination
a) single ended
Input BufferOutput Buffer
c) complementary differential(requires two I/O cells)
DifferentialInput Buffer
Output Buffer i
Output Buffer j
d) digitally controlled impedance (DCI)(single or split termination at source,
destination, or both)
VREF
DifferentialInput Buffer
Output Buffer
b) single ended requiring VREF
(1 VREF per 16 I/O buffers)
Input Bufferz
R
Output Buffer R
R
VCCOVCCO
R
B. Dutton 5/15/08B. Dutton 5/15/08 North Atlantic Test WorkshopNorth Atlantic Test Workshop 1212
BIST Configuration SummaryBIST Configuration SummaryI/OI/O
BISTBISTArchitectureArchitecture
# of # of BISTBIST
ConfigurationsConfigurations
Total BISTTotal BIST Clock CyclesClock Cycles
(constant)(constant)
Total DownloadTotal Download Size (Kbits)*Size (Kbits)*
(varies w/ size)(varies w/ size)
ILOGIC/OLOGICILOGIC/OLOGIC 88 81928192 4,0344,034
SERDESSERDES 88 19,12419,124 10,38410,384
I/O StandardsI/O Standards 6262 496496 5,8285,828
TOTALTOTAL 7878 27,81227,812 20,24620,246
**Configuration file size for SX35 using compressed configuration files and Configuration file size for SX35 using compressed configuration files and partial reconfiguration filespartial reconfiguration files
I/O Standards configurationsI/O Standards configurations Less than 30% of configuration bitsLess than 30% of configuration bits Less than 2% of BIST clock cyclesLess than 2% of BIST clock cycles
78 configurations, but smaller than 6 full downloads78 configurations, but smaller than 6 full downloads Total test time = 405 msec for SX35Total test time = 405 msec for SX35
B. Dutton 5/15/08B. Dutton 5/15/08 North Atlantic Test WorkshopNorth Atlantic Test Workshop 1313
Virtex-4 I/O BIST Configuraiton Virtex-4 I/O BIST Configuraiton Generation ProgramsGeneration Programs
Three XDL template file generation programsThree XDL template file generation programsV4iobistV4iobist – ILOGIC, OLOGIC, I/O buffer logic resources – ILOGIC, OLOGIC, I/O buffer logic resourcesV4iobistiosV4iobistios – SERDES logic resources – SERDES logic resourcesV4iobistdV4iobistd – complementary differential I/O standards – complementary differential I/O standards
Three XDL modification programs Three XDL modification programs V4iobmodV4iobmod - ILOGIC, OLOGIC, I/O buffer logic - ILOGIC, OLOGIC, I/O buffer logic
resourcesresourcesV4iobmodiosV4iobmodios – SERDES logic resources – SERDES logic resourcesV4iobrmodV4iobrmod – I/O standards – I/O standards
B. Dutton 5/15/08B. Dutton 5/15/08 North Atlantic Test WorkshopNorth Atlantic Test Workshop 1414
BIST Configuration Generation ProcessBIST Configuration Generation Process
BIST Programs
BitGen.exe
BIT file
XDL file
NCD file
XDL.exe
download
FPGA Editor
verification on FPGA
XDL: Xilinx XDL: Xilinx Description Description LanguageLanguage
Can generate Can generate configurations for configurations for every Virtex-4 every Virtex-4 device in any device in any packagepackageFX12 not currently FX12 not currently
supported due to supported due to only 1 column of only 1 column of BRAMs in Power BRAMs in Power PC rowsPC rows
B. Dutton 5/15/08B. Dutton 5/15/08 North Atlantic Test WorkshopNorth Atlantic Test Workshop 1515
All I/O Buffers Under Test in Virtex-4 FX20 All I/O Buffers Under Test in Virtex-4 FX20 as viewed in Xilinx FPGA Editoras viewed in Xilinx FPGA Editor
BRAMs for TPGs
I/O tiles under test and
corresponding ORAs
DSPs for TPGs
B. Dutton 5/15/08B. Dutton 5/15/08 North Atlantic Test WorkshopNorth Atlantic Test Workshop 1616
SummarySummary3 architectures in 78 configurations to test 3 architectures in 78 configurations to test
I/O cells in every mode of operationI/O cells in every mode of operationILOGIC/OLOGICILOGIC/OLOGICISERDES/OSERDESISERDES/OSERDESI/O StandardsI/O Standards
Tests both bonded and unbonded I/O cellsTests both bonded and unbonded I/O cellsCan be used for manufacturing or system Can be used for manufacturing or system
level testinglevel testingConnecting devices should be tri-statedConnecting devices should be tri-stated
Allows for testing at system frequenciesAllows for testing at system frequencies
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