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Bring IP verification closure to SoCScalable Methods to Bridge the Gap between IP and SoC Verification
Speaker – Gaurav Gupta
Authors - Gaurav Gupta, Tejbal Prasad, Rohit Goyal
(Automotive Industrial Solutions GroupFreescale Semiconductor
Noida, India)
Dec 1, 2015
Motivation
Processor runs ‘C’ code that provides instructions
Processor controls the operation : data movement, timing
No link between testbench and the processor
Can testbench provide ‘instructions’ that processor executes ?
IP
IP Sequences
Sequencer
(UVM)
BFMs
IP Verification Environment
IP
‘C’
Patterns
Processor Core
PBRIDGE
SOC Verification Environment
Re-use IP Sequences at system level
Eliminate Duplicity
Easier to control interdependent interactions among various functional
units
Bridging the Gap
Adapter
Porthole
(Buffer in SRAM, to
enable HW/SW
communicat-ion)
CPU waits for an
instruction to be
available in porthole
RAL transaction is converted into an instruction to CPU
CPU picks up the instruction and executes it
CPU writes back the result after the execution of an instruction
UVM RAL transaction
(cmd)RAL transaction (read or write), blocks till it gets result of the execution
Adapter picks up the result from Porthole
Adapter passes result to RAL and unblocks it to execute next instruction
IP Sequence
CPU
PBRIDGE
Proposed environment
Adapter
(HW/SW Communication)
API
Sequencer
(UVM)
(C-file for Configsequences)
IP
Bridging the Gap
Adapter
Porthole
(Buffer in SRAM, to
enable HW/SW
communicat-ion)
CPU waits for an
instruction to be
available in porthole
RAL transaction is converted into an instruction to CPU
CPU picks up the instruction and executes it
CPU writes back the result after the execution of an instruction
UVM RAL transaction
(cmd)RAL transaction (read or write), blocks till it gets result of the execution
Adapter picks up the result from Porthole
Adapter passes result to RAL and unblocks it to execute next instruction
IP Sequence
CPU
PBRIDGE
Proposed environment
Adapter
(HW/SW Communication)
API
Sequencer
(UVM)
Make a C – program / tests
IP
IP Sequence
CPU
PBRIDGE
Execution through UVM Sequence
Adapter
(HW/SW Communication)
API
(C-file)
Sequencer
(UVM)
IP
‘C ‘
Programs
CPU
PBRIDGE
Adapter
(HW/SW Communication)
Sequencer
(UVM)
Execution through ‘C’ Patterns
(C-file for Configsequences)
IP
Bridging the GapExecution of Read and Write
Source: http://dvcon-india.org/wp-content/uploads/2014/proceedings/1400-1530/D2A1-2-1-DV_Bring_IP_Verification_Closer_Paper.pdf
Set by Processor, Read by Adapter
Set by Adapter, Read by Processor
Clear by Adapter
Set and Clear by Adapter
RD/WR PORTHOLE BUFFER
SV_FLAG
TRANS_TYPE
TRANS_ADDR
TRANS_DATA
RESULT
ADAPTER
UVM RAL (cmd)
CPU
C_FLAG
Case Study : Processing Flow
Generate global configuration and
Configure components 1/2
component_*_global_cfg_sequence
Run component_*_cfg_sequence on respective sequencers / UVM RAL
Start image transfer from camera i/f
Run csi2_ sequence on respective sequencer
Pole on a register bit until required data is
processed
UVM RAL
Process Data -> Trigger components 1/2 to start
processing data
Run trigger_component_*_sequenceon respective sequencers / UVM
RAL
Execution in proposed flow
Start image transfer from camera i/f
Run csi2_ sequence on respective sequencer
Wait for processor to finish execution
wait_for_core_exec_seq.start(p_sequencer)
Run ‘C’ code on CPU to configure components and to control the data
movement
Load ‘HEX’ file of compiled code
Execution in traditional flow
System under Verification
Benefits and ApplicationsGenerating a Performance Matrix for the Components
Sequence .. 1
Sequence .. n
Sequence Graphs / Portable Stimulus Easy Stimulus
Creation re-using IP sequences
Easy to control and visualize parallel
threads, complex tests
Benefits and ApplicationsGenerating a Performance Matrix for the Components
Coverage
Sequence .. 1
Sequence .. n
Sequence Graphs / Portable Stimulus Easy Stimulus
Creation re-using IP sequences
Easy to control and visualize parallel
threads, complex tests
Randomization capabilities and easier
tests creation aids to get better coverage quickly
Benefits and ApplicationsGenerating a Performance Matrix for the Components
Coverage
Sequence .. 1
Sequence .. n
Sequence Graphs / Portable Stimulus Easy Stimulus
Creation re-using IP sequences
Easy to control and visualize parallel
threads, complex tests
Randomization capabilities and easier
tests creation aids to get better coverage quickly
CPU 0
CPU n
CPU 1
|
Adapter 0
Adapter 1
Adapter n
OR
CPU 0
CPU n
CPU 1
|
SC
HE
DU
LE
R
Adapter
Scalable to multiple CPUs
Benefits and ApplicationsGenerating a Performance Matrix for the Components
Conclusion
‘Stimulus Portability’ can be achieved with simple solution; Avoid duplicity; Validation could also be a beneficiary
Greater control on overall verification – Randomization, threading etc.
The methods described in this presentation are scalable and re-usable with easy implementation
Opens a whole new dimension for testbench (UVM) controlled “System Level Verification”
Testbenchcontrolled
CPU execution
Replace RAL adapter to put an instruction into Memory
instead of driving to the register bus
Execute a simple ‘C’ program on CPU to fetch dynamic instructions from Memory
Constrained Random CPU acts as a Slave
Questions ?
BACKUPs
Flow Chart of Communication
UVM RAL transaction
(cmd)
Adapter writes an instruction to porthole buffer and then waits for CPU to execute it by polling on porthole location ‘SV_FLAG’ to be set to the value defined as ‘FLAG_SET_VAL’
Adapter writes an instruction to porthole buffer and then waits for CPU to execute it by polling on porthole location ‘SV_FLAG’ to be set to the value defined as ‘FLAG_SET_VAL’
Write Read
CPU picks up the instruction from porthole buffer and executes it. After execution of the instruction, CPU writes a PASS/FAIL signature on the porthole location ‘RESULT’ and sets porthole location ‘SV_FLAG’ to value defined as ‘FLAG_SET_VAL’ in porthole buffer
Adapter then clears all the flags and RESULT
CPU picks up the instruction from porthole buffer and executes it. After execution of the instruction, CPU writes read data to the porthole location ‘TRANS_DATA’, writes a PASS/FAIL signature on ‘RESULT’ and sets ‘SV_FLAG’ to ‘FLAG_SET_VAL’ in porthole buffer
Adapter then return data from the porthole location ‘TRANS_DATA’ to UVM RAL command and clears all the flags and RESULT
C – Code : To run on CPU
Adapter Implementation
C – Program : Using Adapter
User needs to create such ‘control statements’ manually as it needs to be declared in ‘C’ and may differ from how this would have been done in SV
Adapter dumps RAW ‘C’ files for each component containing generated instructions. Appropriate comments are embedded to help user to create a meaningful program combining these RAW ‘C’ files
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