block diagrams
Post on 25-Feb-2016
39 Views
Preview:
DESCRIPTION
TRANSCRIPT
Block Diagrams
Top-Level Circuit for Lab 4, Tasks 2-4
rstclkenCNTR
UP
rstclken
MISR
ldrst clk
enLFSR
X”00” 8
8
8
IVBloadB
rstOR
loadB
nexti
10cnz
ldrst clk
enLFSR
X”00” 8
8
8
IVAloadA
rstOR
loadA
10cnz
clkclk
LAB2
A B
X Y
sel
En ‘0’
8
clkrst
8
YSGN
nexti
nextorst
clken
MISR
8
clkrst
8
XSGN
nexto
10k
k9..8
2k7..0
8
≠ 0
cnz
= X”3FF”10
done
rstclk
nexto
OR
AND not done
nexto
step run
AND
cnz
LAB3
Top-Level Circuit for Lab 4, Tasks 5 & 6
Top-Level Unit for Lab 4, Tasks 5 & 6entity lab4 is port( CLOCK : in std_logic; BTNL : in std_logic; BTNR : in std_logic; BTNU : in std_logic; BTNS : in std_logic; BTND : in std_logic; SW : in std_logic_vector(7 downto 0); LED : out std_logic_vector(7 downto 0); SEG : out std_logic_vector(6 downto 0); AN : out std_logic_vector(3 downto 0)););end entity lab4;
LAB4 for TASK5BTNL BTNR BTNU BTND BTNS
loadA loadB step run
BTNL BTNR BTNU BTND BTNS
loadA loadB step run
BUTTON_UNIT SWITCH_UNITSW
SW
IVA IVB
LAB3e
SEG AN
SEG AN
hex0hex1hex2hex3
hex0hex1hex2hex3
SSD_DRIVER
XSGN YSGN Xout Yout Aout Bout k
XSGN YSGN X Y A B k
next_out
LED
LED
TASK5
CLOCK
CLK_RST_1
BTNR
clk rst
clk rst
clk
rst
clkrst
clkrst
8
8 8
88 8 8 8 8
8 7 4
4444
10
BTNL
rstclkenCNTR
UP
rstclken
MISR
ldrst clk
enLFSR
X”00” 8
8
8
IVBloadB
rstOR
loadB
nexti
10cnz
ldrst clk
enLFSR
X”00” 8
8
8
IVAloadA
rstOR
loadA
10cnz
clkclk
LAB2
A B
X Y
sel
En ‘0’
8
clkrst
8
YSGN
nexti
nextorst
clken
MISR
8
clkrst
8
XSGN
nexto
10k
k9..8
2k7..0
8
≠ 0
cnz
= X”3FF”10
done
rstclk
nexto
OR
AND not donenexto
step run
AND
cnz
LAB3eXout Aout
A8 8
B8 8
Yout
8
Bout kout
10k
BTNL
BTNS
Debouncer RED loadA
Debouncer RED
runD Q‘1’en
rst
clk
rst
clk
BTNR Debouncer RED loadBrst
clk
rst
clk
rst
clk
rst
clk clk
BUTTON_UNIT
BTNU Debouncer RED steprst
clk
rst
clk
BTND Debouncer RED next_outrst
clk
rst
clk rst
SW IVA
SWITCH_UNIT
IVB
8 8
8
CLOCK
BTNL
CLK_RST_1
BTNRrst
clk
Counter UPCOUNTER UP
Counter UP
q(k-1..k-2)
AN
Counter UP
SEG(6..0)
Counter UP
Counter UPrst
clkOC
SSD_DRIVER
OC – One’s Complement
LAB4 for TASK6BTNL BTNR BTNU BTND BTNS
loadA loadB step run
BTNL BTNR BTNU BTND BTNS
loadA loadB step run
BUTTON_UNIT SWITCH_UNITSW
SW
IVA IVB
LAB3e
SEG AN
SEG AN
hex0hex1hex2hex3
hex0hex1hex2hex3
SSD_DRIVER
XSGN YSGN Xout Yout Aout Bout k
XSGN YSGN X Y A B k
next_out
LED
LED
TASK5
CLOCK
CLK_RST_2
BTNR
clk rst
clk rst
clk
rst
clkrst
clkrst
8
8 8
88 8 8 8 8
8 7 4
4444
10
BTNL
DCM_SPIBUFG BUFGCLOCK
locked
clk_ibufg clk100
rst
clkin
clkfb
clk0
rstBTNL
BTNRrst_or
clkfxclkFX
clkBUFGclkfx_obufg
clk0_obufg
‘0’
0
1
CLK_RST_2
BUFGMUX
User Constraint File (UCF)
User Constraint File (UCF) - LEDs# LEDs
NET "LED<0>" LOC = "U16" | IOSTANDARD = "LVCMOS33";
NET "LED<1>" LOC = "V16" | IOSTANDARD = "LVCMOS33";
NET "LED<2>" LOC = "U15" | IOSTANDARD = "LVCMOS33";
NET "LED<3>" LOC = "V15" | IOSTANDARD = "LVCMOS33";
NET "LED<4>" LOC = "M11" | IOSTANDARD = "LVCMOS33";
NET "LED<5>" LOC = "N11" | IOSTANDARD = "LVCMOS33";
NET "LED<6>" LOC = "R11" | IOSTANDARD = "LVCMOS33";
NET "LED<7>" LOC = "T11" | IOSTANDARD = "LVCMOS33";
User Constraint File (UCF) - SSD# Seven Segment DisplaysNET "SEG<0>" LOC = "T17" | IOSTANDARD = "LVCMOS33"; NET "SEG<1>" LOC = "T18" | IOSTANDARD = "LVCMOS33"; NET "SEG<2>" LOC = "U17" | IOSTANDARD = "LVCMOS33";NET "SEG<3>" LOC = "U18" | IOSTANDARD = "LVCMOS33"; NET "SEG<4>" LOC = "M14" | IOSTANDARD = "LVCMOS33"; NET "SEG<5>" LOC = "N14" | IOSTANDARD = "LVCMOS33"; NET "SEG<6>" LOC = "L14" | IOSTANDARD = "LVCMOS33";NET "AN<0>" LOC = "N16" | IOSTANDARD = "LVCMOS33"; NET "AN<1>" LOC = "N15" | IOSTANDARD = "LVCMOS33";NET "AN<2>" LOC = "P18" | IOSTANDARD = "LVCMOS33";NET "AN<3>" LOC = "P17" | IOSTANDARD = "LVCMOS33";
User Constraint File (UCF) Switches
# Switches
NET "SW<0>" LOC = "T10" | IOSTANDARD = "LVCMOS33";
NET "SW<1>" LOC = "T9" | IOSTANDARD = "LVCMOS33";
NET "SW<2>" LOC = "V9" | IOSTANDARD = "LVCMOS33";
NET "SW<3>" LOC = "M8" | IOSTANDARD = "LVCMOS33";
NET "SW<4>" LOC = "N8" | IOSTANDARD = "LVCMOS33";
NET "SW<5>" LOC = "U8" | IOSTANDARD = "LVCMOS33";
NET "SW<6>" LOC = "V8" | IOSTANDARD = "LVCMOS33";
NET "SW<7>" LOC = "T5" | IOSTANDARD = "LVCMOS33";
# Buttons
NET "BTNS" LOC = "B8" | IOSTANDARD = "LVCMOS33"; BTNS
NET "BTNU" LOC = "A8" | IOSTANDARD = "LVCMOS33"; BTNU
NET "BTNL" LOC = "C4" | IOSTANDARD = "LVCMOS33"; BTNL
NET "BTND" LOC = "C9" | IOSTANDARD = "LVCMOS33"; BTND
NET "BTNR" LOC = "D9" | IOSTANDARD = "LVCMOS33"; BTNR
User Constraint File (UCF) Buttons
# Buttons
NET "CLOCK" LOC = "V10" | IOSTANDARD = "LVCMOS33";
User Constraint File (UCF) CLOCK
Seven Segment Displays
4-Digit Seven Segment Display
Patterns for Decimal Digits
Patterns for Hexadecimal Digits
Connection to FPGA Pins
Multiplexing Digits
Time-Multiplexed Seven Segment Display
Counter UPCOUNTER UP
Counter UP
q(k-1..k-2)
AN
Counter UP
SEG(6..0)
Counter UP
Counter UPrst
clkOC
SSD_DRIVER
OC – One’s Complement
Size of the counter
2k * TCLK ≈ 16 ms
fCLK = 100 MHz
k = ?
Digital Clock Managers and
Variable Clock Frequency
Clock Management
• Clock sources are generated off of the FPGA• Clock source needs to enter the FPGA• Clock needs to be “de-jittered”
– Clock naturally has non-constant duty cycle and period
• Clock needs to reach the rest of the chip
Clock Management
• Ideal clock has one frequency
• Clock jitter is the undesired deviation in the timing of clock edges
• We can see the jitter in the top (yellow) trace
• Blue clock is de-jittered
Clock Management
• CLOCK Enters FPGA and enters IBUFG• Output of BUFGMUX goes to the rest of the FPGA• Invert of LOCKED signal is used as a reset for the top-level circuit• To simulate, include the following lines in the library section
– library UNISIM;– use UNISIM.vcomponents.all;
DCM_SPIBUFG BUFGCLOCK
locked
clk_ibufg clk100
rst
clkin
clkfb
clk0
rstBTNL
BTNRrst_or
clkfxclkFX
clkBUFGclkfx_obufg
clk0_obufg
‘0’
0
1
BUFGMUX
Digital Clock Manager
• DCM can also change clock frequency
• CLK2X doubles frequency
• CLKDV and CLKFX change the frequency based on the generics (see instantiation)
Digital Clock Manager
Digital Clock Manager
DCM_SP_inst : DCM_SPgeneric map ( CLKDV_DIVIDE => 2.0,-- CLKDV divide value-- (1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,7,7.5,8,9,10,11,12,13,14,15,16).-- Divide value on CLKFX outputs - D - (1-32)-- Multiply value on CLKFX outputs - M - (2-32)-- CLKIN divide by two (TRUE/FALSE)-- Input clock period specified in nS-- Output phase shift (NONE, FIXED, VARIABLE)-- Feedback source (NONE, 1X, 2X)CLKFX_DIVIDE => ………….,CLKFX_MULTIPLY => ………,CLKIN_DIVIDE_BY_2 => FALSE,CLKIN_PERIOD => 10.0,CLKOUT_PHASE_SHIFT => "NONE",CLK_FEEDBACK => "1X”,
DCM_SP Instantiation (1)
-- SYSTEM_SYNCHRNOUS or SOURCE_SYNCHRONOUSDESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
-- Unsupported generics - Do not change value DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW", DSS_MODE => "NONE", DUTY_CYCLE_CORRECTION => TRUE, FACTORY_JF => X"c080", PHASE_SHIFT => 0, STARTUP_WAIT => FALSE
-- Amount of fixed phase shift (-255 to 255) PHASE_SHIFT => 0,-- Delay config DONE until DCM_SP LOCKED (TRUE/FALSE) STARTUP_WAIT => FALSE)
DCM_SP Instantiation (2)
port map (
CLK0 => …………., -- 0 degree clock output
CLK180 => open, -- 180 degree clock output
CLK270 => open, -- 270 degree clock output
CLK2X => open, -- 2X clock frequency clock output
CLK2X180 => open, -- 2X clock frequency 180 degree clock output
CLK90 => open, -- 90 degree clock output
CLKDV => open, -- Divided clock output
CLKFX => …………, -- Digital Frequency Synthesizer (DFS) output
CLKFX180 => open, -- 180 degree CLKFX output
LOCKED => …………, -- DCM_SP Lock Output
DCM_SP Instantiation (3)
PSDONE => open, -- Phase shift done output
STATUS => open, -- DCM_SP status output
CLKFB => …………., -- Clock feedback input
CLKIN => ………….., -- Clock input
DSSEN => ‘0’, -- Unsupported, specify to GND
PSCLK => clk_ibufg, -- Phase shift clock input
PSEN => ‘0’, -- Phase shift enable
PSINCDEC => ‘0’ , -- Phase shift increment/decrement input
RST => ………… -- Active high reset input
);
DCM_SP Instantiation (4)
Library and Package
In order to compile, simulate and synthesize a circuit including DCM_SP, you need to includein the top-level circuit:
library UNISIM;use UNISIM.vcomponents.all;
Clock Buffers
IBUFG_inst : IBUFG generic map ( IOSTANDARD => "DEFAULT") port map ( O => O, I => I);
• Dedicated clock route for reaching a DCM and the rest of the chip• Should be used for a clock port
BUFG_inst : BUFG port map ( O => O, I => I);
• Dedicated clock route for reaching the rest of the chip at the same time• Should be used for all generated clocks
– Output from DCM– Output from clock divider circuits
Clock Multiplexer
BUFGMUX_inst : BUFGMUXgeneric map (
CLK_SEL_TYPE => "SYNC" -- Glitchles ("SYNC") or fast ("ASYNC") clock switch-over
)port map (
O => …….., -- 1-bit output: Clock buffer output I0 => …….., -- 1-bit input: Clock buffer input (S=0) I1 => …….., -- 1-bit input: Clock buffer input (S=1) S => ……… -- 1-bit input: Clock buffer select
);
top related