avishai wool lecture 8 - 1 introduction to systems programming lecture 8 input-output

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Introduction to Systems Programming Lecture 8

Input-Output

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Devices, Controllers, and I/O Architectures

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I/O Device Types

• Block Devices– block size of 512-32768 bytes– block can be read/written individually– typical: disks / floppy / CD

• Character Devices– delivers / accepts a sequential stream of characters– non-addressable – typical: keyboard, mouse, printer, network

• Other: Monitor, Clock

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Typical Data Rates

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Device Controllers

• I/O devices have components:– mechanical component – electronic component

• The electronic component is the device controller– may be able to handle multiple devices

• Controller's tasks– convert serial bit stream to block of bytes– perform error correction as necessary– make available to main memory

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Communicating with Controllers

• Controllers have registers to deliver data, accept data, etc.

• Option 1: special I/O commands, I/O ports in r0, 4

• “4” is not memory address 4, it is I/O port 4

• Option 2: I/O registers mapped to memory addresses

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Memory-Mapped Registers

• Controller connected to the bus

• Has a physical “memory address” like B0000000

• When this address appears on the bus, the controller responds (read/write to its I/O register)

• RAM configured to ignore controller’s address

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Possible I/O Register Mappings

• Separate I/O and memory space (IBM 360)• Memory-mapped I/O (PDP-11)• Hybrid (Pentium, 640K-1M are for I/O)

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Advantages of Memory Mapped I/O

• No special instructions, can be written in C.

• Protection by not putting I/O memory in user virtual address space.

• All machine instructions can access I/O:LOOP: test *b0000004 // check if port_4 is 0 beq READY branch LOOP

READY: ...

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Disadvantages of Memory Mapped I/O

• Memory and I/O controllers have to be on the same bus:– modern architectures have separate memory bus!– Pentium has 3 buses: memory, PCI, ISA

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Bus Architectures

(a) A single-bus architecture(b) A dual-bus memory architecture

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Memory Mapped with Separate Bus

• I/O Controllers do not see memory bus.

• Option 1: all addresses to memory bus. No response I/O bus

• Option 2: Snooping device between buses– speed difference is a problem

• Option 3 (Pentium): filter addresses in PCI bridge

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Structure of a large Pentium system

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Principles of I/O Software

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Goals of I/O Software

• Device independence– programs can access any I/O device – without specifying device in advance

· (floppy, hard drive, or CD-ROM)

• Uniform naming– name of a file or device a string or an integer– not depending on which machine

• Error handling– handle as close to the hardware as possible

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Goals of I/O Software (2)

• Synchronous vs. asynchronous transfers– blocked transfers vs. interrupt-driven

• Buffering– data coming off a device cannot be stored in final

destination

• Sharable vs. dedicated devices– disks are sharable– tape drives would not be

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How is I/O Programmed

• Programmed I/O

• Interrupt-driven I/O

• DMA (Direct Memory Access)

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Programmed I/O

Steps in printing a string

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Polling

Busy-waiting until device can accept another character

Example assumes memory-mapped registers

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Properties of Programmed I/O

• Simple to program

• Ties up CPU, especially if device is slow

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Interrupts Revisited

bus

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Interrupt-Driven I/O

Code executed when print system call is made

Interrupt service procedure

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Properties of Interrupt-Driven I/O

• Interrupt every character or word.

• Interrupt handling takes time.

• Makes sense for slow devices (keyboard, mouse)

• For fast device: use dedicated DMA controller – usually for disk and network.

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Direct Memory Access (DMA)

• DMA controller has access to bus.

• Registers:– memory address to write/read from– byte count– I/O port or mapped-memory address to use– direction (read from / write to device)– transfer unit (byte or word)

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Operation of a DMA transfer

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I/O Using DMA

code executed when the print system call is made

interrupt service procedure

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DMA with Virtual Memory

• Most DMA controllers use physical addresses

• What if memory of buffer is paged out during DMA transfer?

• Force the page to not page out (“pinning”)

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Burst or Cycle-stealing

• DMA controller grabs bus for one word at a time, it competes with CPU bus access. This is called “cycle-stealing”.

• In “burst” mode the DMA controller acquires the bus (exclusively), issues several transfers, and releases. – More efficient – May block CPU and other devices

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Concepts for review• TLB

• Local/Global page replacement

• Demand paging

• Page-fault-frequency monitor

• I/O device controller

• in/out commands

• Memory-mapped registers

• PCI Bridge

• Programmed I/O (Polling)

• Interrupt-driven I/O

• I/O using DMA

• Page pinning

• DMA cycle-stealing

• DMA burst mode