a.r. hertneky j.w. o’brien j.t. shin c.s. wessels laser controller one (lc1)
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January 31, 2006 Preliminary Design Review (PDR) 2
Outline
• Background• Functionality• Block diagrams/sub-
systems• Parts list/budget• Schedule/division of labor• Risk analysis
January 31, 2006 Preliminary Design Review (PDR) 3
Background
• Physics experiments often require laser cooling– Bose-Einstein
Condensate (BEC)– atomic fountain clock
• Laser wavelength locked to hyperfine transition– analog control system– Doppler-free saturated
absorption spectroscopy (sat spec)
January 31, 2006 Preliminary Design Review (PDR) 4
Background
• Establishing/maintaining lock is operator intensive– non-intuitive– manual system
monitoring required
• Incompatible with automated lab equipment
January 31, 2006 Preliminary Design Review (PDR) 5
Functionality
• Auto-magically scans atomic spectrum
• Identifies absorption peaks
• Operator selects a reference peak
• Configures analog control equipment
• Lock is engaged
January 31, 2006 Preliminary Design Review (PDR) 6
Functionality
A manual operator would…• observe erroneous
behavior in experiment• discover broken lock
through troubleshooting• repeat procedure to
establish lock from scratch
Our device will…• sense problem• recalibrate and
reestablish the lock• return to normal
operation within seconds
If the lock is lost
January 31, 2006 Preliminary Design Review (PDR) 7
User Interface
• Front panel status– LCD
• available absorption peaks• currently selected reference peak• time since last lock status change
– Two-color LED• quick visual: locked/unlocked
– Keypad or dial• choose peak and initiate automatic behavior
January 31, 2006 Preliminary Design Review (PDR) 8
Hardware Environment
Laser /Saturated Absorption
SpectroscopyLoop Filter Peak Lock
Laser Controller One (LC1)
Switch
January 31, 2006 Preliminary Design Review (PDR) 9
External Connections
Laser Controller One (LC1)
Spectrum Output(Saturated Absorption
Spectroscopy)
Error Offset Monitor(Loop Filter)
Error Monitor(Peak Lock)
Offset Control(Loop Filter)
Sweep(Loop Filter)
Switch(Peak Lock/Loop Filter)
LegendInput
Output
Digital Interconnect
Analog Interconnect
January 31, 2006 Preliminary Design Review (PDR) 10
Hardware Subsystems
Laser Control One (LC1)
A/D D/A
LCDDisplay
CPU
FPGADigilent Spartan 3 Development
Board
FlashMemory
InputDevice
(Dial/Keypad)
Bus
UART OtherIP
1MBSRAM
January 31, 2006 Preliminary Design Review (PDR) 11
Microcontroller
Freescale M683XX Microcontroller• Clock speeds for wire wrapped prototype (8-
12MHz) and PCB integration (15-20MHz) • Integrated Memory Controller• LQFP 144, PQFP 132, QFP 144 Packages
January 31, 2006 Preliminary Design Review (PDR) 12
FPGA Module
Digilent Spartan-3 Starter Board
• XC3S1000 Core• 1000k gate version• 1 Megabyte of SRAM• 2 Megabits of platform
flash• 50 MHz oscillator• 3 x 40-pin I/O headers
January 31, 2006 Preliminary Design Review (PDR) 13
Optional FPGA Sub-modules
• Memory (Flash/SRAM)• Test Point Header• Serial I/O• R2R Module (8-bit DAC up to 25MHz)• Two A/D 12-bit converter chips• Two D/A 8-bit converter chips• RS232 converter• Four high bright LEDs• 6-pin header to two BNC connectors
January 31, 2006 Preliminary Design Review (PDR) 14
Software/Hardware Division
CPU•User Interface
– LCD Display– Keypad
•Remote control•System management
FPGA•Laser control interaction•Signal processing•Application specific functions•System monitoring
January 31, 2006 Preliminary Design Review (PDR) 15
Estimated Cost
Component Price2 Spartan3 FPGA Boards $150.00 eaPCB etching (2 revisions) $200.00LCD $300.00Power Supply $100.00Keypad/Dial $25.00Chassis $100.00Flash Memory $50.00Misc/Unforeseen Expenses $225.00Total $1,300.00
January 31, 2006 Preliminary Design Review (PDR) 16
Risks and Contingency Plan• Risks
– unfamiliarity with DSP and control systems– system and algorithmic complexity– integration with automated environment a
large task• Contingencies
– utilize classmates and instructors– modularize and reduce interdependencies– limit project scope
January 31, 2006 Preliminary Design Review (PDR) 18
Project Responsibilities• A.R. Hertneky
– PCB layout, FPGA development, laser system modifications
• J.W. O’Brien– System-level software, chassis/UI design, test
procedure design• J.T. Shin
– Analog interfaces, FPGA on-chip peripherals, peripheral simulation
• C.S. Wessels– Graphical LCD driver, FPGA development, boot
loader and CPU firmware
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