applied innovative power electronics · 2020. 5. 28. · little box 1.0 converter topology zvs of...

Applied Innovative Power ElectronicsJ. W. Kolar, et al.

Swiss Federal Institute of Technology (ETH) ZurichPower Electronic Systems Laboratorywww.pes.ee.ethz.ch

Applied Innovative Power ElectronicsJ. W. Kolar, D. Neumayr, D. Bortis, J. Huber, R. Burkart, L. Schrittwieser

Swiss Federal Institute of Technology (ETH) ZurichPower Electronic Systems Laboratorywww.pes.ee.ethz.ch

Outline

► 1-Φ Multi-Cell Telecom Rectifier► GOOGLE Little Box 2.0► 3-Φ SiC vs. Si PV Inverter► 3-Φ Buck-Type PFC Rectifier► Outlook

1/40

1-Φ Multi-Cell Telecom Rectifier

Multi-Objective OptimizationHardware Demonstrator 4D-ModulationCap. CouplingSwiss SST

► 1-Φ Multi-Cell Telecom Rectifier

■ Input-Series Output Parallel Arrangement■ Interleaving on Input and Output Side■ Realization Based on LV MOSFETs

Vin = 230V ± 10%Vout = 48V Pout = 3.3kW Thold = 10ms

Multi-Objective Optimization

- Full-Bridge AC/DC Converter- Phase-Shift Full Bridge DC/DC Stage

2/40

► Results of ηρ-Pareto Optimization

■ All Degrees of Freedom Considered ■ 80% Part Load Optimization

- N=6 Converter Cells (550W each)- 100V Si MOSFETs / 4mΩ- AC/DC Cells: 20kHz (120kHz eff.) - DC/DC Cells: 80kHz

Volume & Loss Distribution

3/40

► Hardware Demonstrator

■ Dimensions: 31cm x 11cm x 4.8cm = 1.6dm3

■ 2.1 kW/dm3

Full-System and Power Board

4/40

► Control Concept

■ Master / Slave Control

Control of DC Link Voltages Trough DC/DC Converter Stages

- AC/DC Stages - DC/DC Stages

5/40

► Measurement Results

Peak Efficiency of 97.7% Diff. to Calculation due to PCB Losses etc.

■ Closed-Loop Operation■ Measurements @ Vin=230V, Vout=48V

Pout=1.5kW Pout=2.5kW

6/40

► 4D-Interleaving Operation (1)

■ Utilizing All Degrees of Freedom of the ISOP Multi-Cell Converter Concept

Sinusoidal Mains Voltage – Intervals with Low Modulation Index / Low Power Power Decoupling of Input and Output due to DC Link Caps.

7/40

Permutation of AC/DC and DC/DC Stages for Average Power Balancing

► 4D-Interleaving Operation (2)

■ Utilizing All Degrees of Freedom of the ISOP Multi-Cell Converter Concept

8/40

Optimal Operation of AC/DC Converter w. Single PWM Cell, i.e. 5 Mains-Frequency Sw. Cells Flat DC/DC Converter Efficiency Characteristic

■ Performance Improvements w. 4D-Interleaving

AC/DC Stages DC/DC Stages

9/40

► 4D-Interleaving – Performance Improvement

► GaN vs. Si Power Semiconductor Technology

● Si MOSFETs

● GaN

Further Efficiency Improvement Higher Power Density by 3D-Integration

■ Multi-Objective Optimization

10/40

Substantial Saving of Losses / Volume

■ Phase-Shift or Resonant Operation ■ Cap. Coupled “Sine Amplitude Converter”

● Conventional Transformer-Coupled DC/DCConverter Cell

► Remark #1: Capacitive Coupling ISOP DC/DC Converter

11/40

- 80% Volume and Substantial Saving of Losses

■ Multi-Objective Optimization of Cap. Coupled Phase-Shift Full-Bridge

► Remark #1: Capacitive Coupling ISOP DC/DC Converter

● Transformer

● Series Ind. and CouplingCapacitors

12/40

■ Isolated DC/DC Back End ■ Isolated AC/│AC│Front End

● Conventional ISOP Topology● Direct Input Current Control● Indir. or Direct Output Voltage Control● Controlled or Sine Ampl. Isol. Stage● Distributed DC Link Capacitors● High Complexity

● Swiss SST (S3T)● Indirect Input Current Control● Direct Output Voltage Control● Sine Amplitude Isolation Stage● Single Storage Capacitor● Low Complexity

► Remark #2: Isolated Front-End vs. Isolated Back-End

13/40

“Sine Amplitude Converter”for AC/│AC│Conversion

► Remark #2: Isolated Front-End vs. Isolated Back-End

14/40

Little Box 2.0Full-Bridge DC/AC ConverterDC/│AC│- Converter + Unfolder

“The Ideal Switch is Not Enough” (!)

Little Box 1.0 Converter Topology

■ ZVS of All Bridge Legs @ Turn-On/Turn-Off in Whole Operating Range (4D-TCM Interleaving) ■ Heatsinks Connected to DC Bus / Shield to Prevent Cap. Coupling to Grounded Enclosure

● Interleaving of 2 Bridge Legs per Phase ● Active DC-Side Buck-Type Power Pulsation Buffer● 2-Stage EMI AC Output Filter

15/40

Little Box 1.0 Power Pulsation Buffer

● High Energy Density 2nd Gen. 400VDC CeraLink Capacitors Utilized as Energy Storage● Highly Non-Linear Behavior Opt. DC Bias Voltage of 280VDC● Cap. Losses of 16W @ 2kVA Output Power

■ Effective Large Signal Capacitance of C ≈140μF

- 108 x 1.2μF /400 V- 23.7cm3 Capacitor Volume

27/4816/40

Little-Box 1.0 Prototype (1)

- 8.2 kW/dm3

- 8.9cm x 8.8cm x 3.1cm- 96,3% Efficiency @ 2kW- Tc=58°C @ 2kW

- ΔuDC= 1.1%- ΔiDC= 2.8%- THD+NU = 2.6%- THD+NI = 1.9%

135 W/in3

● DC-Side Power Pulsation Buffer

■ Compliant to All Original Specifications (!)

- No Low-Frequ. CM Output Voltage Component- No Overstressing of Components- All Own IP / Patents

17/40

Little-Box 1.0 Prototype (2)

■ Compliant to All Original Specifications (!)

- No Low-Frequ. CM Output Voltage Component- No Overstressing of Components- All Own IP / Patents

- 8.2 kW/dm3

- 8.9cm x 8.8cm x 3.1cm- 96,3% Efficiency @ 2kW- Tc=58°C @ 2kW

- ΔuDC= 1.1%- ΔiDC= 2.8%- THD+NU = 2.6%- THD+NI = 1.9%

135 W/in3

18/40

● DC-Side Power Pulsation Buffer

Little-Box 1.0 Measurement Results

Output CurrentInductor Current Bridge Leg 1-1Inductor Current Bridge Leg 1-2

DC Link Voltage (AC-Coupl., 2V/Div.)Buffer Cap. VoltageBuffer Cap. Current

Output Voltage- Ohmic Load / 2kW

■ Compliant to All Original Specifications (!)

18/40

● DC-Side Power Pulsation Buffer

Little Box 1.0 X6S Power Pulsation Buffer (1)

● X6S Capacitor Technology Allows Considerable Loss Reduction vs. CeraLink (P2 vs. P7)● Lower Losses / Lower Heatsink Volume Higher Power Density

■ Lower Volume Comp. to Electrolytic Cap. only for ΔV/V < 5% / No Efficiency Benefit

18/40

● X6S Capacitor Technology Allows Considerable Loss Reduction vs. CeraLink (P2 vs. P7) ● Lower Losses / Lower Heatsink Volume Higher Power Density

■ Lower Volume Comp. to Electrolytic Cap. only for ΔV/V < 5% / No Efficiency Benefit

19/40

Little Box 1.0 X6S Power Pulsation Buffer (2)

● Multi-Objective Optimization of Little-Box 1.0 (incl. CeraLink X6S)● Absolute Performance Limits (I) - DSP/FPGA Power Consumption

(II) - Heatsink Volume @ (1-η)

■ Further Performance Improvement for Triangular Current Mode (TCM) PWM

20/40

Little Box 1.0 X6S Power Pulsation Buffer (3)

■ The Ideal Switch is NOT Enough (!) High Frequency Magnetics etc.

Little Box 1.0 @ Ideal Switches ● Multi-Objective Optimization of Little-Box 1.0 (Example: TCM, X6S Power Pulsation Buffer)● Step-by-Step Idealization of the Power Transistors

21/40

Little Box 2.0 – New Converter Topology ● Novel Converter Topology - DC/│AC│- Buck Converter + Unfolder● Temporary PWM of Unfolder for Ensuring Continuous Current Control● TCM or PWM of Buck-Converter

■ Full Optimization of All Converter Options / Idealization of the Switches

22/40

Little Box 2.0 – Multi-Objective Optimization ● Novel Converter Topology - DC/│AC│- Buck Converter + Unfolder● Temporary PWM of Unfolder for Ensuring Continuous Current Control● TCM or PWM of Buck-Converter

■ Full Optimization Allows Power Density of ≈250W/in3 @ 98% Efficiency

23/40

3-Φ SiC vs. Si PV Inverter

Multi-Objective Optimization Flying Capacitor Conv. Concept

► Analysis of 3-Φ Si vs. SiC PV Inverter

─ Single-Input/Single-MPP-Tracker Multi-String PV Converter─ DC/DC Boost Converter for Wide MPP Voltage Range─ Output EMI Filter─ Typical Residential Application

■ Systematic Multi-Objective η-ρ-σ-Comparison of Si vs. SiC■ Exploit Excellent Hard- AND Soft-Switching Capabilities of SiC■ Find Useful Switching Frequency and Current Ripple Ranges■ Find Appropriate Core Material

24/40

■ All-Si IGBT 3-Level PWM Inverter(3L-PWM)

► Topologies - Converter Stages

■ All-SiC MOSFET 2-Level Double-Interleaved TCM-Inverter(2L-TCM)

■ All-SiC MOSFET 2-Level PWM Inverter(2L-PWM)

25/40

► Topologies - Filter Stages

■ 2-Stage DM & CMFilter for 2L-PWM and 3L-PWM

■ 2-Stage DM & CMFilter for 2L-TCM

■ TCM Inductor Acting as DM & CM Inductance

26/40

► Modulation Schemes - PWM Converters

■ Three-Level PWM Inverter (3L-PMW)

─ Symmetric Boost Converter─ Interleaved Operation─ Part. Compensation of LF DC-Link

Midpoint Variation

─ 3-Level T-Type Converter─ 3-Level PWM Modulation─ 3rd Harmonic Injection

─ Standard DC/DC Booster─ Standard Modulation

─ 2-Level Converter─ 2-Level PWM Modulation─ 3rd Harmonic Injection

■ Two-Level PWM Inverter (2L-PMW)

27/40

► Modulation Schemes - TCM Converter

─ 2-Level/Double Interleaved Booster─ Interleaved TCM Operation─ Turn-Off of Branch in Partial Load

─ 2-Level/Double Interleaved─ Interleaved TCM Operation─ Turn-Off of Branch in Partial Load

─ ZVS for All Sw.Transitions

─ Variable fsw

─ Imin to Limit fsw─ Losses Due to Imin

@ Low Loads

■ Two-Level TCM Inverter (2L-TCM)

■ TCM OperatingPrinciple

28/40

► Components and Materials►

2L-TCM

─ 16 x CREE SiC MOSFET80 m 1200 V

─ Optimized Al Heat Sinks─ Range of Sanyo Low Power Long Life DC Fans

─ METGLAS 2605SA1 Amorphous Iron C Cores

─ Solid Round Wire

─ EPCOS MKP DC Film Capacitors 575V and 1100 V for MPP Cap.─ EPCOS Long Life Al Electrolytic Capacitors 500 V for DC-Link Cap.

►

2L-PWM

─ 7 x CREE SiC MOSFET80 m 1200 V

─ 1 x CREE SiC SchottkyDiode 20 A 1200 V

3L-PWM

─ 6 x Infineon Si IGBT H325 A 1200 V / PiN Diode

─ 6 x Infineon Si IGBT T&F30 A 600 V / PiN Diode

─ 2 x Infineon Si IGBT T&F30 A 600 V

─ Infineon Si PiN Diode45 A 600 V

─ EPCOS N87 Ferrite E Cores─ Litz Wire With Range of

Strand DiametersOr

─ EPCOS X2 (DM/CM) and Y2 (CM) EMI Capacitors ─ Magnetics KoolMu Gapless Powder Cores / Solid Round Wire (DM)─ VAC Vitroperm 250F/500F Nanocrystalline Toroid

Cores / Solid Round Wire (CM)

Filt

erDC Ca

psM

ain

Indu

ct.

Cool

ing

Syst

emPo

wer

Se

mic

ondu

ctor

s

►

29/40

► Global Optimization Routine

■ Dependent Design Variables

─ Main Inductances Function of fsw and IL,maxpp

─ Filter Components Based on CISPR Class B

■ European Efficiency

v─ Add. Weighted for {525, 575, 625} V MPP Voltage

■ Independent Design Variables─ 3L-PWM

─ 2L-PWM

─ 2L-TCM

30/40

► Optimization Results - Pareto Surfaces (1)

─ No Pareto-Optimal Designsfor fsw,min> 60 kHz

─ No METGLAS Amorphous Iron Designs

─ Pareto-Optimal Designs for Entire Considered fsw Range

─ No METGLAS Amorphous Iron Designs

─ Pareto-Optimal Designs for Entire Considered fsw Range

─ METGLAS Amorphous Iron and Ferrite Designs

31/40

─ Compact Designs with AmorphousCore Material @ Low Ripples

─ Cheap Designs with Ferrite @ HighRipples Despite Larger Volume

■ 3L-PWM Core Material

─ Only Ferrite for 2L-TCM DueLarge HF Excitations

─ Expected Result

■ 2L-TCM Core Material

─ Ferrite @ High Ripples Cheaper AND Smaller - Unexpected Result (!)

─ Amorphous Core Material too High Losses Already @ Low Ripples, High Flux Density Not Exploited

■ 2L-PWM Core Material

► Optimization Results - Pareto Surfaces (2)

32/40

► Increasing the # of Levels - Flying Capacitor Converter (FCC)

33/40

■ Each Cell Consists of 2 Switches / 1 Capacitor ■ Phase-Modular Topology Supports DC/AC and AC/AC Conversion■ Standard Phase-Shift PWM

■ Natural Capacitor Voltage Balancing ■ No 50Hz Cap. Voltage Ripple

34/40

► Flying Capacitor Converter – Simulation Results (1)

■ Example of N=9-Level FCC■ Switch Blocking Voltage: USw= UDC/(N-1) 100V @ 800V DC Link■ Effective Output Frequency fSw,eff = fSw(N-1) 960kHz @ 120kHz/Switch■ Standard Phase-Shift PWM

P=30kW CFC= 10uF LC-Filter: 3uH / 1uF

35/40

■ Concept Applicable for DC/AC and DC/DC Operation■ Design of Flying Capacitors only for Sw.-Frequency Components

AC/DC Operation (800VDC/400VAC) DC/DC Operation (800VDC/400VDC)

■ Natural Flying Cap. Voltage Balancing Independent of Current Direction

► Flying Capacitor Converter – Simulation Results (2)

36/40

■ Design Issues: Start-Up / Shut-Down / No-Load / Standby (DC Energized, No Uout)■ E.g. Startup: UDC Pre-Charging Time Constant τDC= RDCCDC > 2 τFC

Pre-Charging w. Small τDC

Example of Startup of 5-Level FCC (UDC=450V, UCF≈ 110V)

Pre-Charging w. Sufficient τDC

► Flying Capacitor Converter – Simulation Results (3)

3-Φ Buck-Type PFC Rectifier

Integr. Active Filter Rectifier ConceptHigh Efficiency Demonstrator

► 3-Φ Integrated Active Filter (IAF) Rectifier

■ Injection of 3rd Harmonic Ensures Sinusoidal Input■ Six-Pulse Output of Uncontrolled Rectifier Stage■ Buck-Type Output Stage Generates DC Output from Six-Pulse Rectifier Output ■ Three Devices in the Main Conduction Path

Vin = 400VacVout = 400VdcPout = 8kW fS = 27kHz

■ SpecificationsIntegrated Active Filter.

Activated @ 180°

37/40

► 3-Φ IAF Rectifier Optimization

■ Multi-Objective Optimization - Max. Efficiency / Max. Power Density / Min. Life Cycle Costs■ Life Cycle Costs: (i) Initial Costs & (ii) Electricity Costs of Converter Losses

10 Years of 24x7 Operation Demands η≈99% for Min. LCC

38/40

► 3-Φ IAF Rectifier Demonstrator

■ Efficiency η> 99% @ 60% Rated Load■ Mains Current THD≈ 2% @ Rated Load■ Power Density ρ≈ 4kW/dm3

SiC Power MOSFETs & Diodes

39/40

Conclusions

► Outlook

– 1-Φ 250W/in3 @ 98% PFC Rectifier Module (EV Charger etc.) – 1-Φ 99+% PFC Rectifier (Telecom etc. )– 3-Φ Non-Isolated Very High Bandwidth AC Source – 3-Φ Non-Isolated Ultra-Compact Inverter– 3-Φ 99% Isolated Two-Stage (!) AC/DC Converter– Bidirectional Extr. Eff. Resonant Multi-Port DC/DC Converters– Design Space Diversity of Multi-Objective Optimization– Little Box 3.0 / HF Magnetics (10MHz)– Cellular Scalable Converter Topologies– etc.

■ Research Targets @ ETH Zurich

40/40

Thank You!

Questions