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Analyze-RTLLinting™Solution

Overview

TheBluePearlSoftwareSuiteisasetofanalysisanddebuggingtoolsforIPandFPGAverificationthatfinds:

• RTLdesignerrorsandproblems• MissingClockDomainCrossing(CDC)synchronization• Falseandmulti-cyclepathtimingexceptions

WhyAnalyze-RTLLintingsolution

FPGAsroutinelyhavemillionsofgateswithmemories,transceivers,thirdpartyIPandprocessorcores.Problemscanbetimeconsumingandcomplextodebuginthelabandthroughsimulations.Toreduceverificationanddebugtimes,designersneedtoolsthatcanidentifyproblemsquicklybeforesimulationandsynthesis,anddefinitelybeforespendingtimeinthelab.

FeaturesofAnalyze-RTLLintingsolution

WithAnalyze-RTLLintingsolution,designerscan

• GeteffectiveandmeaningfulresultsquicklywithtoolSetupWizard

• CheckIEEEVerilog/SystemVerilog&VHDLlanguage

specificationcomplianceandsyntax• Configurechecksalongwithstandardchecks,STARC,

RMM,andXilinxUltraFast

• UsetheGUItostreamlinedebug;integratedRTL,schematics,andmessageviewer

• Useeasydebugmessagesorting,filteringandwaivingtopinpointproblems

• AutomateflowwithCommandLineInterface(CLI),andre-usablemessagewaiverfile

DebugDesignIssuesQuickly

TheVisualVerificationEnvironmentenablesAnalyzeRTLsolutionuserstodebugdesignissuesquicklyusingintelligentsortingandmessagefiltering.

• Lownoise• Checkcustomizationforspecificdesignstyle• Easysetup• Waivermigration

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FiniteStateMachineAnalysis

Ratherthanwritingexhaustivesimulationtestbenchestovalidatetheirfinitestatemachines(FSMs),designerscanusetheFSManalysiscapabilitywithinAnalyze-RTLLintingsolution. Withminimaleffort,designerscan

• ExtractFSMsfromtheirRTL• Finddeadorunreachablestates• Generateeasytoreadbubblediagramstobetter

visualizeFSMs

RTLChecksforHighSpeedDesigns

ItisimportanttofindasearlyaspossibleRTLcodingthatpreventsthedesignfromgettingdesiredspeed.FPGAs,becauseoftheirmoreconstrainedfabricthanASIC,certaintypeofstructurescausesslowdown.Ratherthanwaitforsynthesisorstatictiminganalysisresults,Analyze-RTLLintingsolutionuserscaneasilyidentify:

• Highfanoutnets• Deepnested“if-then-else”statements• Highlevelsoflogicpaths• Resetmethodology,Async/sync

Contactus:www.bluepearlsoftware.com+1(408)9610121sales@bluepearlsoftware.com