analog, io test chip validation

ANALOG IO TEST CHIP VALIDATION

SMIT PATEL

13MECC12

INTERN AT

ST MICROELECTRONICS

INTERNAL GUIDE,

DR. TANISH ZAVERIEXTERNAL GUIDE,

MR. NITIN BANSAL

INSTITUTE OF TECHNOLOGY

NIRMA UNIVERSITY

2

PRE-SILICON IOS VALIDATION ON DIFFERENT IP’S

PHASE - 1

3INDEX

• Area Introduction

• Motivation

• Problem Statement

• Objective

• Background study

• Methodology

• Work & Results

• Conclusion

• References

4AREA INTRODUCTION

• A chip can be divided into two main parts,

1) Core

2) I/O's

• Core is main circuit which perform the logic for which chip is designed

• Normally core operates at Vdd level of 1.2V

• If any of incoming signal is having voltage level more then core level then it may lead to failure of core

• Here, comes the need and importance of I/O integrated with core section

5MOTIVATION

• Motivation behind Input-Output(IO) Test-Chip validation is to verify the accurate functioning of IO rings

• IO rings are the communication medium between the external world and inside core(processors, analog IPs)

• Inside Core, IPs run on different specification voltages

• What happens if we apply high voltage ?

• Current technologies in IO pads

• Hence, proper functioning of IO ring must be checked and verified

7PROBLEM STATEMENT

• Plethoric behavior of external world to IPs may be unpredictable with respect to inside core in order to analyze the behavioral current flowing to core we should validate the IO ring

• So we should analyze the characteristics of IO ring

8OBJECTIVE

• The objective is to design, simulate and characterize the Input Output analog library cells in different technologies in order to meet the desired specifications

• Ensuring proper signal routing and placement from the inside low voltage level core signals to the off-chip higher voltage level Input Output bidirectional peripherals

9IOS - ROLE AND PLACEMENT

• IOs are placed on the periphery of the chip

• IOs are elements which interface the core signal to the off-chip world

• Any input signal which comes from the off-chip environment into the chip, must be checked by IO circuitry

• If IO finds any signal defying the behavior expected from it, it modifies the signal for proper functioning of the chip

• IOs also scan outgoing signals from core to off-chip environment

• Efficiency of the chip is determined by the functionality of IOs

10STANDARD IO-CHIP COMPONENTS

• Input Buffers

• Output Buffers

• Bidirectional Buffers

• Supply cells

• Leaf cells

• Fillers and Corner cells

• Filler-cuts

11

BI-DIRECTIONAL BUFFER

• A Bidirectional Buffer consists

- Input Buffer (also known as Receiver)

- Output buffer (also known as Driver)

- Pull-up / Pull-down logic

- ESD protection circuitry

• A Bidirectional buffer can be used in both ways i.e. signals from off-chip environment can interact with the core chip and vice versa

Core side

12INPUT RECEIVER BLOCK

• An Input buffer (also known as Receiver) receives and makes the signal adaptable for the core logic

• Input buffers couples the signal

- High voltage ‘Vdde’ Lower voltage ‘Vdd’

13OUTPUT DRIVER BLOCK

• Output buffers amplifies the signal

- Lower voltage level ‘Vdd’ Higher voltage level ‘Vdde’

• To limit switching noise (L*dI/dt), for all the buffers, the impedance of the driver is controlled through control bits which are generated by compensation cell

14MODES OF OPERATION OF A

BIDIRECTIONAL CELL• Normal Mode

• Test Mode

• IDDQ Mode (no static current dissipation in the cell)

• IO-OFF Mode

• CORE-OFF Mode

• Power down / Stand-by Mode

15IO DESIGN AND CHARACTERIZATION FLOW

My work

16ELDO SIMULATION FLOW

17IOSIM WRAPPER OVER ELDO

IOSIM

OUTPUT

ELDO

Netlist (circuit description file – ex.

SPICE.spi)

Command file (for

parameter extraction –

ex. out_tran_1v

8)

Lib.spec (for PVT

measures)

Reference_model.spec (for library inclusion and flags)

Simulation log file (.chi)

INPUT

Set_prod_linux (for

sourcing tool environment

)

Error / Logfile (.log)

Simulation

waveform file (.wdb or .cou)

Simulation results file (.aex)

Result database

(.rdb)

• To run ELDO simulations in parallel, a wrapper is build i.e. IOSIM

18CMOS INVERTER

Schematic of CMOS Inverter

Output waveform of CMOS Inverter in Transient analysis

19DESIGN OF BI-DIRECTIONAL CELL

20IO RING OF HSICUSB TEST-CHIP

Bi-Directional Loops

Supply Cells

• Repeated Bi-Directional cells give rise to an IO ring structure

21LAYOUT OF HSICUSB IO RING

Layout using metal sheets

• After drawing the layout of IO Ring, DRC is performed for the entire chip

• After DRC, parasitic extraction layout view is generated

22WAVEFORMS OF HSICUSB IO RING

MODE = Test ModeFrequency 1 = 1KHzFrequency 2 = 2KHzOutput freq. = 2KHz

MODE = Normal ModeFrequency 1 = 1KHzFrequency 2 = 2KHzOutput freq. = 1KHz

23RESULTS OF HSICUSB IO RING

Normal Mode IO-OFF Mode CORE-OFF Mode

EXTRACT for TRANSIENT ANALYSIS

TEMPERATURE = 2.5000 E + 01

I_VDDE1V8_CUT = 1.87E-08 AI_VDDE1V8_CUT1 = 8.96E-08 AI_VDDE = 2.95E-06 AI_VDD = 8.13E-07 AI_GNDE = 9.97E-06 AI_VDDE1V8 = 5.61E-06 A

I_VDDE1V8_CUT = 1.49E-18 A I_VDDE1V 8_CUT1 = 7.12E-15 AI_VDDE = 2.39E-11 AI_VDD = 7.16E-07 AI_GNDE = 1.57E-09 AI_VDDE1V8 = 1.31E-10 A

I_VDDE1V8_CUT = 1.87E-08 AI_VDDE1V8_CUT1 = 1.02E-07 AI_VDDE = 1.18E-06 AI_VDD = 4.06E-10 AI_GNDE = 4.07E-06 AI_VDDE1V8 = 1.16E-06 A

• Following are Leakage Current analysis at different PVT Corner

- Process = Typical - Voltage = 1V8v - Temperature = 25 C

24SILICON TESTING WITH JTAG

• To configure the chip for testing

• Three IO Pins should be configured with TDI,TCLK & TE.

• Number of Bits in TDI & TCLK will vary from chip to chip.

• Testing has to be started when TE goes low(only then Control signals will go to the IO/Core cells)

25RESULTS OF JTAG BLOCK

• Specifications of the waveforms - Voltage Level- IO HV Supply - Bit Period of TDI = 2*(Bit Period of TCLK) - Every transition(Zero to One or vice versa) in TDI should be at the negative edge of the TCLK(One to Zero).

26SCHEMATIC OF REFCOMPENSATION

Bi-Directional Loops

Compensation Cell

JTAG Block

• IO Ring with JTAG Block and COMPENSATION Cell

• Using JTAG we can be able to add more Bi-Directional cells

• To limit switching noise, for all the buffers, the impedance of the driver is controlled through control bits which are generated by compensation cell

27RESULTS OF REFCOMPENSATION

Leakage Currents in Supply Cells

REFCOMPENSATION1V83V3

EXTRACT for TRANSIENT ANALYSIS

TEMPERATURE = 2.5000 E + 01

DEFAULT MODE NORMAL MODE (TQ = 0)

IO-OFF MODE

CORE-OFF MODE IDDQ MODE (TQ = 1)

Supply levels HV LV HV LV LV HV LV HV LV

GNDBGCOMP (A) 1.43E-08 3.34E-09 1.50E-04 1.75E-04 1.62E-13 1.18E-08 1.18E-08 1.05E-07 3.01E-06

VDDE3V3_COMP (A) 8.52E-05 7.74E-05 1.04E-03 8.54E-04 6.48E-12 1.00E-04 1.23E-04 8.56E-05 1.01E-04

GNDV3_COMP (A) 8.21E-05 9.30E-06 9.62E-04 6.87E-04 5.78E-07 3.13E-04 5.44E-04 8.23E-05 1.17E-05

VDDE3V3 (A) 4.00E-04 1.15E-04 1.74E-03 1.82E-04 2.18E-10 5.15E-04 7.23E-04 4.05E-04 1.27E-04

GNDE (A) 4.04E-04 1.83E-04 1.68E-03 1.85E-04 5.02E-09 3.02E-04 3.02E-04 4.09E-04 2.14E-04

VDD (A) 7.07E-05 5.52E-05 7.99E-05 6.56E-05 5.39E-05 3.80E-09 3.80E-09 6.98E-05 5.48E-05

• Following are Leakage Current analysis at different PVT Corner HV = High supply (3.3v), LV = Low supply = (1.8v)

28

CHARACTERIZED LIBRARIES AND TECHNOLOGIES

TECHNOLOGIES USED – 5 JTAG

CMOS28FDSOI CMOS028 CMOSM40 CMOSM55 CMOS28FDSOI

LIBRARIES WORKED ON – 9

PROG1V8FAST PROG1V8FASTIO_CUP_3V35V0_LS_GO

HV_7M4X0Y2ZLB

IO_CUP_TRIPPLEPROG5V0_LH_GOHV_6M4X0Y

1ZLB (WORKING)

C28SOI_IO_EXT_3V3SF_REFCOMPENSATION1V8

3V3_EG_UM

TESTMUX1V8

3V3SF_SRCNHS3V3

3V3SF_I2C3V3

I2C1V8FS

IO CELLS CHARACTERIZED - 10

BDPROG8SCARUD14KQPCKRH_FAST_SF_1V8

BDPROG6SCARUD14KQPCKRH_FAST_SF_1V8

BDPROG05S2M8F16FSCATARUDQ_5V03V3_65U

BDPROG05S2M8FSATARUDQ_5V0_65U_LIN

(WORKING)

C28SOI_IO_EXT_3V3SF_I2C3V3_LR_EG

BD8SCARUDQPCZ_SF_1V8_FC_LIN

BDPROG6SCARUDQPCKRH_FAST_SF_1V8_FC

C28SOI_IO_EXT_3V3SF_I2C_5VFSFT_LR_EG

BD8SCARUDQP_HS_3V3SF_3V3_FC

BDPROG6SCARUQPCKRH_FAST_SF_1V8_FC

I2C_EXT_3V3SF_3V3FS_FC_LIN

I2CRZ_SF_1V8

29CONCLUSION

• This project work has helped me in understanding verification of Analog IO Ring

• This project has also helped me to get knowledge of different types of IO Designs

• Expose to different kinds of tools like CADENCE Virtuoso, ELDO, IOSIM

• By validating the IO Ring characteristics we are protecting our core and its IPs to perform safe in its safe functional mode.

31REFERENCES

[1] Vikas Chaudhary, Design of I/O elements, Central Research and Development, STMicroelectronics, Greater Noida, India

[2] MOHD. RIZVI, FUNDAMENTALS of IOs Central Research and Development at ST Microelectronics Noida, India

[3] Testchip Basics company presentation on basics of IO testchip, ST Microelectronics, Greater Noida

[4] http://lsmwww.epfl.ch/Education/CadenceTutorial/explanations/schematic.html

[5] http://ipdf.dlh.st.com/ftmweb/iflweb/TRAINING/modules/MODULE1/ Module1.htm

POST-SILICON IOS VALIDATION OF OSCILLATOR IP’S USING AUTOMATION

PHASE - 2

34INDEX

• Introduction

• Objective

• Background

• Methodology

• Test Results

• Conclusion

35INTRODUCTION

• Integrated Circuit development cycle involves a variety of sequential stages which are equally essential to its successful completion

• Post-Silicon Validation is one such process which is aimed at verification of the IC’s performance at silicon level before mass production

• Automation is employed to complete the validation process in limited time frame due to repeatability of tests

36OBJECTIVE

• Thorough understanding of the Post-Silicon Validation Process Validation of analog IP’s received by design teams for hands-on experience

• Analyzing and finding problems in current methodologies

• Proposing solutions to any short-comings in validation process

• Implementing feasible solutions to any problems

37WHAT IS VALIDATION?

• Performing a number of requested tests to check the performance of a device or chip at various operating conditions

Test 1

Test 2

Test 3

Validation Report

38PURPOSE OF VALIDATION?

• Providing feedback to a designer for his/her circuit’s functionality at operating conditions

Design Review Output

Validation

APPROVAL

REVIEWAL

39WHY AUTOMATION?

• Automation employed due to repeatability of tests on several dies

• Reduces test time considerably

• Reduces human-led errors

• Promises reproducibility of test results

40TEST RUN THROUGH AUTOMATION

Die Sorting Threshold Operating Mode Measurements

0

10

20

30

40

50

60

70

9

24

61

210

16

Test time reduction using Automations

Manual Automated

Tests

Tim

e in

hrs

41

Test Request by Design

Team

Fab

Test Chip

Package

Test Board Selection

Test Requirements, Specifications and CAD

simulation data

Test Set-Up

• Equipment Selection

·Test Configurations

·Automation Needs and Feasibility

Creation of Input Daffy

Existing Automations

sufficient

Develop/Modify Automations

Perform required Tests:

•Die Sorting

•DC

•Timing

Test Results

Blank Test

Report

Silicon vs. CAD Analysis

Publish Validation

Report

NO

NO

YES

YES

VALIDATION FLOW

42TEST SETUP

43TEST BOARD

44TYPES OF TEST PERFORMED

• Functionality Test

• Selection of Die

• DC current consumption

• Normal Dissipation

• IO-Off Dissipation

• Core-Off Dissipation

• IDDQ Dissipation

• Input Threshold Measurements

• Compensation Code

• Reference voltage measurement

45FLOWCHART FOR DC CURRENT MEASUREMENTS

46 FLOWCHART FOR TRANSIENT MEASUREMENTS

47TEST BOARD SETUP

48CONT.

49AUTOMATION PROCESS

50CONT.

51CONT.

52CONT.

53RESULTS

54CONT.

55CONT.

56CONCLUSION

• This project work has helped me in understanding IO Ring validation of Analog IP’s

• This project has also helped me to get knowledge of different types of IO Designs

• Expose to different kinds of automation like IO Validator, Oscillator Validator, etc.

• By validating the IO Ring characteristics we are protecting our core and its IPs to perform safe in its safe functional mode.

57REFERENCES

[1] Stanley L.Hurst, “VLSI TESTING – digital and mixed analogue/digital techniques”, IEE Circuits, Devices and Systems, Series 9

[2] Hung-Chih Chiang, “Introduction to System IC Design Flow”

[3] Agilent Technologies, “3458A & DSA 90804A Instrument Manuals and Data Sheets”

[4] Keithley Instruments, “DMM 2700 & 2400 Instrument Manual and Data Sheets”

[5] Thermonics, “T-2800 Instrument Manuals”

[6] Analog Design Flow, www.eda.ei.tum.de

[7] Post-Silicon Validation, www.wikipedia.org

58

Thank You