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Tsuto et al.: Advanced Through-Silicon Via Inspection for 3D Integration (1/5)
1. Introduction3D IC packaging employs advanced interconnect tech-
nologies including TSVs, bonding, wafer thinning, back-
side processing and fine pitch multi-chip stacking.[1]
These new technologies improve the value of semiconduc-
tor devices, but produce new and complex manufacturing
processes. In 2012, Semiconductor Equipment and Materi-
als International (SEMI) has updated the standard of TSV
geometrical metrology[2] and other standards under
development. Thus, new inspection and metrology tech-
nologies are required to manage those complex manufac-
turing processes.
In 2011, International Technology Roadmap for Semi-
conductors (ITRS) updated the specific challenges of TSV
and 3D interconnect metrology.[3]
As shown Table 1, the main challenges of 3D metrology
involve the measurement of high-aspect -ratio TSVs and
the opaque nature of materials (silicon and copper) that
limits conventional optical microscopy techniques.
There are several methods for determining the shape of
TSVs during or after their creation process, such as depth
measurement using white light interference, optical coher-
ence tomography (OCT) or confocal microscopy and 3D
shape observation by X-ray CT or IR microscope. Although
these methods can examine one TSV or a few TSVs at
[Technical Paper]
Advanced Through-Silicon Via Inspection for 3D IntegrationTakashi Tsuto*, Yoshihiko Fujimori**, Hiroyuki Tsukamoto**, Kyoichi Suwa*, and Kazuya Okamoto***
*Core Technology Center, Nikon Corporation, 471 Nagaodai-cho, Sakae-ku, Yokohama, Kanagawa 244-8533, Japan
**Instruments Company, Nikon Corporation, 471 Nagaodai-cho, Sakae-ku, Yokohama, Kanagawa 244-8533, Japan
***Office for University-Industry Collaboration, Osaka University, 2-1 Yamadaoka, Suita, Osaka 565-0871, Japan
(Received July 31, 2013; accepted October 11, 2013)
Abstract
A new methodology for inspection of through-silicon via (TSV) process wafers have been developed by utilizing the signal
of diffracted light from the wafer, which will be suitable for 3D IC production. Near infrared (NIR) light should be applied
for the inspection including defect observation at a large depth with chip-cost economy. Diffraction-based macroscopic
inspection with NIR light demonstrates a good potential for in-line defect inspection, because it can detect small shape
variations and/or defects by capturing the light as a one- frame image via an image sensor, not a special high-cost image
sensor but a general high resolution CCD sensor. Our newly developed TSV inspection system exhibits a high sensitivity
to 3D shape variation and a high throughput covering the entire wafer. This new technology should be essential for future
3D IC fabrication.
Keywords: TSV, 3D Integration, Inspection, Metrology
Table 1 2011 ITRS 3D Interconnect TSV Roadmap.
GLOBAL LEVEL, WTW, DTW, or DTD 3D stacking
2009–2012 2012–2015
Minimum TSV diameter 4–8 μm 2–4 μm
Minimum TSV pitch 8–16 μm 4–8 μm
Minimum TSV depth 20–50 μm 20–50 μm
Maximum TSV aspect ratio 5:1–10:1 10:1–20:1
Bonding overlay accuracy 1.0–1.5 μm 0.5–1.0 μm
Minimum contact pitch (thermocompression)
10 μm 5 μm
Minimum contact pitch (solder or SLID)
20 μm 10 μm
Number of tiers 2–3 2–4
INTERMEDIATE LEVEL, WTW 3D stacking
2009–2012 2012–2015
Minimum TSV diameter 1–2 μm 0.8–1.5 μm
Minimum TSV pitch 2–4 μm 1.6–3 μm
Minimum TSV depth 6–10 μm 6–10 μm
Maximum TSV aspect ratio 5:1–10:1 10:1–20:1
Bonding overlay accuracy 1.0–1.5 μm 0.5–1.0 μm
Minimum contact pitch 2–3 μm 2–3 μm
Number of tiers 2–3 8–16 (DRAM)
Copyright © The Japan Institute of Electronics Packaging
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Transactions of The Japan Institute of Electronics Packaging Vol. 6, No. 1, 2013
once, it takes a long time to cover all TSV arrays over the
wafer. On the other hand, conventional automatic macroin-
spection tools can examine the entire wafer rapidly. How-
ever, such tools cannot detect issues regarding via pat-
terns in deep locations. Table 2 shows a comparison of via
inspection/measurement tools. We already proposed a
system for TSV array macroinspection.[4] In this paper,
we studied the methodology to measure the shape varia-
tion of vias, including that of diameter and depth.
2. Methodology2.1 Optical system
Figure 1 shows the optical configuration for diffraction
inspection. The wafer is illuminated by telecentric light of
single-band wavelength, and the diffracted light from
repeated patterns is captured by the image sensor as a
one-frame image. When repeated patterns are illuminated
by light, diffracted light emerges to satisfy Eq. (1) as
described below. The wafer tilting mechanism is installed
in the system, and the wafer is tilted to satisfy the diffrac-
tion condition:
d m m(sin sin ) ( , , )β α λ− = = ± ±1 2 (1)
where d is the pattern pitch, α is the incident angle, β is
the exit angle, m is the diffraction order, and λ is the wave-
length. Telecentric illumination is important for obtaining
the diffracted light from the entire wafer in one shot. All
the points over the wafer should be illuminated with the
same incident angle, and diffracted light with the same
exit angle should be captured. Optical parameters, such as
wavelength, polarization, wafer tilting angle, and illumina-
tion power, are defined before the inspections so as to
obtain sensitive signals for each wafer process.
The diffracted light image of the entire wafer captured
by the optical system is shown in Fig. 2.
Obviously, the diffraction signal intensity in each area
on the wafer changes as shown by the gray level, at which
the variation in signal intensity depends on the variation in
via size. The circle shows the wafer outline in Fig. 2. When
the patterns are formed uniformly, the diffraction effi-
ciency is uniform in every pattern area, and the image
gray level is uniform. When cross-sectional pattern shapes
in some areas are changed by the defocusing of the expo-
sure tool, for example, the diffraction efficiency in the area
changes, and the image gray level becomes brighter or
darker. The area resolution in the XY axis is not very high,
but a slight change in cross-sectional pattern shape due to
the error of the exposure or etching tool can be detected
as the grayscale changes in the image. Diffraction occurs
Table 2 Comparison of via inspection/measurement tools.
TSV array macroinspection
White light fringes, confocal
X-ray CTAutomatic
macroinspection toolsIR microscope
PurposeInspection/
measurementMeasurement Inspection Inspection Observation
Target3D-shape
nonuniformityDepth 3D shape Surface pattern 3D shape
Throughput 150 wph (front side) ~1 s/FOV ~10 min/piece ~100 wph Manual operation
Detection resolution or sensitivity
0.01 μm (1% of 1 μm) detected diameter change
~0.1 μm measurement
resolution
~0.1 μm shape representation
resolution
~10 μm detected particle size
~0.1 μm observation resolution
Fig. 1 Optical configuration for TSV array inspection utiliz-ing diffracted light.
Fig. 2 Diffraction image sample.
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Tsuto et al.: Advanced Through-Silicon Via Inspection for 3D Integration (3/5)
at the boundary of two materials with different refractive
indices; therefore, the method is applicable to each stage
of TSV formation, such as after deep via etching or after
isolation/barrier metal coverage. Here, this type of inspec-
tion is called “TSV array macroinspection.”
2.2 Wavelength of illumination lightRegarding illumination light, a single-band NIR light is
selected in this study. By using NIR light such as that of
1,100 nm wavelength, it is possible to detect the change in
via shape in deep position, including the bottom position
because of Si transparency. A system with an NIR light
illumination capability is installed to detect the defects in
deep positions of the wafer.
3. Simulation3.1 Model system
We evaluate quantitatively the order of magnitude of the
diffraction signal for a realistic model system. We consid-
ered the basic structure (see Fig. 3): with a pitch size of 2
μm, a top/bottom via diameter of 1·μm and a depth of 10
μm. The profile change types and ranges of variations are
as follows:
a) via diameter (straight via): 0.8–1.2 μm
b) bottom diameter (taper): 0.6–1 μm
c) via depth: 9–11 μm
The calculations are carried out within the incident
angle θ range of 0–75 deg by 15 deg steps for each s-polar-
ization (i.e., TE wave) and p-polarization (i.e., TM wave) to
obtain the optimum conditions. The azimuthal angle φ of 0
deg is fixed.
3.2 Calculation systemFor the microstructure with diffraction, we perform a
rigorous coupled-wave analysis (RCWA) for simulations.
Because of the interaction between the micrometer-scale
structures and the micrometer-wavelength light (i.e.,
NIR), a simpler method (e.g., scalar analysis which is simi-
lar to the effective medium approximation), is not accu-
rate.[5]
We consider the light path in the Si wafer shown in Fig.
5. Utot represents the incoherent intensity summation of
diffracted signal from the upper side. Ua, Ub, Uc and B
represent the coherent product of amplitude reflectance or
amplitude transmittance.
Inspection from the back side is expected to have a high
sensitivity for deep locations and to extend the inspection
opportunity proposed in this study.
3.3 ResultsWe obtained 56 results of simulation (incident from
upper side or back side, incident angle, polarization, and
diffraction order) per one profile type and chose better
Fig. 3 Illustration of basic structure.
Fig. 4 Illustration of profile change type.
Fig. 5 Schematic view of light path.
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Transactions of The Japan Institute of Electronics Packaging Vol. 6, No. 1, 2013
conditions with high sensitivity and linearity.
As shown in Figs. 6-(a) and (b), a high correlation
between diffraction signal intensity and each profile type
variation was observed. On the other hand, as shown Fig.
6-(c), the signal of depth has small but noisy oscillation.
We consider that it is caused by the high refractive index
of Si. A small physical depth variation increases the optical
path length variation in Si. By further analysis of this phe-
nomenon, it is expected that the technology will be
enhanced to a higher level of shape profile measurement.
How a small defect is detected by the system depends
on the noise level of the system and the resolution of the
image sensor. However, evaluations of the system noise
level and the resolution of the image sensor are not
included in this study, and will be studied as future work.
4. Experiment4.1 The sample
We prepared a test wafer to confirm the practicability of
measurement and the reliability of simulation. For this
purpose, only the via diameter variation is examined. A
simple structure with via patterns of aspect ratio 1:1, i.e., 1
μm diameter, 1 μm depth and 2 μm pitch, was used. The
number of TSVs per shot is on the order of 107, but we
measured an area near the center of shot for simplicity.
A small depth is expected to result in a small depth
direction profile variation. In other words, it is robust
against the noise except the signal of diameter. The model
system changes accordingly.
4.2 Result and discussionFigure 7 shows the relationship between diffraction sig-
nal intensity and via diameter measured by CD-SEM.
From Fig. 7, it was calculated that the signal change for a
10-nm-diameter change was 2 image gray levels; this
change is large enough to be detected.
The experimental and simulated diffracted signal varia-
tions plotted against the diameter variation are shown by
red and blue dots, respectively (see Fig. 8). We can see a
correlation between the gray level and via diameter pro-
files (R2 > 0.7) for experimental data (see Figs. 7 and 8).
Deviations of the experimental data are larger than that of
the simulated data, probably because of the error that was
Fig. 6 Simulation results: relationship between diffraction signal intensity and each profile type variation.
a) Via diameter variation
b) Bottom diameter variation
c) Depth variation
Fig. 7 Relationship between diffraction signal and via diame-ter.
Fig. 8 Comparison of experimental and simulated data about relationship between diffraction signal and via diameter.
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Tsuto et al.: Advanced Through-Silicon Via Inspection for 3D Integration (5/5)
not considered (e.g., depth fluctuation or aperture defor-
mation). The experimental and simulated curves look
almost parallel in the Fig. 8, which suggests that properly
calibrated experimental data correspond with the simu-
lated data. We are continuously considering the dominant
factor of deviations.
5. Proposed OperationFigure 9 shows the proposed operation in the TSV pro-
cess. TSV array macroinspection and measurement after
D-RIE can monitor both hard mask etching and D-RIE
during the creation of TSVs. In addition, it is recom-
mended that a litho-oriented macroinspection be per-
formed as after-development inspection to eliminate coat-
ing, exposure, and developmental issues.
5.1 Inspection opportunities in various processesFigure 10 shows the inspection opportunities in various
TSV processes. In the case of the via first process or sili-
con interposer, holes (vias) are created on a bare silicon
wafer. The via pattern shape can be inspected from both
front and back sides.
In the case of the via middle or via last process with front-
side vias, vias are created after the fabrication of a metal
oxide semiconductor field-effect transistor (MOSFET)
fabrication. Inspection from the front side is difficult
because of the presence of doped ions and wiring patterns,
which block light. However, inspection from the back side
is possible and effective in this case. In the case of the via
last process with back-side vias, vias are created after the
fabrication of the MOSFET and interconnect, and the
attachment of the wafer support system attachment.
Inspection from the front side is difficult, but that from the
back side is possible.
6. ConclusionNew inspection and metrology technologies are
required for TSVs and 3D IC processes. We demonstrated
the capability of TSV array macro-inspection. The results
of simulation using RCWA were investigated. For via diam-
eter and bottom diameter, dif fraction signals were
observed to have good sensitivity and linearity for profile
variation. By choosing or combining different conditions,
it is expected that more effective inspection and defect
depth discrimination for the measurement will be made
possible. From the experimental results, the sensitivity
was determined to be sufficiently high for detecting a
10-nm-diameter change under test conditions considered.
This result showed a correlation with the diameter varia-
tion and a possibility of agreement between simulated data
and experimental data.
We proposed the operation in the TSV process. This
new technology should be essential for future 3D IC fabri-
cation.
References[1] Yole Development Report, “3-D IC integration & TSV
interconnects, 2010 Market Analysis,” 2010.
[2] SEMI 3D1-0912, “Terminology for Through Silicon
Via Geometrical Metrology,” copy available for pur-
chase at www.semi.org
[3] International Technology Roadmap for Semiconduc-
tors, 2011 Update, http://www.itrs.net/Links/2011IT
RS/2011Chapters/2011Metrology.pdf
[4] Y. Fujimori et al., “New methodology for through sili-
con via array macroinspection,” J. Micro/Nanolith.
MEMS MOEMS 12(1), 013013, Jan–Mar 2013.
[5] A. A. Maznev et al., NIST Metrology 2007.
Takashi TsutoYoshihiko FujimoriHiroyuki TsukamotoKyoichi SuwaKazuya Okamoto
Fig. 9 Proposed operation in TSV process.
Fig. 10 Inspection opportunities in various processes.
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