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Advanced planar FDSOI devices
Dr. Claire Fenouillet-Beranger
CEA LETI, Grenoble, France Claire.fenouillet-beranger@cea.fr PARIS / July 16th, 2014
-French National funding/projects : Nano2012, Nano 2017, …
-European funding/projects : Reaching 22, Dynamic ULP, Places2Be, …
-Industrial collaboration:
STMicroelectronics, IBM, SOITEC
Acknowledgement
| 2 C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
Outline
Introduction to planar FDSOI
28nm FDSOI [platform]
Process integration, results reminder, devices partitioning
Multi Vt, back bias effect, variability
14nm FDSOI [development]
Boosters, process integration
Scalability
10nm FDSOI [R&D]
Geometrical scaling, new modules, strain for µ boost
Conclusion
| 3 C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
Outline
Introduction to planar FDSOI
28nm FDSOI [platform]
Process integration, results reminder, devices partitioning
Multi Vt, back bias effect, variability
14nm FDSOI [development]
Boosters, process integration
Scalability
10nm FDSOI [R&D]
Geometrical scaling, new modules, strain for µ boost
Conclusions
| 4 C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
ITRS roadmap beyond 28nm
l 5
65nm 45nm
Introduction of technological « boosters » for bulk
Limited control of the gate through the
channel
28nm
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
Bulk transistor limitation beyond 20nm
Heavily Doped Wells
High variability due to dopant fluctuation
Longer minimum gate length (less speed, less density)
Severe layout effects (wells proximity)
Gate
Gate oxide stack
Source Drain
Limited body bias capability
Weak process compensation
FD-SOI technology very suitable for low power from
28nm nodes and beyond
d
eff
dep
eff
ox
2
eff
j
ox
Si φL
T
L
T
L
X1
ε
ε0.64SCE
Ref: [Skotnicki – ESSDERC 00]
- Short channel effects improvement (Xj ,
Tdep)
- Low subthreshold slope
- Reduced junction capacitances
- Isolation between devices
- Better variability no channel doping
Complex channel architecture
High cost process flow (yield, cycle time)
Source of variability (multiple steps)
Source of leakages currents
Gate
Gate oxide stack
Source Drain
Body bias flexibility
Punchthrough limited by BOX
Tsi Xj
Depleted devices deliver improved
electrostatic control and device scalability
Tsi Tsi
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16 | 6
ITRS roadmap beyond 28nm
l 7
65nm 45nm Innovative structures 28nm
Transistor FinFET : 3D
Planar FDSOI transistor Introduction of technological « boosters » for bulk
Limited control of the gate through the
channel gate
Thin Silicon film
gate
drain
source
he
igh
t
Thin Silicon film
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
Why thin BOX?
TBOX
G
DrainSource
Couplage
lateral
Y
X
Y
X
Vg=Vd=1V
Ca
na
l d
e c
on
du
cti
on
Su
sb
str
at
40 60 80 20 0
Y (nm)
Drain
Y
X
Y
X
Source
G
TBOX
Ca
na
l d
e c
on
du
cti
on
Su
sb
str
at
Y (nm)
-Potential increases in
BOX
-Strong lateral coupling,
through the BOX,
between the source and
drain
-DIBL degradation
Thin BOX
Thick BOX
-Low potential
modification in the BOX
-Low lateral coupling
between source and
drain
-DIBL improvement
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16 l 8
Thin BOX and Ground Plane (GP) Thin BOX improves the short channel effects
Depletion area extended under the BOX
Potentiel electrostatique
Gate Gate
Substrate doping= 1e17cm-3 Substrate doping= 1e17cm-3
DIBL and subthreshold slope improvement C. Fenouillet-Beranger et al,
ESSDERC 2008
VT modulation
Ground Plane introduction (GP or BP)
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
-0.25
-0.2
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
0.01 0.1 1
Lg(µm)
DIB
L(V
) @
Vd
d l
1.1
lV
TiN ALD 10nm/ HfZrO2 CET 17Å Tsi 8nm
BOX 20nm With GP
BOX 20nm W/O GP
BOX 145nm
PMOS
NMOS
60
70
80
90
100
110
0.01 0.1 1Lg(µm)
S(m
V/d
ec
) @
V
d 1
.1V NMOS TiN ALD 10nm HfZrO2 2.5nm
CET 17Å Tsi 8nm
BOX 20nm With GP
BOX 20nm W/O GP
BOX 145nm
l 9
Without GP
BOX 20nm
Si 8nmBOX 20nm BOX 20nm
Si 8nm
With GP
BOX 20nm
GP
BOX 20nm
Si 8nm
BOX 145nm
Thick BOX
Without GP
BOX 20nm
Si 8nmBOX 20nm
Without GP
BOX 20nm
Si 8nmBOX 20nm BOX 20nm
Si 8nm
With GP
BOX 20nm
GP
BOX 20nmSi 8nm
With GP
BOX 20nm
GP
BOX 20nm
Si 8nm
BOX 145nm
Thick BOX
BOX 20nm
Si 8nm
BOX 145nm
Thick BOX
G
S D
Ground Plane
Thin BOX
G
S D
Ground Plane
Thin BOX
G
S D
Ground Plane
Thin BOX
Back Plane
Without GP
BOX 20nm
Si 8nmBOX 20nm BOX 20nm
Si 8nm
With GP
BOX 20nm
GP
BOX 20nm
Si 8nm
BOX 145nm
Thick BOX
Without GP
BOX 20nm
Si 8nmBOX 20nm
Without GP
BOX 20nm
Si 8nmBOX 20nm BOX 20nm
Si 8nm
With GP
BOX 20nm
GP
BOX 20nmSi 8nm
With GP
BOX 20nm
GP
BOX 20nm
Si 8nm
BOX 145nm
Thick BOX
BOX 20nm
Si 8nm
BOX 145nm
Thick BOX
FDSOI: Introduction
| 10
Fully Depleted Silicon-On-Insulator (FDSOI) Improves the device scalability (vs. bulk): enhanced electrostatics
O. Faynot, SOI conf. 2011 short course FDSOI
bulk
0
50
100
150
200
250
300
10 20 30 40Gate Length (nm)
DIB
L (
mV
/V)
FinFET
Bulk
FDSOI (TSOI~7-9nm)
EOT~1nm
WFin=13nm Toshiba
WFin=17nm TSMC
WFin=17nm
Intel
IEDM09
ST IEDM09
IMEC
IBM ETSOI IEDM09
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
FDSOI: Introduction
| 11
Fully Depleted Silicon-On-Insulator (FDSOI) Improves the device scalability (vs. bulk): enhanced electrostatics
Reduce the variability thanks to undoped channel: record variability 1.4mV.µm in C28nm technology = 150mV SRAM VMIN reduction
ST: N. Planes et al., VLSI tech symp 2012
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
IBM
K.Cheng, IEDM 09
BULK
FDSOILETI
O.Weber, IEDM 08 FinFET
O. Faynot, SOI conf. 2011 short course
Figure of merit: Pelgrom plot => slope ADVt
FDSOI: Introduction
| 12
P = f C Vdd2 + IOFF Vdd
Dynamic or active Power
Static or subthreshold Power
T. C. Chen et al., ISSCC 2006
Fully Depleted Silicon-On-Insulator (FDSOI) Improves the device scalability (vs. bulk): enhanced electrostatics
Reduce the variability thanks to undoped channel
Limits the static power and dynamic power consumptions (low Vdd operation, lowest junction capa, improved subthreshold slope)
…
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
FDSOI
| 13
Adapted from ST (J. Hartmann 2012)
• Transistors run at max frequencies up to 30% faster than bulk CMOS, enabling faster processors
• This puts devices more powerful in the hands of the end user
• The manufacturing process for FD-SOI is much simpler than alternatives and makes extensive use of existing fab infrastructure
• Design porting from bulk is simple and fast
• Transistors are significantly more power efficient than bulk CMOS devices with lower leakage and much wider range of operation points down to lower voltages
• End user devices run cooler and last longer
Simpler.
Cooler.
Faster.
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
Outline
Introduction to planar FDSOI
28nm FDSOI [platform]
Process integration, results reminder, devices partitioning
Multi Vt, back bias effect, variability
14nm FDSOI [development]
Boosters, process integration
Scalability
10nm FDSOI [R&D]
Geometrical scaling, new modules, strain for µ boost
Conclusions
| 14 C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
28nm FDSOI platform: process integration
| 15
Same as bulk Adjustment vs bulk
New module Not use in FD-SOI
Caption:
36 masks for - Dual Vt core oxide - 1.8V I/O oxide - Full active/passives offer - Deep Nwell - 7 metal levels BEOL stack - … Adapted from ST (J. Hartmann 2012)
Gate-first type FEOL same as ST/ISDA 28LP
No complex stressors
FE process: 80% common with ST/ISDA 28LP
20% specific
15% less steps in UTBB vs. 28LP
Same LDD implants for all GO1 devices, incl. SRAM
No pocket implants
BE process: identical to ST/ISDA 28LP
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
28nm FDSOI platform: process integration
| 16
Front End Process Starting wafers: SOI (Si 12nm/BOX 25nm)
After process: 7nm final Si body (undoped channel)
Hybrid bulk-SOI co-integration
Ground-Plane for Vth adjust
Two Vth flavors: RVT, LVT
Contact Poly Pitch (CPP): 114nm
Min. gate length: 24nm
High-K/Metal Gate, Gate First
Si Raised Source & Drain
Ion implantation for SD doping
ST: N. Planes et al., VLSI tech symp 2012
Source Drain
BOX
Gate
HK MG
Key features 28FDSOI 14FDSOI
Min Contact gatepitch CPP
114nm 90nm
M1 pitch 90nm 64nm
Std cell area 1X 0.55X
VT flavours RVT / LVT LVT / SLVT
Lgate in min CPP 24nm → 30nm 20nm → 34nm
Channel SOI 7nm Dual SOI/SiGeOI 6nm
Buried oxide BOX 25nm BOX 20nm
Gate HKMG single metal HKMG dual WF
Source-Drain Single Si epi + I/I Dual epi SiGeB/Si:CP
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
28nm FDSOI platform
| 17
Performance
ST: N. Planes et al., VLSI tech symp 2012
NMOS: ION=1070µA/µm @ IOFF=16nA/µm
PMOS: ION=610µA/µm @ IOFF=30nA/µm
DIBL<100mV/V
SS<85mV/dec
@ VDD=1V
FDSOI is 32% faster than bulk at same leakage @ VDD=1V (84% @ VDD=0.6V) thanks to its superior electrostatics (DIBL)
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
| 18
• +50% energy efficiency, +30% peak performance @ 1.1V • Full technology platform • Longer life time of application processor
28nm FDSOI: ST results reminder
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
Device Type UTBB
FD-SOI BULK
Logic 2Vt / PB0-16nm*
SRAM
Capacitance, Varactor
Drift MOS (OTP)
Digital I/O
Analog MOS
RF MOS
Resistors (Poly) (Active)
Diodes (antenna)
ESD Devices (FET)
(FET, diode, SCR)
Vertical Bipolar
UTBB
FDSOI
side
Box Si
“HYBRID”
Bulk
side
(*) PB = Poly Bias
19
Adapted from ST (J. Hartmann 2012)
Key solutions for ESD protection & Performance enhancement
leti: C. Fenouillet et al., IEDM 2009
28nm FDSOI: devices partitioning
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16 l 19
Multi-VT and applications
p-type n-type
n-well p-well
25nm BOX 25nm BOX
Adjustement of VT versus the different elements that compose a circuit
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
-1.1 -0.9 -0.7 -0.5 -0.3 -0.1 0.1 0.3 0.5 0.7 0.9 1.1
Vg(V)
Id(A
/µm
)@ V
d l
1.1
lV
PMOS
LVT family
Lg 40nm
Tbox 10nm
Vb=-1.1V to
1.1V /0.1V
Vb=1.1V to
-1.1V /-0.1V
HfO2 2.5nm
ALD TiN 10nm
NMOS
0.001
0.01
0.1
1
10
100
0 500 1000 1500
Ion (µA/µm)
Ioff
(n
A/µ
m)
High Performance
Digital Consumer
Wireless
Vitesse d’Execution
Co
nso
mm
atio
n E
lectriq
ue
Bas Vth : Logique
rapide
Vth médian : Logique
Standard
Vth haut: mémoire
SRAM embarquée
C. Fenouillet-Beranger et al. VLSI 2010
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16 l 20
28nm FDSOI: Multi Vt
| 21
Regular Vt: RVT
Low Vt: LVT
p-Well n-Well
NMOS PMOS
n-Well p-Well
NMOS PMOS Gnd
Gnd
Conventional Well
Flip Well
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
20 40 60 80 100V
Tlin
(V
)
LG (nm)
W=10m, VD=50mV
pMOS
nMOS
TaAlN/TaN
TiN
TiN
TaAlN/TaN
close: same GP
open: opposite GP
Close: Conventional well
Open: flip well
RVT LVT
Leti: O. Weber et al., IEDM 2010
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
28nm FDSOI: Back bias effect
| 22
Efficient to modulate the threshold voltage during circuit operation
Reuse of Bulk design techniques No area penalty compared to
Bulk Not possible with FinFET! ION(IOFF) modulation through
Forward and Reverse Back Bias
=> improvement of the speed/Power tradeoff
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
FDSOI
May 2014: Agreement on 28nm FDSOI
| 23
2nd source foundry
SOI
Substrates
Techno-IP
1st foundry
Research
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
Outline
Introduction to planar FDSOI
28nm FDSOI [platform]
Process integration, results reminder, devices partitioning
Multi Vt, back bias effect, variability
14nm FDSOI [development]
Boosters, process integration
Scalability
10nm FDSOI [R&D]
Geometrical scaling, new modules, strain for µ boost
Conclusions
| 24 C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
FDSOI is scalable
28nm FDSOI
10nm FDSOI
14nm FDSOI
0.9V 113CPP 90Mx
0.8V 90CPP 64Mx
0.7V 64CPP 48Mx
2012 2013 2014 2015 2016
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16 l 25
© CEA. All rights reserved
in situ doped RSD
SiGe channel for PFET
Raccess
Vt + µ boost
Performance
14nm FDSOI
10nm FDSOI
| 26
+40
%
at s
ame
Vd
d
+30
%
at s
ame
Vd
d
28nm FDSOI
Strained dual channel technology with in situ doped RSD
Unstrained Si channel technology with implanted RSD
FDSOI scalability: boosters roadmap
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
14nm FDSOI boosters
SGOI pFET for Vth adjust & µ boost Compressively strained SiGe channels with the Ge enrichment process*
leti: L. Hutin et al., VLSI tech symp 2010
| 27
*MIRAI: S. Nakaharai, et al. APL 83, p.3516 (2003)
0
50
100
150
200
250
0 0.2 0.4 0.6 0.8 1 1.2
Universal hole mob.
SOI Y funct.split CV
c-SGOI 25% Y funct.split CV
c-SGOI 35% Y funct.split CV
Ho
le m
ob
ilit
y (
cm
2.V
-1.s
-1)
Eeff
(MV/cm)
LG=10µm
W=10µm
+67%
0
50
100
150
200
250
0 0.2 0.4 0.6 0.8 1 1.2
Universal hole mob.
SOI Y funct.split CV
c-SGOI 25% Y funct.split CV
c-SGOI 35% Y funct.split CV
Ho
le m
ob
ilit
y (
cm
2.V
-1.s
-1)
Eeff
(MV/cm)
LG=10µm
W=10µm0
50
100
150
200
250
0 0.2 0.4 0.6 0.8 1 1.2
Universal hole mob.
SOI Y funct.split CV
c-SGOI 25% Y funct.split CV
c-SGOI 35% Y funct.split CV
Ho
le m
ob
ilit
y (
cm
2.V
-1.s
-1)
Eeff
(MV/cm)
LG=10µm
W=10µm
+67%
10-7
10-5
10-3
10-1
101
103
-1.5 -1 -0.5 0 0.5 1 1.5
I D/W
eff (
µA
/µm
)
VGS
(V)
|VDS
|=1V
LG = 1µm
W = 10µm
pFET
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
14nm FDSOI boosters
Other option: SiGe/SOI pFET Ultrathin SiGe on SOI for Vth adjust & µ boost
SiGe(:B) RSD for Raccess reduction
leti: C. Le Royer et al., IEDM 2011
| 28
BOX
Si0.7Ge0.3:B
RSD
c-SiGe20%
Si cap
Si bottom
BOX
c-SiGe20%
Si cap
Si bottom
BOX
1.E-07
1.E-05
1.E-03
1.E-01
1.E+01
1.E+03
-0.9 -0.7 -0.5 -0.3 -0.1 0.1
Gate voltage (V)
Dra
in c
urr
en
t (µ
A/µ
m) SOI
( A' )
c-Si0.8Ge0.2 / SOI
( B' )
Vth,p shift
~120mV
L = 23nm
W = 80nm
VDS = -0.05V
276 179 196 1100
50
100
150
200
250
300
350
Ra
cc
es
s (
Oh
m.µ
m)
SOI SiGe/SOI
-30% -60%
RSD Si SiGe30% SiGe%30:B
ITRS 15nm: 120Ω.µm
VDS = -0.05V
0
50
100
150
200
250
0.01 0.1 1
Gate length (µm)
Max o
f G
m (
µS
/µm
)
1: SOI
+ RSD SiGe30%
2: SiGe20% channel
+ RSD SiGe30%
1
2
3
A
A'
B'
B'' 3: SiGe20% channel + RSD
in situ doped B SiGe30%
Gate length (µm)
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
14nm FDSOI boosters
+35%
SGOI pFET: IEFF=615µA/µm @ IOFF=100nA/µm, VDS=-0.9V
Dual channel CMOS: SOI nFET + SGOI pFET Compressively strained SiGe channels
with the Ge enrichment process*
SiGe epi on SOI
Ge enrichment => 6nm compressively strained Si0.75Ge0.25 channel
IBM: K. Cheng et al., IEDM 2012
| 29
*MIRAI: S. Nakaharai, et al. APL 83, p.3516 (2003)
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
14nm FDSOI boosters
SOI nFET:
No strain in Si channel
ION=1120µA/µm @ IOFF=100nA/µm, VDS=-0.9V
IEFF=630µA/µm @ IOFF=100nA/µm, VDS=-0.9V
Dual channel CMOS: SOI nFET + SGOI pFET
ST-IBM: Q. Liu et al., IEDM 2013
| 30
25nm TBOX
20nm LG ISPD SiCRSD
Si channel
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
14nm FDSOI boosters
SGOI pFET:
Compressively strained Si0.75Ge0.25 channels: µ boost
Ge enr. + SiGe:B RSD
ION=1220µA/µm @ IOFF=100nA/µm, VDS=-0.9V
IEFF=670µA/µm @ IOFF=100nA/µm, VDS=-0.9V
Dual channel CMOS: SOI nFET + SGOI pFET
ST-IBM: Q. Liu et al., IEDM 2013
| 31
25nm TBOX
ISBD SiGeRSD
Si Ge channel
20nm LG
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
14nm FDSOI boosters
Dual channel CMOS: SOI nFET + SGOI pFET Benchmark: DC performance
| 32
ST-IBM: Q. Liu et al., IEDM 2013
Intel VLSI 2012
FinFET FinFET
Intel IEDM 2012
FDSOI
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
14nm FDSOI boosters
Dual channel CMOS: SOI nFET + SGOI pFET Benchmark: AC performance
Fastest Ring Oscillators performance ever reported!
| 33
ST-IBM: Q. Liu et al., IEDM 2013
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
14nm FDSOI platform: process integration
Process integration 6nm Si / cSiGe dualchannel w. 20nm BOX
(undoped channel)
Hybrid bulk-SOI co-integration
Ground-Plane for Vth adjust
Two Vth flavors: LVT, SLVT
Contact Poly Pitch (CPP): 90nm
Min. gate length: 20nm
High-K/Dual Metal Gate, Gate First
Dual-epi SiC:Ph / SiGe:B Raised S-D
| 34
ST-IBM-leti: O. Weber et al., VLSI tech. symp. 2014
Key features 28FDSOI 14FDSOI
Min Contact gatepitch CPP
114nm 90nm
M1 pitch 90nm 64nm
Std cell area 1X 0.55X
VT flavours RVT / LVT LVT / SLVT
Lgate in min CPP 24nm → 30nm 20nm → 34nm
Channel SOI 7nm Dual SOI/SiGeOI 6nm
Buried oxide BOX 25nm BOX 20nm
Gate HKMG single metal HKMG dual WF
Source-Drain Single Si epi + I/I Dual epi SiGeB/Si:CP
Si
cSiGeOI6nm
BOX 20nm
Hybrid bulk FDSOI
STI
SiPresentation Title
SPWELL
P+ P+
PD & PG PUGND GND
SPWELL
P+ P+
PD & PG PUGND GND
N P
PP
cSi
cSi
NWELLPWELL
NFET LVT PFET LVT
P+ N+
Gnd Vdd
N P
PWELLNWELL
NFET SLVT PFET SLVT
N+ P+
Gnd Gnd
N N
cSiGe
cSiGe
nMOS pMOS
nMOS pMOS
nMOS pMOS
nMOS pMOS
LVT – regular well
SLVT – flip well
Bitcell LL – single Pwell
Bitcell HS – single Pwell
Logic SRAMs
pFET
20nm
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
14nm FDSOI platform:
Performance (2014 Q2):
| 35
0.1
1
10
100
1000
100 200 300 400 500
Ioff
(n
A/µ
m)
Ieff (µA/µm)
Series6
Series5PMOSVdd=0.8VCPP90nmLg=20-34nm
0.1
1
10
100
1000
100 200 300 400 500
Ioff
(n
A/µ
m)
Ieff (µA/µm)
Series2
Series1
NMOSVdd=0.8VCPP90nmLg=20-34nm
0
100
200
300
400
500
600
150 250 350 450 550
Pd
yn =
Idyn
.Vd
d.f
(a.
u.)
Frequency (MHz)
Chart Title
Series7
Series2
Series5
Series1
Power (Series7)
Power (Series2)
Power (Series5)
Power (Series1)
FO3 ROsSilicon data median values
-55%
+30%
-40%
0.9V
0.8V
+20%
Cfr
Cdov
Cpc-tspFET nFET
20nm
IEFF, P = 330µA/µm & IEFF, N = 405µA/µm @ IOFF=20nA/µm, VDD=0.8V
ST-IBM-leti: O. Weber et al., VLSI tech. symp. 2014
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
Outline
Introduction to planar FDSOI
28nm FDSOI [platform]
Process integration, results reminder, devices partitioning
Multi Vt, back bias effect, variability
14nm FDSOI [development]
Boosters, process integration
Scalability
10nm FDSOI [R&D]
Geometrical scaling, new modules, strain for µ boost
Conclusions
| 36 C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
FDSOI is scalable
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16 l 37
© CEA. All rights reserved
in situ doped RSD
SiGe channel for PFET
Raccess
Vt + µ boost
Performance
14nm FDSOI
10nm FDSOI
| 38
+40
%
at s
ame
Vd
d
+30
%
at s
ame
Vd
d
28nm FDSOI
Strained dual channel technology with in situ doped RSD
Unstrained Si channel technology with implanted RSD
Density / capacitance
Raccess
µ boost
sSOI SAIPS…
in situ doped RSD 2nd generation
SAC GL
FDSOI scalability: boosters roadmap
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
10nm FDSOI: Geometrical scaling
Thinner Si body, thinner BOX
| 39
LG LG LG
O. Faynot et al., IEDM 2010
LG, TSOI, and TBOX have impact on DIBL
SOI : Si body scaling down to 3.5nm without impact on performance
A. Khakifirooz et al., IEEE EDL 2012
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
10nm FDSOI: Geometrical scaling
Thinner Si body for enhanced electrostatics
| 40
LG LG LG
Thinner Si body is effective to reduce SCE and DIBL Beware of Si film amorphisation (in case of ion implanted S-D)
Thanks to selective in situ doped epi S-D, access resistance can be controlled down to 5nm SOI film
V. Barral et al., VLSI tech symp 2007
0
20
40
60
80
100
120
2 4 6 8 10 12D
IBL
(m
V/V
)Si film thickness t
SI (nm)
Lg= 20nm
Lg=30nm
Lg=40nm
Lg=80nm
Lg=120nm
Symb. : Experiment
Model
0
20
40
60
80
100
120
2 4 6 8 10 12D
IBL
(m
V/V
)Si film thickness t
SI (nm)
Lg= 20nm
Lg=30nm
Lg=40nm
Lg=80nm
Lg=120nm
Symb. : Experiment
Model
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
10nm FDSOI: Geometrical scaling
Thinner BOX for enhanced electrostatics
| 41
LG LG LG
Thinner BOX is effective to reduce SCE and DIBL
L. Grenouillet et al., S3S conf 2013
5 10 15 20 25
60
70
80
90
100
110
LG = 22nm
LG = 25nm
DIB
L (
mV
)BOX thickness (nm)
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
10nm FDSOI: Geometrical scaling
Thinner BOX for enhanced electrostatics
| 42
LG LG LG
Back bias efficiency improved (body factor improvement)
L. Grenouillet et al., S3S conf 2013
10 1000
50
100
150
Bo
dy F
acto
r (m
V/V
)
BOX thickness (nm)
25nm BOX
20nm BOX
15nm BOX
10nm BOX
28FDSOI
14FDSOI
10FDSOI100mV/V
75mV/V
65mV/V
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
10nm FDSOI: Geometrical scaling
Tighter CPP for higher device density
| 43
Gate
CPP=64nm @ 10nm
Gate
1995 2000 2005 2010 201510
100
1000
0.01
0.1
1
10SRAM Cell AreaContacted Gate Pitch
SR
AM
Ce
ll Are
a (
m2)
Le
ng
th (
nm
)
Year
?
250180
13090
65 45 32
Gate LengthO. Faynot, SOI conf. 2011 short course
LG LG LG
Min CPP (nm)
114 90 64
Leti-ST: H. Niebojewski et al., S3S conf. 2013
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
10nm FDSOI: Geometrical scaling
Tighter CPP for larger device density
| 44
LG LG LG
Min CPP (nm)
114 90 64
Freescale : P. Grudowski et al., VLSI tech symp 2006
Consequence (1/2):
- Benefits of stressors get smaller for tight pitch (bulk, finFET, FD)
=> Need to look at substrate for µ boost IBM: B. Doris, SOI conf. 2011
TCAD
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
10nm FDSOI: Geometrical scaling
Consequence (2/2):
- Less space for contacts
=> Self-Aligned contacts (SAC)
| 45
Leti-ST: H. Niebojewski et al., S3S conf. 2013
Buried Oxide
Substrate
MetalSi
Gate
PMD
Contact CESL
Sp.
RSD
silicide
Buried Oxide
Substrate
MetalSi
SAC
ContactPMD
CESL
Gate
Diel.
Sp.
RSD
silicide
Top
contact
90nm 65nm 45nm 32nm 22nm10
20
30
40
50
60
70
Dim
ensio
n (
nm
)
Technologie Intel
Lg
Contact
Grille-ContactGate-Contact
SAC architecture Classical contacts
Gate- Contact
C. Auth et al., VLSI tech symp 2012
Intel FinFET 22nm w. SAC
Buried Oxide
Substrate
MetalSi
SAC
ContactPMD
CESL
Gate
Diel.
Sp.
RSD
silicide
Top
contact
FDSOI
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
10nm FDSOI: new modules
Self-Aligned contacts (SAC) Mandatory for tight CPP
Misalignment-proof structure
TCAD/SPICE results At the device level:
Geometrical optimizations & low-k spacers to minimize parasitic capacitances
| 46
Leti-ST: H. Niebojewski et al., S3S conf. 2013
10 15 20 25 30 35 40 45
0.20
0.24
0.28
0.32
0.36
0.40
low k
C
tot (f
F/µ
m)
PolySi Thickness (nm)
r(HfO
2)=20
r(SiN)=7
r(SiO
2)=3.9
r(SiCOH)=3
polySi+cap
=constant
=50nm
1 2 3 4 5 6 70.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
optimized arch.
unoptimized arch.
nitri
de
Cto
t (f
F/µ
m)
r(spacers)
air
gap
-47%
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
Ctot reduced with PolySi thickness reduction Further reduction
with airgap
10nm FDSOI: new modules
Self-Aligned contacts (SAC) Mandatory for tight CPP
Misalignment-proof structure
TCAD/SPICE results At the circuit level:
The use of low-k spacers is mandatory to achieve 10nm node delay specifications
| 47 C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
Leti-ST: H. Niebojewski et al., S3S conf. 2013
6
8
10
12
14
16
VDD
=0.8V
W=140nm
Airgap
Spacers
Nitride
Spacers
CBE= 1.5fF/µm
This work
10nmFDSOI SAC
(optimized)
28nm 14nm 10nm6
8
10
12
14
16
VDD
0.8V
VDD
0.9V
VDD
0.9V
Targets
x0.75
x0.75
STMicro. *
VLSI 2012
RO
dela
y/s
tag
e (
ps)
FDSOI node
6 7 8 9 10 11
0.08
0.09
0.10
0.11
0.12
0.13
10
FD
SO
I
ta
rge
t -0.9ps
VDD
=0.8V
W=120n
W=140n
W=170n
CBE
= 1.5fF/µm)
Dyn
am
ic P
ow
er
(mW
)
RO delay/stage (ps)
r(spacers)=7
r(spacers)=1
-0.9ps
Airgap required to meet 10nm FDSOI target
10nm FDSOI: new modules
Gate Last (GL) Pursue the EOT scaling … with a good reliability
due to low thermal budget (in the case of HK last)
Adjust the threshold voltage Gate first: WF tend to midgap + VFB roll-off
Gate last: Easier WF tuning + less VFB roll-off (lower th. budget.)
Induce more strain in the channel: cf. next part
| 48
0 1 2 3 4 54.0
4.2
4.4
4.6
4.8
5.0
5.2
HfO2/TaN
x
HfO2/Ta
0.85 nm
HfO2/TiN/TiAl
HfO2/TiN
Si Mid-Gap
WF
me
ff (
V)
EOT (nm)
Intel: K. Kuhn et al., IWCE 2009 ST-leti: B. Saidi PhD thesis 2013
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
10nm FDSOI: strain for µ boost
sSOI (=SSDOI) wafers Tensily strained Si :
Enhanced electron µ: sSOI improves nMOSFET perf. by 27%
Slightly reduced hole mobility
| 49
IBM: A. Khakifirooz et al., VLSI tech. symp. 2012
0.8 1.0 1.2 1.4 1.6 1.810
-8
10-7
10-6
10-5
VDD
= 0.9V
SSDOI
SOI
(new epi)
SOI [1]
I OFF (
A/
m)
ION
(mA/m)
+27%
0
100
200
300
400
500
600
0 0.2 0.4 0.6 0.8 1 1.2 1.4
Univ. electron mobility
SOI
sSOI 20%
Ele
ctr
on
mo
bilit
y µ
e (
cm
2.V
-1.s
-1)
Eeff
(MV/cm)
+106%
nFET LG=10µm
W=10µm
Leti: L. Hutin et al., IEDM2010
BOX
tens. Si
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
10nm FDSOI: strain for µ boost
sSOI wafers Tensily strained Si :
No variability degradation with sSOI (vs. SOI)
| 50
0
5
10
15
20
25
0 5 10 15 20
1/(L.W)1/2
(µm-1
)
nMOS
σΔ
VT (
mV
)
AVT = 1.15mV.µm
VD=50mV
sSOI
SOI
TSi=12nm
J. Mazurier et al., SOI conf. 2010
BOX
tens. Si
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
10nm FDSOI: strain for µ boost
sSOI wafers: strained SGOI issue 14nm FDSOI:
| 51
BOX
rSi
The final SiGe film exhibits compressive strain (& stress) corresponding to the lattice mismatch between SiGe and SOI
SiGe
rSi
ST-IBM: Q. Liu et al., IEDM 2013
From S. Nakaharai et al., APL 83, p.3516 (2003)
cSiGe rSi 14nm SOI wafer
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
10nm FDSOI: strain for µ boost
sSOI wafers: strained SGOI issue 10nm FDSOI w. sSOI
Drawback for strained SGOI
| 52
« 10nm » sSOI wafer
BOX
tSi (eq. 20%) xSiGe tSi
SiGe
The strain in the final SiGe is delayed because of the tensily strained Si (sSOI) lattice cq: strain and µ loss
tSi (eq. 20%)
T. Tezuka et al., APL 2003
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
10nm FDSOI: strain for µ boost
sSOI wafers: strained SGOI issue 10nm FDSOI w. sSOI
Solution for strained SGOI:
| 53
BOX
tSi (eq. 20%) tSi
SiGe
rSi tSi
cSiGe tSi
10nm sSOI wafer
rSi
Locally relax the tensile strain in the pMOSFET area (for efficient Ge enrichment)
T. Tezuka et al., APL 2003
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
10nm FDSOI: strain for µ boost
Self-Aligned In-Plane Stressors (SAIPS) Principle: Increase the Ge content in the SGOI film in the SD
regions of pMOSFETs (before SD epi)
Advantages:
Uniaxial compressive strain + high transmission efficiency
Self-aligned process
No modification of the channel itself
| 54
L. Grenouillet et al., S3S conf 2013
SiGe
BOX STI
Si
BOX STI
pMOS nMOS
SiC:P SiC:P SiGe40% SiGe40%
SiGe:B SiGe:B
STI
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
10nm FDSOI: strain for µ boost
Self-Aligned In-Plane Stressors (SAIPS) First morpho results: SOI case
1) Ge mapping
a
30% Ge content difference between channel and stressors
| 55
EDX
Dark field STEM
SiGe
gate
channelstressor stressor
2) Strain mapping
SAIPS induce an additional -0.9% compressive strain in the channel
L. Grenouillet et al., S3S conf 2013
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
Slicing Width effect:
Biaxial to uniaxial strain transition when width decreases
FD cSiGe pMOSFET performance increase by >60%
| 56
0.5
1
1.5
2
2.5
3
3.5
0.1 1 10
Dra
in c
urr
en
t e
nh
an
ce
men
t
I D(W
eff)
/ I D
, S
OI (
We
ff=
10µ
m)
Wdesign
(µm)
LG=10µm
VDS
=-50mV
VGS
-Vth
=-0.67V
<110> pFET0.5
1
1.5
2
2.5
3
3.5
0.1 1 10
Dra
in c
urr
en
t e
nh
an
ce
men
t
I D(W
eff)
/ I D
, S
OI (
We
ff=
10µ
m)
Wdesign
(µm)
LG=10µm
VDS
=-50mV
VGS
-Vth
=-0.67V
<110> pFET
Biaxial
Uniaxial
I D,l
ine
nh
ance
me
nt
leti: L. Hutin et al., VLSI tech symp 2010
IBM: K. Cheng et al., IEDM 2012
MIRAI: S. Takagi et al., IEEE TED 2008
10nm FDSOI: strain for µ boost
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
Slicing: Cutting a nominal device into a striped device
Current per active width increases
Effective active width decreases
Effective capacitance decreases
| 57
10nm FDSOI: strain for µ boost
Nom
inal
wid
th
Wst
ripe
Nominal device Striped device
Wsp
ace
Nom
inal
wid
th
Wst
ripe
Nominal device Striped device
Wsp
ace
S D
G
L. Grenouillet et al., S3S conf 2013
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
Gate Last Pursue the EOT scaling … with a good reliability
Adjust the threshold voltage
Induce more strain in the channel
Dummy gate removal increases the stress from SiGe S-D
Bulk: Sony, Intel…
FDSOI: leti
| 58
10nm FDSOI: strain for µ boost
Intel: C. Auth et al., VLSI tech symp 2008
Sony: J. Wang et al., VLSI tech symp 2007
INTEL, 45nm
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
© CEA. All rights reserved
| 59
What will scaled-FDSOI offer … … down to 10nm ?
• Intrinsic gain in performance
• Back-bias: speed/power control
Performance
• Soft design transition
• Low VT dispersion
• Hybrid bulk/FDSOI for maximal IP re-use
Risk-contained design
transition
• A simple process (15% less step than 28LPM): positive impact on cost and yield
A cost-optimized
silicon solution
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
© CEA. All rights reserved
| 60
When will scaled FDSOI deliver?
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
© CEA. All rights reserved
in situ doped RSD
SiGe channel for PFET
Raccess
Vt + µ boost
Performance
14nm FDSOI
10nm FDSOI
| 61
+40
%
at s
ame
Vd
d
+30
%
at s
ame
Vd
d
28nm FDSOI
Density / capacitance
Raccess
µ boost
sSOI SAIPS, GL…
in situ doped RSD 2nd generation
SAC GL
FDSOI: conclusion
28FD has already demonstrated its advantages
Scaling enablers & perf. boosters identified to address the 10FD
14FD demonstrates state of the art results
C. Fenouillet-Beranger et al, Advanced planar FDSOI devices 2014/07/16
© CEA. All rights reserved
| 62
Advanced CMOS roadmap
Early design coupling
28FDSOI
28nm
14nm
10nm
7nm
5nm
Evolutionary scaling: technology driven performance improvement
14FDSOI 10FDSOI
High mobility materials Ge and III-V
Non planar / trigate / stacked NW
Early material and process coupling
Mechanical switches
Hyb
rid
logi
c Steep slope devices
Single Electron Transistor
Disruptive scaling
Monolithic3D – M3D
FinFET
Alternative to scaling
Ge 10 nm
BOX
Si02
25nm TBOX
20nm LG ISPD SiCRSD
Si channel
Source
Drain
Gate
Fin
Source
Drain
Gate
Fin
C. Le Royer, Advanced nano-transistors: from Si to Ge, from planar FD to Nanowire, from CMOS to TFET, NanoKISS 2014
Thank you
| 63
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