advanced digital design limits of synchonous design by a. steininger and m. delvai vienna university...
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Advanced Digital DesignAdvanced Digital DesignLimits of Synchonous DesignLimits of Synchonous Design
by A. Steininger and M. DelvaiVienna University of Technology
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 2
OutlineOutline
Defining the Ideal Design StyleDefining the Ideal Design Style
Timed Communication ModelTimed Communication Model
Control Flow ConditionsControl Flow Conditions
Classification of Sychronous DesignClassification of Sychronous Design
Benefits of Synchronous DesignBenefits of Synchronous Design
Problems with Synchronous DesignProblems with Synchronous Design
EvaluationEvaluation
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 3
Resume 2Resume 2
In practice temporal relations DO In practice temporal relations DO matter for a design.matter for a design.
Boolean logic is not capable of Boolean logic is not capable of expressing them.expressing them.
This causes consistency problems, This causes consistency problems, glitches and runts.glitches and runts.
We need other means of introducing We need other means of introducing the missing information.the missing information.
This is exactly the purpose of a This is exactly the purpose of a design style.design style.
recall
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 4
„„Root of all Evil“Root of all Evil“
gate receiving contradictory signals gate receiving contradictory signals simultaneously on different inputssimultaneously on different inputs
runt pulse (marginal pulse in value or runt pulse (marginal pulse in value or time domain)time domain)
potential metastability in storage looppotential metastability in storage loop propagation of runt and/or propagation of runt and/or
metastability metastability „„Byzantine“ interpretation of runt Byzantine“ interpretation of runt
and/or metastabilityand/or metastability
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 5
What we actually needWhat we actually need
SRC SNK f(x) f(x)
When it is valid and consistent
When SNK has consumed the previous one
When can SNK use its input?
When can SRC apply the next input?
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 6
Our OptionsOur Options
We must only use consistent input We must only use consistent input vectorsvectors
How can we tell an input vector is How can we tell an input vector is consistent?consistent?
(1) use TIME to mark consistent phases(1) use TIME to mark consistent phases synchronous approachsynchronous approach asynchronous/bounded delayasynchronous/bounded delay
(2) use CODING to add information(2) use CODING to add information asynchronous/delay insensitiveasynchronous/delay insensitive
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 7
A Fair ComparisonA Fair Comparison
The purpose of a design style is to provide The purpose of a design style is to provide information for flow control.information for flow control.
Boolean Logic alone cannot provide this Boolean Logic alone cannot provide this information.information.
Severe technological problems force us to Severe technological problems force us to question the current (synchronous) design question the current (synchronous) design practice. We shall focus on that.practice. We shall focus on that.
Alternatives must be evaluated very Alternatives must be evaluated very critically with respect to improvements critically with respect to improvements concerning power, area, robustness, ease of concerning power, area, robustness, ease of composition, testability and performance.composition, testability and performance.
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 8
The market demands …The market demands …
… … faster chips faster chips („performance“)(„performance“)
… … smaller chips smaller chips („embedded“)(„embedded“)
… … cheaper products cheaper products („consumer prod.“)(„consumer prod.“)
… … more functions more functions („features“)(„features“)
… … battery supply battery supply („mobile“)(„mobile“)
… … robust operation robust operation („reliable“)(„reliable“)
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 9
Technology‘s AnswerTechnology‘s Answer
MiniaturizationMiniaturization makes chips … makes chips … … … fasterfaster
… … smallersmaller
… … cheapercheaper
… … more complex & powerfulmore complex & powerful
… … (ultimately)(ultimately) more power-hungry more power-hungry
… … more error-pronemore error-prone
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 10
Vizualizing MiniaturizationVizualizing Miniaturization
n Transistors1995
n Transistors2000
n Transistors2005
n Transistors2010
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 11
The Chip Design CrisisThe Chip Design Crisis
designer productivity gap
hard physical limits impede miniaturization
excessive test complexityheat problems
power delivery problems
increasing transient fault rateshard physical limits
impede speed-up
increasing NRE costs
short time-to-market
Do we need a new („revolutionary“) design approach?
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 12
The MOS TransistorThe MOS Transistor
S G D
B
nn
n-channel enhancement FET contacts
gate oxide
n+
substrate
channel
LW
TOX
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 13
Scaling TheoryScaling Theory
„„Scaling technology by Scaling technology by scales… scales… area byarea by 1/1/22
transistor current bytransistor current by 1/1/ transistor power bytransistor power by 1/1/22
power density power density (pwr/area)(pwr/area) by by 11 “ “
This is no more true for tech-This is no more true for tech-nology nodes below 100nm!nology nodes below 100nm!
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 14
Static Power ConsumptionStatic Power Consumption
gate tunnel currentsgate tunnel currents ((currents over gate oxide)currents over gate oxide)
grow exponentially for thinner oxidegrow exponentially for thinner oxide subthreshold currentssubthreshold currents
( (currents over „open“ transistor)currents over „open“ transistor)
grow for lower threshold voltagegrow for lower threshold voltage leakage currentsleakage currents
((currents over reverse biased junction)currents over reverse biased junction)
can be decreased by SOI, e.g.can be decreased by SOI, e.g.
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 15
Dynamic Power ConsumptionDynamic Power Consumption
switching currentsswitching currents(loading parasitic capacitances)(loading parasitic capacitances)
crowbar currentscrowbar currents(imperfect stack switching)(imperfect stack switching)
2DDclkswitch VCfP
clkcrowbar fP
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 16
Power Consumption TrendsPower Consumption Trends
processor power [W]
1000
100
10
1
0.1
0.01
1960 1970 1980 1990 2000 2010
dynamic
static
[Furuyama, DSD’06]
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 17
Limits of MiniaturizationLimits of Miniaturization
charge of an electron does not scale charge of an electron does not scale e = -1,602e = -1,602..1010-19 -19 CC
size of an atom does not scale size of an atom does not scale Si-Atom = 0.05nmSi-Atom = 0.05nm
wave length for lithography does not scale wave length for lithography does not scale UVUV>150nm>150nm
statistics of band model does not scale:statistics of band model does not scale:invalid for small populations (doping)invalid for small populations (doping)
exponential growth of tunnel currentsexponential growth of tunnel currents linear growth of electrical field strengthlinear growth of electrical field strength ……
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 19
Power Delivery ProblemsPower Delivery Problems
need to deliver currents of many need to deliver currents of many amps into chipamps into chip extreme current density in bondings & extreme current density in bondings &
power railspower rails
need to supply huge current spikes need to supply huge current spikes within pswithin ps parasitic inductances criticalparasitic inductances critical buffer capacitances requiredbuffer capacitances required noise margins reducednoise margins reduced
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 20
Time-to-marketTime-to-market
needs to be ever shorterneeds to be ever shorter rapidly changing standardsrapidly changing standards „„last minute“ availability of crucial last minute“ availability of crucial
components/specscomponents/specs exploit market opportunitiesexploit market opportunities
being late causes tremendous being late causes tremendous loss of profitloss of profit
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 21
Productivity GapProductivity Gap
We cannot design as complex chips We cannot design as complex chips as we could manufactureas we could manufacture
need much better tool supportneed much better tool support need to combine pre-designed modulesneed to combine pre-designed modules
log
trans/c
hip
trans/staff/time+59%/a (Moore)
+21%/a
[ITRS]t
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 22
VerificationVerification
Need to make sure that implemen-Need to make sure that implemen-tation matches specification:tation matches specification: all desired functions availableall desired functions available no undesired behaviorno undesired behavior
70% of time spent on verification70% of time spent on verification Model-based approach:Model-based approach:
spec transformed into (high-level) modelspec transformed into (high-level) model model properties formally verifiedmodel properties formally verified model is implemented in HW & SWmodel is implemented in HW & SW
BUT: how check implementation vs. model??BUT: how check implementation vs. model??
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 23
TestTest
Test complexity rises with more than O(Test complexity rises with more than O(nn22) ) with circuit complecitywith circuit complecity
It will soon cost more to test a transistor It will soon cost more to test a transistor than to manufacture itthan to manufacture it
log €cost/transtest costs-29%/a
const
[ITRS]t
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 24
Transient FaultsTransient Faults
……occur 10…100 times more oftenoccur 10…100 times more oftenthan permanent faults todaythan permanent faults today
……originate from storage elements originate from storage elements being upset (directly or indirectly)being upset (directly or indirectly)
……can only be caused by disturbances can only be caused by disturbances with an energy larger than that with an energy larger than that stored in the affected cellstored in the affected cell
… … are often caused by particle hitsare often caused by particle hits(single event upsets: SEUs)(single event upsets: SEUs)
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 25
Fault Rate PredictionsFault Rate Predictions
energy stored in a storage element energy stored in a storage element scales withscales with feature sizefeature size power supplypower supply
energy distribution of particles is energy distribution of particles is non-linearnon-linear significantly more particles towards significantly more particles towards
lower energylower energy
fault potential largely increases fault potential largely increases with every technology nodewith every technology node
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 26
Fault MitigationFault Mitigation
stopping miniaturization stopping miniaturization is not an optionis not an option
technology (materials, shielding,…)technology (materials, shielding,…) keeps fault rate per transistor keeps fault rate per transistor
constantconstant = still overall increase per chip= still overall increase per chip
robust circuit designrobust circuit design requires different design techniquesrequires different design techniques
system-level fault tolerancesystem-level fault tolerance current solutioncurrent solution expensiveexpensive
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 27
Ideal Design MethodIdeal Design Method
An ideal design method …An ideal design method … minimizes power consumptionminimizes power consumption miminizes circuit overheadmiminizes circuit overhead naturally supports composabilitynaturally supports composability naturally aids testabilitynaturally aids testability yields robust circuitsyields robust circuits yields fast circuits.yields fast circuits.
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 28
Solutions ahead?Solutions ahead?
Many people envision a paradigm Many people envision a paradigm shift as the only solutionshift as the only solution
As the pain grows…As the pain grows… so does the willingness to perform such so does the willingness to perform such
a shifta shift so does the incentive to come up with a so does the incentive to come up with a
novel solutionnovel solution
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 29
What we actually needWhat we actually need
SRC SNK f(x) f(x)
When it is valid and consistent
When SNK has consumed the previous one
When can SNK use its input?
When can SRC apply the next input?
recall
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 30
TerminologyTerminology
consistent DW: all bits belong to the same context
valid signal: result of function applied to consistent DW
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 31
Timed Comm. ModelTimed Comm. Model
for details see: M. Delvai, A. Steininger. Solving the fundamental Problem of Digital Design – A Systematic Review of Design Methods, 9th Euromicro Conference on System Design, Dubrovnik 2006.
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 32
Timed Comm. ModelTimed Comm. Model
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 33
The Issue ConditionThe Issue Condition
Control TRGSRC: Have SRC issue the next data word such that the current one can still be safely consumed by SNK.
Formal Condition: tinvalid,x > tsafe,x src > - invalid
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 34
The Capture ConditionThe Capture Condition
Control TRGSNK: Have SNK capture data only after it has become consistent.
Formal Condition: tcons,x > tsnkrdy,x snk > - snktrg
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 35
Our OptionsOur Options
We must only use consistent input We must only use consistent input vectorsvectors
How can we tell an input vector is How can we tell an input vector is consistent?consistent?
(1) use TIME to mark consistent phases(1) use TIME to mark consistent phases synchronous approach / global time basesynchronous approach / global time base asynchronous/bounded delayasynchronous/bounded delay
(2) use CODING to add information(2) use CODING to add information asynchronous/delay insensitiveasynchronous/delay insensitive
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 36
„ „If the problem originates from the If the problem originates from the time domain, why don‘t we solve it in time domain, why don‘t we solve it in the time domain!“the time domain!“
Process inputs only after they have Process inputs only after they have become become stablestable..
Use Use clockclock to signal these instants. to signal these instants.
Synchronous PhilosophySynchronous Philosophy
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 37
Control by Global TimeControl by Global Time
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 38
clock period active clock edge
recovery from transients* clock to output delay * combinational delay* routing delay, …
setup/hold window
HI LO
Synchronous TimingSynchronous Timing
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 39
The Synchronous ConceptThe Synchronous Concept
f(x) f(x)FF1 FF2
TClk
„After some TIME Tclk FF2 can use f(x)‘s output and
at the same time FF1 can apply a new input“
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 40
The ImplicationsThe Implications
Clock Period TClock Period TClkClk = Period = Period Must be determined by static timing Must be determined by static timing
analysisanalysis Phase Phase = = (!) (!)
this implies thatthis implies that
srcsrc = -( = -(snktrgsnktrg + + conscons)) still we must guaranteestill we must guarantee
srcsrc > - > -invalid invalid (issue condition)(issue condition) thereforetherefore
invalidinvalid > > snktrgsnktrg + + conscons
This is This is notnot formally safe – but it works! formally safe – but it works!
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 41
Benefits of Sync. LogicBenefits of Sync. Logic
Simplicity improves productivitySimplicity improves productivity design on high level of abstractiondesign on high level of abstraction
truth table with „previous state“truth table with „previous state“
transients are irrelevent, transients are irrelevent, all considered states are clearly defined all considered states are clearly defined
timing analysis separate, after designtiming analysis separate, after design
clear distinction between data andclear distinction between data and clock simplifies timing analysis clock simplifies timing analysis
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 42
Benefits of Sync. Logic (2)Benefits of Sync. Logic (2)
High implementation efficiency:High implementation efficiency: one singleone single control signal for the control signal for the
complete system! complete system!
periodic clock is easy to generateperiodic clock is easy to generate
single-rail data codingsingle-rail data coding
minimum number of transitions minimum number of transitions on the data rails on the data rails
clock also provides a time baseclock also provides a time base
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 43
Resume 1Resume 1
Synchronous design does workSynchronous design does work billions of working designsbillions of working designs
Synchronous design is VERY efficientSynchronous design is VERY efficient wrt. designwrt. design wrt. implementationwrt. implementation
So everything is solvedSo everything is solved
Is it?Is it?
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 44
The Original ProblemThe Original Problem
SRC SNK f(x) f(x)
When it is valid and consistent
When SNK has consumed the previous one
When can SNK use its input?
When can SRC apply the next input?
recall
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 45
What have we done?What have we done?
We have expressed a simple information related
condition by means of complicated timing related
parameters that we don‘t even know!
DOES IT MATTER ?
recall
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 46
That damned traffic lightThat damned traffic light
YES!
It does matter
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 47
That damned …That damned …
Traffic lightTraffic light number of waiting carsnumber of waiting cars
Microwave ovenMicrowave oven temperature of the foodtemperature of the food
WiperWiper visibility through the front shieldvisibility through the front shield
Stairway lightStairway light presence of a person in the stairwaypresence of a person in the stairway
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 48
What‘s wrong?What‘s wrong?
Often events define important points in time.Often events define important points in time. This does, however, not mean that the This does, however, not mean that the
occurrence of the event can be a priori occurrence of the event can be a priori related to (absolute or relative) time.related to (absolute or relative) time.
BUT: Time is relatively easy to measureBUT: Time is relatively easy to measure Therefore it is often much more efficient to Therefore it is often much more efficient to
establish such an indirect relation than to establish such an indirect relation than to observe the actual event (that is sometimes observe the actual event (that is sometimes invisible)invisible)
This starts to become annoying when the This starts to become annoying when the artificial relation between actual event and artificial relation between actual event and time model is too weak.time model is too weak.
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 49
The Synchronous ApproachThe Synchronous Approach
f(x) f(x)FF1 FF2
TClk
„After some TIME Tclk FF2 can use f(x)‘s output and
at the same time FF1 can apply a new input“
Relating flow control to time in this way is
convenient and effective, but in fact the implied
relation does not (naturally) exist!
We need to establish this relation artificially
during design (timing optimization & constraints)
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 50
The annoying consequencesThe annoying consequences
need to determine clock periodneed to determine clock period circuit functionality is technology dependent circuit functionality is technology dependent considerable design efforts, large design considerable design efforts, large design
loopsloops
need to make worst-case assumptionsneed to make worst-case assumptions necessarily pessimisticnecessarily pessimistic no robustness wrt. exceeding themno robustness wrt. exceeding them
need to maintain global synchronyneed to maintain global synchrony clock distribution problemsclock distribution problems power consumption problemspower consumption problems
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 51
Can we predict Delay?Can we predict Delay?
after synthesis: logic depthafter synthesis: logic depth complexity of operationcomplexity of operation optimization & mappingoptimization & mapping
after routing: interconnectafter routing: interconnect geometrie (lengths, capacitances)geometrie (lengths, capacitances) vias, switchesvias, switches
during operation: actual valuesduring operation: actual values process variationsprocess variations temperaturetemperature supply voltagesupply voltage
recall
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 52
Timing AnalysisTiming Analysis
not possible before not possible before the end of the the end of the design flowdesign flow(large iteration loops!)(large iteration loops!)
Design-Entry
Synth. & Technol.-Mapping
Partitioning & Placement
Routing
Manufact.
Specification
Validation
Behavioral Simulation
Postlayout-GL-Simulation
Prelayout-GL-Simulation
Test
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 53
Timing AnalysisTiming Analysis
not possible before not possible before the end of the the end of the design flowdesign flow(large iteration loops!)(large iteration loops!)
tight & safe esti-tight & safe esti-mation has become mation has become a major issuea major issue
sync model
reality
transients setup/hold
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 54
Timing AnalysisTiming Analysis
not possible beforenot possible beforethe end of thethe end of thedesign flowdesign flow(large iteration loops!)(large iteration loops!)
tight & safe esti-tight & safe esti-mation has becomemation has becomea major issuea major issue
feasible with „ideal“ clock net onlyfeasible with „ideal“ clock net only
original idea: avoid having to deal with transientsoriginal idea: avoid having to deal with transientscurrent practice: timing analysis most difficult current practice: timing analysis most difficult
tPD,CLK
CLK
D
CLK
D
CLK
D
CLK
D
…
tdly,DATA,1m
tdly,DATA,2m
tdly,DATA,km
FF1
FF2
FFk FFmcombin. logic
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 55
normally too pessimisticnormally too pessimisticreal, chip could run fasterreal, chip could run faster
no tolerance when exceededno tolerance when exceededgraceful degradation desirablegraceful degradation desirable
lim
Worst-Case AssumptionsWorst-Case Assumptions
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 56
! Performance Efficiency! Performance Efficiency
real
com
puta
tion
tim
e
20100 50 1030 20
lib: w
orst
vs.
typ
cros
stal
k, IR
dro
ppro
cess
var
iation
cloc
k sk
ewunbal
ance
d
stag
es
[Cortadella, ICCD’04]
%443.1
FF
Fperf tt
tE
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 57
Clock DistributionClock Distribution
clock distribution network widely clock distribution network widely spread over chipspread over chip
minimization of delay & skew very minimization of delay & skew very tedious and costlytedious and costly
A
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 58
! Area Efficiency! Area Efficiency
%505.05.0
5.0
CtrlF
Farea AA
AE
area proportion devoted to intended logic function
area proportion devoted to necessary flow control overhead: clock network
45% [Wilton IEEE Jnl. SSC 2/2005]
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 59
Power DissipationPower Dissipation
clock network con-clock network con-sumes much energysumes much energy
concurrent switching concurrent switching
=> current peaks => current peaks => voltage drops=> voltage drops
permanent switching permanent switching
=> artificial activity=> artificial activity
according to according to publications 40% publications 40% (DEC, e.g.)(DEC, e.g.)
D
CLK
D
CLK
D
CLK
D
CLK
D
CLK
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 60
! Power Efficiency! Power Efficiency
FclkFFtot PPPPP )1()1(
dissipated power (total)
static part
dynamic part control part (dynamic only*)
power for intended function
*Fclk PP
9.19.1
F
F
tot
Fpwr P
P
P
PE
%90
%)10(%3.5
%)100(%53
circuit utilization
* [Duarte]
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 61
f
E(f)max / CE
A
long clock rails are good antennaslong clock rails are good antennas virtually all radiated energy is con-virtually all radiated energy is con-
centrated to one single spectral linecentrated to one single spectral line
Electromagn. InterferenceElectromagn. Interference
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 62
! Composability! Composability
each and every small change in the each and every small change in the design requires a completely new design requires a completely new timing analysistiming analysis
a switch to a new technology a switch to a new technology completely changes the timingcompletely changes the timing
interoperation between IP cores on a interoperation between IP cores on a chip requires detailed specification chip requires detailed specification (and matching) of both(and matching) of both logic function logic function andand timing behaviortiming behavior
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 63
! Robustness! Robustness metastability Issuesmetastability Issues clock = single point of failureclock = single point of failure non-redundant signal codingnon-redundant signal coding no graceful degradationno graceful degradation timing margins help masking faults timing margins help masking faults but they are shrinking!but they are shrinking!
synchrony is a very strong assumptionsynchrony is a very strong assumption=> it takes a lot of efforts to maintain it=> it takes a lot of efforts to maintain it=> „assumption coverage“ is lower=> „assumption coverage“ is lower
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 64
Experimental ResultsExperimental Results
Fault Injection Results for SPEAR [Thesis Rahbaran]
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 65
Fault Masking EffectsFault Masking Effects
electrical maskingelectrical masking too short fault pulse is filtered out by too short fault pulse is filtered out by
(parasitic) low-passes(parasitic) low-passes logical maskinglogical masking
faults on masked gate faults on masked gate inputs are irrelevantinputs are irrelevant
temporal maskingtemporal masking depending on design style signal values depending on design style signal values
are considered only during defined are considered only during defined windows; faults may go unrecognized windows; faults may go unrecognized when outside these windowswhen outside these windows
&
00
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 66
Scan test turns sequential problem into combinational one => hard to beat!
c o m b lo g ic c o m b lo g ic
c o m b lo g ic
re g is te r c h a in
re g is te r ch a in
re g is te r c h a in
Test
Pat
tern
Gen
erat
or
Res
pons
e A
naly
sis
! Testability! Testability
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 67
ConclusionConclusion
An analysis of the data transfer process allows An analysis of the data transfer process allows mapping the trigger conditions for data mapping the trigger conditions for data source and sink to the time domain, yielding source and sink to the time domain, yielding an „issue condition“ and a „capture an „issue condition“ and a „capture condition“.condition“.
This convenient solution is used by some This convenient solution is used by some design styles, in particular the synchronous design styles, in particular the synchronous design.design.
This mapping is, however, not natural.This mapping is, however, not natural. As an alternative signal coding may be used As an alternative signal coding may be used
to control the triggers of source and sink.to control the triggers of source and sink.
Lecture "Advanced Digital Design" © A. Steininger & M. Delvai / TU Vienna 68
ConclusionConclusion
Synchronous design is extremely efficient Synchronous design is extremely efficient wrt. design and testing.wrt. design and testing.
It establishes a relation between It establishes a relation between handshake events and time that becomes handshake events and time that becomes increasingly cumbersome.increasingly cumbersome.
Weak points are inherent robustness and Weak points are inherent robustness and composabilitycomposability
Power efficiency, area efficiency and Power efficiency, area efficiency and performance efficiency are very good in performance efficiency are very good in principle, but limitations in clock principle, but limitations in clock distributions tend to foil these benefits.distributions tend to foil these benefits.
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