adsp-bf561 ez-kit lite evaluation system manual
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ADSP-BF561 EZ-KIT Lite®
Evaluation System Manual
Revision 2.0, January 2005
Part Number82-000811-01
Analog Devices, Inc.One Technology WayNorwood, Mass. 02062-9106 a
Copyright Information© 2005 Analog Devices, Inc., ALL RIGHTS RESERVED. This docu-ment may not be reproduced in any form without prior, express written consent from Analog Devices, Inc.
Printed in the USA.
Limited WarrantyThe EZ-KIT Lite evaluation system is warranted against defects in materi-als and workmanship for a period of one year from the date of purchase from Analog Devices or from an authorized dealer.
DisclaimerAnalog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by impli-cation or otherwise under the patent rights of Analog Devices, Inc.
Trademark and Service Mark NoticeThe Analog Devices logo, VisualDSP++, the VisualDSP++ logo, Blackfin, CROSSCORE, the CROSSCORE logo, and EZ-KIT Lite are registered trademarks of Analog Devices, Inc.
All other brand and product names are trademarks or service marks of their respective owners.
Regulatory Compliance The ADSP-BF561 EZ-KIT Lite evaluation system has been certified to comply with the essential requirements of the European EMC directive 89/336/EEC (inclusive 93/68/EEC) and, therefore, carries the “CE” mark.
The ADSP-BF561 EZ-KIT Lite evaluation system has been appended to Analog Devices Development Tools Technical Construction File refer-enced “DSPTOOLS1” dated December 21, 1997 and was awarded CE Certification by an appointed European Competent Body and is on file.
The EZ-KIT Lite evaluation system contains ESD (electrostatic discharge) sensitive devices. Electro-static charges readily accumulate on the human body and equipment and can discharge without detection. Permanent damage may occur on devices subjected to high-energy discharges. Proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Store unused EZ-KIT Lite boards in the protective shipping package.
CONTENTS
PREFACE
Purpose of This Manual ................................................................. xii
Intended Audience ........................................................................ xiii
Manual Contents .......................................................................... xiii
What’s New in This Manual ........................................................... xiv
Technical or Customer Support ...................................................... xiv
Supported Processors ....................................................................... xv
Product Information ....................................................................... xv
MyAnalog.com .......................................................................... xv
Processor Product Information .................................................. xvi
Related Documents .................................................................. xvi
Online Technical Documentation ........................................... xviii
Accessing Documentation From VisualDSP++ .................... xviii
Accessing Documentation From Windows ............................ xix
Accessing Documentation From Web ................................... xix
Printed Manuals ....................................................................... xix
VisualDSP++ Documentation Set .......................................... xx
Hardware Tools Manuals ....................................................... xx
Processor Manuals ................................................................. xx
ADSP-BF561 EZ-KIT Lite Evaluation System Manual v
CONTENTS
Data Sheets .......................................................................... xx
Notation Conventions ................................................................... xxi
USING EZ-KIT LITE
Package Contents ......................................................................... 1-2
Default Configuration .................................................................. 1-3
Installation and Session Startup ..................................................... 1-5
Evaluation License Restrictions ..................................................... 1-6
External Memory .......................................................................... 1-6
LEDs and Push Buttons ................................................................ 1-9
Audio Interface ........................................................................... 1-10
Video Interface ........................................................................... 1-11
Example Programs ...................................................................... 1-12
Flash Programmer Utility ............................................................ 1-12
Background Telemetry Channel .................................................. 1-13
VisualDSP++ Interface ................................................................ 1-13
Target Options ...................................................................... 1-14
Reset Options ................................................................... 1-14
On Emulator Exit ............................................................. 1-14
XML File ......................................................................... 1-15
Other Options .................................................................. 1-15
Restricted Software Breakpoints ............................................. 1-17
EZ-KIT LITE HARDWARE REFERENCE
System Architecture ...................................................................... 2-2
vi ADSP-BF561 EZ-KIT Lite Evaluation System Manual
CONTENTS
External Bus Interface Unit ...................................................... 2-3
SPORT0 Audio Interface ......................................................... 2-3
SPI Interface ........................................................................... 2-3
Programmable Flags ................................................................. 2-4
PPI Interfaces .......................................................................... 2-6
Video Output (PPI1) .......................................................... 2-7
Video Input (PPI0) ............................................................. 2-8
UART Port .............................................................................. 2-8
Expansion Interface ................................................................. 2-8
JTAG Emulation Port .............................................................. 2-9
Jumper and DIP Switch Settings .................................................. 2-10
Video Configuration Switch (SW2) ....................................... 2-10
Boot Mode Switch (SW3) ...................................................... 2-11
Push Button Enable Switch (SW4) ......................................... 2-12
PPI Clock Select Switch (SW5) .............................................. 2-13
Test DIP Switches (SW10 and SW11) .................................... 2-13
LEDs and Push Buttons .............................................................. 2-14
Reset Push Button (SW1) ...................................................... 2-14
Programmable Flag Push Buttons (SW9–6) ............................ 2-15
Power LED (J7) ..................................................................... 2-15
Reset LEDs (LED2 and LED3) .............................................. 2-15
USB Monitor LED (LED4) ................................................... 2-16
User LEDs (LED12–5, LED20–13) ....................................... 2-16
Connectors ................................................................................. 2-17
ADSP-BF561 EZ-KIT Lite Evaluation System Manual vii
CONTENTS
Expansion Interface (J3–1) .................................................... 2-17
Audio (J4 and J5) .................................................................. 2-18
Video (J6) ............................................................................. 2-18
Power (J7) ............................................................................ 2-18
USB (J8) .............................................................................. 2-19
RS232 (P2) ........................................................................... 2-20
SPORT0 (P3) ....................................................................... 2-20
JTAG (P4) ............................................................................ 2-20
BILL OF MATERIALS
INDEX
viii ADSP-BF561 EZ-KIT Lite Evaluation System Manual
PREFACE
Thank you for purchasing the ADSP-BF561 EZ-KIT Lite®, Analog
Devices, Inc. evaluation system for Blackfin® processors.The Blackfin processors are embedded processors that support a Media Instruction Set Computing (MISC) architecture. This architecture is the natural merging of RISC, media functions, and digital signal processing (DSP) characteristics towards delivering signal processing performance in a microprocessor-like environment.
The evaluation board is designed to be used in conjunction with the Visu-alDSP++® development environment to test the capabilities of the ADSP-BF561 Blackfin processors. The VisualDSP++ development envi-ronment gives you the ability to perform advanced application code development and debug, such as:
• Create, compile, assemble, and link application programs written in C++, C and ADSP-BF561 assembly
• Load, run, step, halt, and set breakpoints in application program
• Read and write data and program memory
• Read and write core and peripheral registers
• Plot memory
Access to the ADSP-BF561 processor from a personal computer (PC) is achieved through a USB port or an optional JTAG emulator. The USB interface gives unrestricted access to the ADSP-BF561 processor and the evaluation board peripherals. Analog Devices JTAG emulators offer faster
ADSP-BF561 EZ-KIT Lite Evaluation System Manual ix
communication between the host PC and target hardware. Analog Devices carries a wide range of in-circuit emulation products. To learn more about Analog Devices emulators and processor development tools, go to http://www.analog.com/dsp/tools/.
ADSP-BF561 EZ-KIT Lite provides example programs to demonstrate the capabilities of the evaluation board.
The ADSP-BF561 EZ-KIT Lite installation is part of the Visu-alDSP++ installation. The EZ-KIT Lite is a licensed product that offers an unrestricted evaluation license for the first 90 days. Once the initial unrestricted 90-day evaluation license expires:
• VisualDSP++ allows a connection to the ADSP-BF561 EZ-KIT Lite via the USB Debug Agent interface only. Con-nections to simulators and emulation products are no longer allowed.
• The linker restricts a users program to 41 KB of internal memory for code space with no restrictions for data space.
The board features:
• Analog Devices ADSP-BF561 processor
256-pin Mini-BGA package30 MHz CLKIN oscillator
• Synchronous Dynamic Random Access Memory (SDRAM)
64 MB (16M x 16 bits x 2 chips)
• Flash Memory
8 MB (4M x 16 bits)
x ADSP-BF561 EZ-KIT Lite Evaluation System Manual
Preface
• Analog Audio Interface
AD1836 A – Analog Devices 96 kHz audio codec 4 input RCA phono jacks (2 Stereo Channels)6 output RCA phono jacks (3 Stereo Channels)
• Analog Video Interface
ADV7183A video decoder w/ 3 input RCA phono jacksADV7179 video encoder w/ 3 output RCA phono jacks
• Universal Asynchronous Receiver/Transmitter (UART)
ADM3202 RS-232 line driver/receiverDB9 male connector
• LEDs
20 LEDs: 1 power (green), 1 board reset (red), 1 USB (red), 16 general purpose (amber), and 1 USB monitor (amber)
• Push Buttons
5 push buttons with debounce logic: 1 reset, 4 programmable flags
• Expansion Interface
PPI0, PPI1, SPI, EBIU, Timers11-0, UART, Programmable Flags, SPORT0, SPORT1
• Other Features
JTAG ICE 14-pin header
The EZ-KIT Lite board holds 8 MB of flash memory, which can be used to store user-specific boot code, allowing the board to run as a stand-alone unit. The board also holds 512-Mb SDRAM, which can be used at runt-ime. For more information see “External Memory” on page 1-6.
ADSP-BF561 EZ-KIT Lite Evaluation System Manual xi
Purpose of This Manual
SPORT0 interfaces with the AD1836A audio codec, allowing you to create audio signal processing applications. SPORT0 also attaches to an off-board connector to allow communication with other serial devices. For informa-tion about SPORT0, see “SPORT0 Audio Interface” on page 2-3.
The Parallel Peripheral Interfaces (PPIs) of the processor connect to both a video encoder and video decoder, allowing you to create video signal processing applications. For information on how the board utilizes the processor’s PPIs, see “PPI Interfaces” on page 2-6.
The UART of the processor connects to an RS232 Line Driver and a DB9 male connector, allowing you to interface with a PC or other serial device. For information about the UART, see “UART Port” on page 2-8.
Additionally, the EZ-KIT Lite board provides access to most of the pro-cessor’s peripheral ports. Access is provided in the form of a three-connector expansion interface. For information about the expansion interface, see “Expansion Interface” on page 2-8.
Purpose of This Manual The ADSP-BF561 EZ-KIT Lite Evaluation System Manual provides instructions for installing the product hardware (board). The text describes the operation and configuration of the board components and provides guidelines for running your own code on the ADSP-BF561 EZ-KIT Lite. Finally, a schematic and a bill of materials are provided as a reference for future designs.
The product software installation is detailed in the VisualDSP++ Installa-tion Quick Reference Card.
xii ADSP-BF561 EZ-KIT Lite Evaluation System Manual
Preface
Intended AudienceThe primary audience for this manual is a programmer who is familiar with Analog Devices processors. This manual assumes that the audience has a working knowledge of the appropriate processor architecture and instruction set. Programmers who are unfamiliar with Analog Devices processors can use this manual but should supplement it with other texts (such as the ADSP-BF561 Blackfin Processor Hardware Reference and Blackfin Processor Instruction Set Reference) that describe your target architecture.
Programmers who are unfamiliar with VisualDSP++ should refer to the VisualDSP++ online Help and user’s or getting started guides. For the locations of these documents, see “Related Documents”.
Manual ContentsThe manual consists of:
• Chapter 1, “Using EZ-KIT Lite” on page 1-1Describes the EZ-KIT Lite functionality from a programmer’s per-spective and provides an easy-to-access memory map
• Chapter 2, “EZ-KIT Lite Hardware Reference” on page 2-1Provides information on the EZ-KIT Lite hardware components.
ADSP-BF561 EZ-KIT Lite Evaluation System Manual xiii
What’s New in This Manual
• Appendix A, “Bill Of Materials” on page A-1Provides a list of components used to manufacture the EZ-KIT Lite board.
• Appendix B, “Schematics” on page B-1Provides the resources to allow EZ-KIT Lite board-level debugging or to use as a reference design.
This appendix is not part of the online Help. The online Help viewers should go to the PDF version of the ADSP-BF561 EZ-KIT Lite Evaluation System Manual located in the Docs\EZ-KIT Lite Manuals folder on the installation CD to see the schematics. Alter-natively, the schematics can be found on the Analog Devices Web site, www.analog.com/processors.
What’s New in This Manual This revision of the ADSP-BF561 EZ-KIT Lite Evaluation System Manual provides an updated listing of related documents and updated licensing information.
Technical or Customer SupportYou can reach DSP Tools Support in the following ways.
• Visit the Embedded Processing and DSP products Web site athttp://www.analog.com/processors/technicalSupport
• E-mail tools questions todsptools.support@analog.com
• E-mail processor questions todsp.support@analog.com
• Phone questions to 1-800-ANALOGD
xiv ADSP-BF561 EZ-KIT Lite Evaluation System Manual
Preface
• Contact your Analog Devices, Inc. local sales office or authorized distributor
• Send questions by mail to:
Analog Devices, Inc.
One Technology Way
P.O. Box 9106
Norwood, MA 02062-9106
USA
Supported ProcessorsThis EZ-KIT Lite evaluation system supports the Analog Devices ADSP-BF561 Blackfin embedded processors.
Product InformationYou can obtain product information from the Analog Devices Web site, from the product CD-ROM, or from the printed publications (manuals).
Analog Devices is online at www.analog.com. Our Web site provides infor-mation about a broad range of products—analog integrated circuits, amplifiers, converters, and digital signal processors.
MyAnalog.comMyAnalog.com is a free feature of the Analog Devices Web site that allows customization of a Web page to display only the latest information on products you are interested in. You can also choose to receive weekly e-mail notifications containing updates to the Web pages that meet your interests. MyAnalog.com provides access to books, application notes, data sheets, code examples, and more.
ADSP-BF561 EZ-KIT Lite Evaluation System Manual xv
Product Information
Registration:
Visit www.myanalog.com to sign up. Click Register to use MyAnalog.com. Registration takes about five minutes and serves as means for you to select the information you want to receive.
If you are already a registered user, just log on. Your user name is your e-mail address.
Processor Product InformationFor information on embedded processors and DSPs, visit our Web site at www.analog.com/processors, which provides access to technical publica-tions, data sheets, application notes, product overviews, and product announcements.
You may also obtain additional information about Analog Devices and its products in any of the following ways.
• E-mail questions or requests for information to dsp.support@analog.com
• Fax questions or requests for information to1-781-461-3010 (North America)+49 (89) 76 903-557 (Europe)
• Access the FTP Web site atftp ftp.analog.com or ftp 137.71.23.21 ftp://ftp.analog.com
Related DocumentsFor information on product related development software, see the follow-ing publications.
xvi ADSP-BF561 EZ-KIT Lite Evaluation System Manual
Preface
If you plan to use the EZ-KIT Lite board in conjunction with a JTAG emulator, also refer to the documentation that accompanies the emulator.
All documentation is available online. Most documentation is available in printed form.
Visit the Technical Library Web site to access all processor and tools man-uals and data sheets:
http://www.analog.com/processors/resources/technicalLibrary
Table 1. Related Processor Publications
Title Description
ADSP-BF561 Blackfin Embedded Symmet-ric Multi-Processor Datasheet
General functional description, pinout, and timing
ADSP-BF561 Blackfin Processor Hardware Reference
Description of internal processor architecture and all register functions
Blackfin Processor Instruction Set Reference Description of all allowed processor assembly instructions
Table 2. Related VisualDSP++ Publications
Title Description
VisualDSP++ User’s Guide Description of VisualDSP++ features and usage
VisualDSP++ Assembler and Preprocessor Manual
Description of the assembler function and com-mands
VisualDSP++ C/C++ Complier and Library Manual for Blackfin Processors
Description of the complier function and com-mands for Blackfin processors
VisualDSP++ Linker & Utilities Manual Description of the linker function and commands
VisualDSP++ Loader Manual Description of the loader/splitter function and com-mands
ADSP-BF561 EZ-KIT Lite Evaluation System Manual xvii
Product Information
Online Technical Documentation Online documentation comprises the VisualDSP++ Help system, software tools manuals, hardware tools manuals, processor manuals, the Dinkum Abridged C++ library, and Flexible License Manager (FlexLM) network license manager software documentation. You can easily search across the entire VisualDSP++ documentation set for any topic of interest. For easy printing, supplementary .PDF files of most manuals are provided in the Docs folder on the VisualDSP++ installation CD.
Each documentation file type is described as follows.
If documentation is not installed on your system as part of the software installation, you can add it from the VisualDSP++ CD at any time by run-ning the Tools installation. Access the online documentation from the VisualDSP++ environment, Windows® Explorer, or the Analog Devices Web site.
Accessing Documentation From VisualDSP++
To view VisualDSP++ Help, click on the Help menu item or go to the Windows task bar and navigate to the VisualDSP++ documentation via the Start menu.
File Description
.CHM Help system files and manuals in Help format
.HTM or
.HTMLDinkum Abridged C++ library and FlexLM network license manager software doc-umentation. Viewing and printing the .HTML files requires a browser, such as Internet Explorer 4.0 (or higher).
.PDF VisualDSP++ and processor manuals in Portable Documentation Format (PDF). Viewing and printing the .PDF files requires a PDF reader, such as Adobe Acrobat Reader (4.0 or higher).
xviii ADSP-BF561 EZ-KIT Lite Evaluation System Manual
Preface
To view ADSP-BF561 EZ-KIT Lite Help, which is part of the Visu-alDSP++ Help system, use the Contents or Search tab of the Help window.
Accessing Documentation From Windows
In addition to any shortcuts you may have constructed, there are many ways to open VisualDSP++ online Help or the supplementary documenta-tion from Windows.
Help system files (.CHM) are located in the Help folder, and .PDF files are located in the Docs folder of your VisualDSP++ installation CD-ROM. The Docs folder also contains the Dinkum Abridged C++ library and the FlexLM network license manager software documentation.
Your software installation kit includes online Help as part of the Win-dows® interface. These help files provide information about VisualDSP++ and the ADSP-BF561 EZ-KIT Lite evaluation system.
Accessing Documentation From Web
Download manuals at the following Web site: http://www.analog.com/processors/resources/technicalLibrary/man-
uals.
Select a processor family and book title. Download archive (.ZIP) files, one for each manual. Use any archive management software, such as WinZip, to decompress downloaded files.
Printed ManualsFor general questions regarding literature ordering, call the Literature Center at 1-800-ANALOGD (1-800-262-5643) and follow the prompts.
ADSP-BF561 EZ-KIT Lite Evaluation System Manual xix
Product Information
VisualDSP++ Documentation Set
To purchase VisualDSP++ manuals, call 1-603-883-2430. The manuals may be purchased only as a kit.
If you do not have an account with Analog Devices, you are referred to Analog Devices distributors. For information on our distributors, log onto http://www.analog.com/salesdir/continent.asp.
Hardware Tools Manuals
To purchase EZ-KIT Lite and In-Circuit Emulator (ICE) manuals, call 1-603-883-2430. The manuals may be ordered by title or by product number located on the back cover of each manual.
Processor Manuals
Hardware reference and instruction set reference manuals may be ordered through the Literature Center at 1-800-ANALOGD (1-800-262-5643), or downloaded from the Analog Devices Web site. Manuals may be ordered by title or by product number located on the back cover of each manual.
Data Sheets
All data sheets (preliminary and production) may be downloaded from the Analog Devices Web site. Only production (final) data sheets (Rev. 0, A, B, C, and so on) can be obtained from the Literature Center at 1-800-ANALOGD (1-800-262-5643); they also can be downloaded from the Web site.
To have a data sheet faxed to you, call the Analog Devices Faxback System at 1-800-446-6212. Follow the prompts and a list of data sheet code numbers will be faxed to you. If the data sheet you want is not listed, check for it on the Web site.
xx ADSP-BF561 EZ-KIT Lite Evaluation System Manual
Preface
Notation ConventionsText conventions used in this manual are identified and described as follows.
Example Description
Close command (File menu)
Titles in reference sections indicate the location of an item within the VisualDSP++ environment’s menu system (for example, the Close command appears on the File menu).
{this | that} Alternative required items in syntax descriptions appear within curly brackets and separated by vertical bars; read the example as this or that. One or the other is required.
[this | that] Optional items in syntax descriptions appear within brackets and sepa-rated by vertical bars; read the example as an optional this or that.
[this,…] Optional item lists in syntax descriptions appear within brackets delimited by commas and terminated with an ellipse; read the example as an optional comma-separated list of this.
.SECTION Commands, directives, keywords, and feature names are in text with letter gothic font.
filename Non-keyword placeholders appear in text with italic style format.
Note: For correct operation, ...A Note provides supplementary information on a related topic. In the online version of this book, the word Note appears instead of this
symbol.
Caution: Incorrect device operation may result if ...Caution: Device damage may result if ... A Caution identifies conditions or inappropriate usage of the product that could lead to undesirable results or product damage. In the online version of this book, the word Caution appears instead of this symbol.
Warning: Injury to device users may result if ... A Warning identifies conditions or inappropriate usage of the product that could lead to conditions that are potentially hazardous for the devices users. In the online version of this book, the word Warning appears instead of this symbol.
ADSP-BF561 EZ-KIT Lite Evaluation System Manual xxi
Notation Conventions
Additional conventions, which apply only to specific chapters, may appear throughout this document.
xxii ADSP-BF561 EZ-KIT Lite Evaluation System Manual
1 USING EZ-KIT LITE
This chapter provides specific information to assist you with development
of programs for the ADSP-BF561 EZ-KIT Lite evaluation system.The information appears in the following sections.
• “Package Contents” on page 1-2Lists the items contained in your ADSP-BF561 EZ-KIT Lite package.
• “Default Configuration” on page 1-3Shows the default configuration of the ADSP-BF561 EZ-KIT Lite.
• “Installation and Session Startup” on page 1-5Instructs how to start a new or open an existing ADSP-BF561EZ-KIT Lite session using VisualDSP++.
• “Evaluation License Restrictions” on page 1-6Describes the restrictions of the VisualDSP++ demo license shipped with the EZ-KIT Lite.
• “External Memory” on page 1-6Defines the ADSP-BF561 EZ-KIT Lite’s external memory map.
• “LEDs and Push Buttons” on page 1-9·Describes the board’s LEDs and push buttons.
• “Audio Interface” on page 1-10Describes the board’s audio interface.
• “Video Interface” on page 1-11Describes the board’s video interface.
ADSP-BF561 EZ-KIT Lite Evaluation System Manual 1-1
Package Contents
• “Example Programs” on page 1-12Provides information about the example programs included in the ADSP-BF561 EZ-KIT Lite evaluation system.
• “Flash Programmer Utility” on page 1-12Highlights the advantages of the Flash Programmer utility of VisualDSP++.
• “Background Telemetry Channel” on page 1-13Highlights the advantages of the Background Telemetry Channel feature of VisualDSP++.
• “VisualDSP++ Interface” on page 1-13Describes the target options facilities of the EZ-KIT Lite system.
For more detailed information about programming the ADSP-BF561 Blackfin processor, see the documents referred to as “Related Documents”.
Package ContentsYour ADSP-BF561 EZ-KIT Lite evaluation system package contains the following items.
• ADSP-BF561 EZ-KIT Lite board
• VisualDSP++ Installation Quick Reference Card
• CD containing:
VisualDSP++ softwareADSP-BF561 EZ-KIT Lite softwareUSB driver filesExample programsADSP-BF561 EZ-KIT Lite Evaluation System Manual (this document)
1-2 ADSP-BF561 EZ-KIT Lite Evaluation System Manual
Using EZ-KIT Lite
• Universal 7.5V DC power supply
• USB 2.0 cable
• Registration card (please fill out and return)
If any item is missing, contact the vendor where you purchased your EZ-KIT Lite or contact Analog Devices, Inc.
Default Configuration
The ADSP-BF561 EZ-KIT Lite board is designed to run outside your per-sonal computer as a stand-alone unit. You do not have to open your computer case.
When removing the EZ-KIT Lite board from the package, handle the board carefully to avoid the discharge of static electricity, which may dam-age some components. Figure 1-1 shows the default jumper settings, DIP switch, connector locations, and LEDs used in installation. Confirm that your board is set up in the default configuration before using the board.
The EZ-KIT Lite evaluation system contains ESD (electrostatic discharge) sensitive devices. Electrostatic charges readily accumulate on the human body and equipment and can discharge without detection. Per-manent damage may occur on devices subjected to high-energy discharges. Proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Store unused EZ-KIT Lite boards in the protective shipping package.
ADSP-BF561 EZ-KIT Lite Evaluation System Manual 1-3
Default Configuration
Figure 1-1. EZ-KIT Lite Hardware Setup
1-4 ADSP-BF561 EZ-KIT Lite Evaluation System Manual
Using EZ-KIT Lite
Installation and Session StartupFor correct operation, install the software and hardware in the order presented in the VisualDSP++ Installation Quick Reference Card.
1. Verify that the yellow USB monitor LED (LED4, located near the USB connector) is lit. This signifies that the board is communicat-ing properly with the host PC and is ready to run VisualDSP++.
2. From the Start menu, navigate to the VisualDSP++ environment via the Programs menu.If you are running VisualDSP++ for the first time, the New Session dialog box appears on the screen (skip the rest of the procedure and go to step 3).If you have run VisualDSP++ previously, the last opened session appears on the screen.To switch to another session, via the Session List dialog box, hold down the Ctrl key while starting VisualDSP++ (go to step 5).
3. In Debug target, select Blackfin Emulators/EZ-KIT Lites.In Platform, select the appropriate EZ-KIT Lite via a debug agent(ADSP-BF561 EZ-KIT Lite via Debug Agent). In Session name, type a new name or accept the default.
4. Click OK to return to the Session List.
5. Highlight the session and click Activate.
ADSP-BF561 EZ-KIT Lite Evaluation System Manual 1-5
Evaluation License Restrictions
Evaluation License RestrictionsThe ADSP-BF561 EZ-KIT Lite installation is part of the VisualDSP++ installation. The EZ-KIT Lite is a licensed product that offers an unre-stricted evaluation license for the first 90 days. Once the initial unrestricted 90-day evaluation license expires:
• VisualDSP++ allows a connection to the ADSP-BF561 EZ-KIT Lite via the USB Debug Agent interface only. Connections to sim-ulators and emulation products are no longer allowed.
• The linker restricts a users program to 41 KB of internal memory for code space with no restrictions for data space.
The EZ-KIT Lite hardware must be connected and powered up to use VisualDSP++ with a valid evaluation or permanent license.
Refer to the VisualDSP++ Installation Quick Reference Card for details.
External MemoryEZ-KIT Lite board includes two types of external memory, 64-MB SDRAM and 8-MB flash. Table 1-1 shows the memory map of these devices. The complete configuration of the ADSP-BF561 processor inter-nal SRAM is detailed in Figure 1-2.
Table 1-1. EZ-KIT Lite External Memory Map
Start Address End Address Description
0x00000000 0x3FFFFFF SDRAM Bank 0; see “External Memory” on page 1-6
0x20000000 0x207FFFFF ASYNC Memory Bank 0; see “External Memory” on page 1-6.
All other locations Not used
1-6 ADSP-BF561 EZ-KIT Lite Evaluation System Manual
Using EZ-KIT Lite
The 8 MB of flash memory is organized as 4M x 16 bit and mapped into a ADSP-BF561 processor’s ASYNC Memory Bank 0 (~AMS0, memory select signal connects to the flash memory’s output enable pin).
The 64 MB of SDRAM is organized as 16M x 32 bits wide. The proces-sor’s memory select pin ~SMS0 is configured for the SDRAM. Three SDRAM control registers must be initialized in order to access the SDRAM memory.
When in a VisualDSP++ EZ-KIT Lite session, you can automatically con-figure the SDRAM registers by selecting the Use XML reset values box on the Target Options dialog box, which is accessible through the Settings
Figure 1-2. ADSP-BF561 Processor Internal Memory Map
L1 SCRATCHPAD SRAM (4K)
L1 INSTRUCTION SRAM/CACHE (16K)
L1 INSTRUCTION SRAM (16K)
L1 DATA BANK B SRAM/CACHE (16K)
L1 DATA BANK B SRAM (16K)
L1 DATA BANK A SRAM/CACHE (16K)
L1 DATA BANK A SRAM (16K)
CORE A MEMORY MAP CORE B MEMORY MAP
CORE MMR REGISTERS CORE MMR REGISTERS
SYSTEM MMR REGISTERS
L1 SCRATCHPAD SRAM (4K)
RESERVED
L1 INSTRUCTION SRAM/CACHE (16K)
L1 INSTRUCTION SRAM (16K)
L1 DATA BANK B SRAM/CACHE (16K)
L1 DATA BANK B SRAM (16K)
L1 DATA BANK A SRAM/CACHE (16K)
L1 DATA BANK A SRAM (16K)
L2 SRAM (128K)
0XFFE0 0000
0XFFC0 0000
0XFFB0 1000
0XFFB0 0000
0XFFA1 4000
0XFFA1 0000
0XFFA0 4000
0XFFA0 00000XFF90 8000
0XFF90 4000
0XFF90 0000
0XFF80 8000
0XFF80 4000
0XFF80 0000
0XFF70 1000
0XFF70 0000
0XFF61 4000
0XFF50 4000
0XFF50 0000
0XFF40 8000
0XFF40 4000
0XFF40 0000
0XFEB2 0000
0XFEB0 0000
0XEF00 0800
0XFF61 0000
0XFF60 4000
0XFF60 0000
0XFF50 8000
0XFFFF FFFF
RESERVED
RESERVEDRESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
ADSP-BF561 EZ-KIT Lite Evaluation System Manual 1-7
External Memory
pull-down menu. The values for the EBIU_SDGCTL, EBIU_SDBCTL, and EBIU_SDRRC registers have been set in the ADSP-BF561.xml file found in your VisualDSP\SYSTEM folder under the RegReset tag. These values can be changed to be more optimal depending on the SCLK frequency.
The values in Table 1-2 are programmed by default whenever Bank 0 is accessed through the debugger (for example, when viewing memory win-dows or loading a program). The numbers are derived for maximum flexibility and work for a system clock frequency between 60 MHz and 133 MHz.
The EBIU_SDGCTL register can only be written once after the processor comes out of reset. Therefore, the user code should not reinitialize this register. Clearing the Use XML reset values checkbox allows manual con-figuration of the EBIU registers. For more information, see “Target Options” on page 1-14.
Automatic configuration of the SDRAM is not optimized for a specific SCLK frequency. Table 1-3 shows the optimized configuration for the SDRAM registers using a 120 MHz SCLK. The frequency of 120 MHz is the maximum SCLK frequency when using a 600 MHz core frequency, the maximum frequency for the EZ-KIT Lite. Only the SDRRC register needs to be modified in the user code to achieve maximum performance.
Table 1-2. EZ-KIT Lite Session SDRAM Default Settings
Register Value Function
EBIU_SDGCTL 0x0091998D Calculated with SCLK = 133 MHz
EBIU_SDBCTL 0x00000013
EBIU_SDRRC 0x000001CF Calculated with SCLK = 120 MHz
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For more information about the memory connection on the EZ-KIT Lite, see “External Bus Interface Unit” on page 2-3.
An example program is included in the EZ-KIT installation direc-tory to demonstrate how to set up the SDRAM interface.
LEDs and Push ButtonsThe EZ-KIT Lite provides four push buttons and sixteen LEDs for gen-eral-purpose IO.
Sixteen LEDs labeled LED5 through LED20 are controlled by the processor’s programmable flags PF32 through PF47 (equivalent to PPI0 D15–8 and PPI1 D15–8). These LEDs are accessed through the Flag 2 registers. First, the direction must be configured to output by setting the bits of the FIO2_DIR register to “1”. Then the value of the LEDs can be modified using one the FIO2_FLAG_D, FIO2_FLAG_C, FIO2_FLAG_S, or FIO2_FLAG_T registers.
The four general-purpose push buttons are labeled SW6 through SW9. These connect to the programmable flags PF8–5. A status of each individual but-ton can be read through the FIO0_FLAG_D register. When the corresponding bit of the register reads “1”, a switch is being pressed-on. When the switch is released, the bit reads “0”. A connection between the
Table 1-3. SDRAM Optimum Settings1
Register Value
EBIU_SDGCTL 0x0091998D
EBIU_SDBCTL 0x00000013
EBIU_SDRRC 0x000003A0
1 Calculated with SCLK = 120 MHz
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Audio Interface
push button and PF input is established through the SW4 DIP switch. For information on how to disconnect the switch from the programmable flag and use it for another objective, see “Push Button Enable Switch (SW4)”.
An example program is included in the EZ-KIT installation direc-tory to demonstrate the functionality of the LEDs and push buttons.
Audio InterfaceThe AD1836A audio codec provides three channels of stereo audio output and two channels of multichannel 96 kHz input. The SPORT0 interface of the processor links with the stereo audio data input and output pins of the AD1836A codec. The processor is capable of transferring data to the audio codec in Time-Division Multiplexed (TDM) or Two-Wire Interface (TWI) mode.
The TWI mode allows the codec to operate with a 96 kHz sample rate but restricts the output to two channels. TDM mode can operate at a maxi-mum of 48 kHz sample rate but allows simultaneous use of all input and output channels. When using TWI mode, the TSCLK0 and RSCLK0 pins, as well as the TFS0 and RFS0 pins of the processor, must be tied together externally to the processor. This is accomplished with the SW4 DIP switch. See “Push Button Enable Switch (SW4)” on page 2-12 for more information.
The AD1836A audio codec’s internal configuration registers are config-ured using the processor’s PF4 programmable flag pin is used as the select for this device. For more information on how to configure the multichan-nel codec, download the datasheet from Analog Devices website, www.analog.com.
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The AD1836A codec reset is controlled by the processor’s programmable flag PF15. When PF15 is “0”, the reset is asserted. When PF15 is “1”, the reset is de-asserted. Note, when PF15 is not driven (configured as input), the AD1836A reset is asserted due to the pull-down resistor. See “Pro-grammable Flags” on page 2-4 for more information.
Example programs are included in the EZ-KIT installation direc-tory to demonstrate the AD1836A codec operation.
Video InterfaceThe board supports video input and output applications. The ADV7179 video encoder provides up to three output channels of analog video, while the ADV7183A video decoder provides up to three input channels of ana-log video. The video encoder connects to the Parallel Peripheral Interface 1 (PPI1), while the video decoder connects to the Parallel Peripheral Interface 0, (PPI0). Each PPI interface has an individual clock that is configured by the SW5 switch settings. See “PPI Clock Select Switch (SW5)” on page 2-13 for more information.
Both the encoder and the decoder connect to the Parallel Peripheral Inter-faces (PPI input clock) of the ADSP-BF561 processor. For additional information on the video interface hardware, refer to “PPI Interfaces” on page 2-6.
For the video interface to be operational, the following basic steps must be performed.
1. Configure the SW2 DIP switch as required by the application. Refer to “Video Configuration Switch (SW2)” on page 2-10 for details.
2. De-assert the video device’s reset by setting a corresponding pro-grammable flag “High”. Note that PF14 controls the ADV7179 encoder’s reset, while PF13 controls the ADV7183A decoder’s reset.
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Example Programs
3. If using the decoder:
Enable device by driving programmable flag output PF2 to “0”.Select PPI0 clock; for details, refer to “PPI Clock Select Switch (SW5)” on page 2-13.
4. Program internal registers of the video device in use. Both video encoder and decoder use a 2-wire serial interface to access internal registers. The PF0 programmable flag functions as a serial clock (SCL), and PF1 functions as a serial data (SDAT).
5. Program the ADSP-BF561 processor’s PPI interfaces (configura-tion registers, DMA, and so on).
Example programs are included in the EZ-KIT installation direc-tory to demonstrate the capabilities of the video interface.
Example ProgramsExample programs are provided with the ADSP-BF561 EZ-KIT Lite to demonstrate various capabilities of the evaluation board. These programs are installed with the EZ-KIT Lite software and can be found in the \…\Blackfin\EZ-KITs\ADSP-BF561\Examples subdirectory of the Visu-alDSP++ installation directory. Please refer to the readme file provided with each example for more information.
Flash Programmer UtilityThe ADSP-BF561 EZ-KIT Lite evaluation system includes a Flash Pro-grammer utility. The utility allows you to program the flash memory on the EZ-KIT Lite. The Flash Programmer is installed with VisualDSP++. Once the utility is installed, it is accessible from the Tools pull-down menu.
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The Flash Programmer driver is core-specific (core A) and must be loaded to the core A in order to operate correctly. The Flash Programmer relies on the user to set the correct core focus. To set up the correct core, select the core A in the multiprocessor window before opening the Flash Pro-grammer interface.
For more information on the Flash Programmer utility, refer to the online Help.
Background Telemetry ChannelThe ADSP-BF561 USB debug agent supports the Background Telemetry Channel (BTC), which facilitates data exchange between VisualDSP++ and the processor without interrupting processor execution.
The BTC allows to view a variable as it is updated or changed, all while the processor continues to execute. For increased performance of the BTC, including faster reading and writing, please check out our latest line of processor emulators at www.analog.com/Analog_Root/productPage/productHome/0,2121,EMULA-
TORS,00.html. For more information about the Background Telemetry Channel, see the VisualDSP++ User’s Guide or online Help.
VisualDSP++ InterfaceThis section provides information on the following parts of the Visu-alDSP++ graphical user interface:
• “Target Options” on page 1-14
• “Restricted Software Breakpoints” on page 1-17
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VisualDSP++ Interface
Target OptionsChoosing Target Options from the Settings menu opens the Target Options dialog box (Figure 1-3). Use target options to control certain aspects of the processor on the ADSP-BF561 EZ-KIT Lite evaluation system.
Reset Options
Reset options control how the processor behaves when a reset occurs. The reset options are described in Table 1-4.
On Emulator Exit
This target option controls processor behavior when VisualDSP++ relin-quishes processor control (for example, when exiting VisualDSP++). The option is described in Table 1-5.
Figure 1-3. Target Options Dialog Box
Table 1-4. Reset Options
Option Description
Core reset Resets the core when the debugger executes a reset. Note that a core reset of either core effects both cores as does a system reset.
System reset Resets the peripherals when the debugger executes a reset.
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XML File
These read-only fields show the version information for the processor-spe-cific XML file, in the \…\SYSTEM\ADSP-BF561.xml subdirectory of the VisualDSP++ installation directory, as well as the parser program (Table 1-6).
Other Options
Table 1-7 describes other available target options.
Table 1-5. On Emulator Exit Target Options
Option Description
On Emulator Exit Determines the state the processor is left in when the board relinquishes control of the processor:Reset DSP and Run causes the processor to reset and begin execution from its reset vector location.Run from current PC causes the processor to begin running from its current location. Stall the DSP resets the processor and then writes a JUMP 0 to the first loca-tion in internal memory so the processor is stuck in a tight loop after exit-ing.
Table 1-6. XML File Information
Option Description
XML File Version The version of the processor’s XML file.
XML Parser Version The version of the program that parses the XML file.
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VisualDSP++ Interface
Table 1-7. Miscellaneous Target Options
Option Description
Verify all writes to target memory
Validates all memory writes to the processor. After each write, a read is performed and the values are checked for a matching condition.Enable this option during initial program development to locate and fix initial build problems (such as attempting to load data into non-existent memory). Clear this option to increase performance while loading executable files, since VisualDSP++ does not perform the extra reads that are required to verify each write.
Reset cycle counters on run
Resets the cycle count registers to zero before a Run command is issued. Select this option to count the number of cycles executed between breakpoints in a program.
Use opcode scan method Enables the debugger to use a highly optimized JTAG scan method. This provides extremely fast communication between the EZ-KIT Lite and the processor. In certain circumstances, this causes JTAG scan failures. Typically, JTAG scan failures occur when using this method combined with debugging situations that hold off or stall the core (such as debugging, loading, or viewing external memory). Clearing this option uses a less optimized JTAG scan method.
Use XML reset values Uses a section in the processor-specific .XML file located in the installation’s system folder. The file defines registers that are reset to certain values; the values are read at startup and subsequently used to set the registers when a reset is performed through Visu-alDSP++. Applies to both processors.
Mask interrupts during step
Disables interrupts while single stepping through code. Applies to both processors.
Disable breakpoints in shared memory messages
Suppress a warning message caused by setting a breakpoint in shared memory. Applies to both processors.
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Restricted Software BreakpointsThe EZ-KIT Lite development system restricts breakpoint placement when certain conditions are met. That is, under some conditions, break-points cannot be placed effectively. Such conditions depend on bus architecture, pipeline depth, and ordering of the EZ-KIT Lite and its tar-get processor.
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VisualDSP++ Interface
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2 EZ-KIT LITE HARDWARE REFERENCE
This chapter describes the hardware design of the ADSP-BF561 EZ-KIT
Lite board. The following topics are covered.• “System Architecture” on page 2-2Describes the configuration of the ADSP-BF561EZ-KIT Lite and explains how the board components interface with the processor.
• “Jumper and DIP Switch Settings” on page 2-10Shows the location and describes the function of the configuration jumpers and switches.
• “LEDs and Push Buttons” on page 2-14Shows the location and describes the function of the LEDs and push buttons.
• “Connectors” on page 2-17Shows the location and gives the part number for all of the connec-tors on the board. Also, the manufacturer and part number information is given for the mating parts.
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System Architecture
System ArchitectureThis section describes the processor’s configuration on the EZ-KIT Lite board.
The EZ-KIT Lite has been designed to demonstrate the capabilities of the ADSP-BF561 Blackfin processor. The processor has IO voltage of 3.3V. The core voltage and the core clock rate can be set on the fly by the pro-cessor. The input clock is 30 MHz.
Figure 2-1. System Architecture
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EZ-KIT Lite Hardware Reference
External Bus Interface UnitThe External Bus Interface Unit (EBIU) connects an external memory to the ADSP-BF561 processor. It includes a 32-bit wide data bus, an address bus (A25–A2), and a control bus. All 8-bit, 16-bit, and 32-bit accesses are supported. On the EZ-KIT Lite board, the EBI unit is connected to SDRAM and flash memory. For more information on using the external memory see “External Memory” on page 1-6.
All of the address, data, and control signals are available externally via the extender connectors (J3–J1). The pinout of these connectors can be found in Appendix B, “Schematics” on page B-1.
SPORT0 Audio InterfaceThe SPORT0 interface connects to the AD1836A audio codec, the SPORT connector (P3), and the expansion interface. The AD1836A codec uses both the primary and secondary data transmit and receive pins to input and output data from the audio input and outputs.
The pinout of the SPORT connector and the expansion interface connec-tors can be found in Appendix B, “Schematics” on page B-1.
SPI InterfaceThe processor’s Serial Peripheral Interconnect (SPI) interface connects to the AD1836A audio codec and the expansion interface. The SPI connec-tion to the AD1836A is used to access the control registers of the device. The PF4 flag of the processor acts as the devices select for the SPI port.
The SPI signals are available on the expansion interface. The pinout for the expansion interface can be found in Appendix B, “Schematics” on page B-1.
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System Architecture
Programmable Flags
The processor has 48 programmable flag pins (PFs). Many of the flags have a multiple functionality, depending on the processor’s setup. Table 2-1 shows how the programmable flag pins are used on the EZ-KIT Lite.
Table 2-1. Programmable Flag Connections
Processor PF Pin
Processor Function EZ-KIT Function
PF0 SPI Select S, Timer 0 Serial clock for programming ADV7179 video encoder and ADV7183A video decoder.
PF1 SPI Select 1, Timer 1 Serial data for programming ADV7179 video encoder and ADV7183A video decoder.
PF2 SPI Select 2, Timer 2 ADV7183A video decoder’s ~OE.
PF3 SPI Select 3, Timer 3 ADV7183A Field pin. See “Video Configuration Switch (SW2)” on page 2-10.
PF4 SPI Select 4, Timer 4 AD1836A audio codec’s SPI Select.
PF5 SPI Select 5, Timer 5 Push Button (SW6). See “LEDs and Push Buttons” on page 1-9 and “Push Button Enable Switch (SW4)” on page 2-12 for information on how to disable the push button.
PF6 SPI Select 6, Timer 6 Push Button (SW7). See “LEDs and Push Buttons” on page 1-9 and “Push Button Enable Switch (SW4)” on page 2-12 for information on how to disable the push button.
PF7 SPI Select 7, Timer 7 Push Button (SW8). See “LEDs and Push Buttons” on page 1-9 and “Push Button Enable Switch (SW4)” on page 2-12 for information on how to disable the push button.
PF8 Push Button (SW9). See “LEDs and Push Buttons” on page 1-9 and “Push Button Enable Switch (SW4)” on page 2-12 for information on how to disable the push button.
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PF9–PF12 Not used
PF13 ADV7183A video decoder’s reset
PF14 ADV7179 video encoder’s reset
PF15 AD1836 codec’s reset
PF16 Sport 0 Transmit Frame Sync
PF17 Sport 0 Transmit Data Secondary
PF18 Sport 0 Transmit Data Primary
PF19 Sport 0 Receive Frame Sync
PF20 Sport 0 Receive Data Secondary
PF21 Sport 1 Transmit Frame
PF22 Sport 1 Transmit Data Secondary
PF23 Sport 1 Transmit Data Primary
PF24 Sport 1 Receive Frame Sync
PF25 Sport 1 Receive Data Secondary
PF26 UART Transmit
PF27 UART Receive
PF28 Sport 0 Receive Serial Clock
PF29 Sport 0 Transmit Serial Clock
PF30 Sport 1 Receive Serial Clock
PF31 Sport 1 Transmit Serial Clock
PF39–32 PPI1 data 15–8 LED20–13
PF47–40 PPI0 data 15–8 LED12–5
Table 2-1. Programmable Flag Connections (Cont’d)
Processor PF Pin
Processor Function EZ-KIT Function
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System Architecture
PPI InterfacesThe ADSP-BF561 processor employs two independent Parallel Peripheral Interfaces (PPIs), PPI0 and PPI1. Each PPI interface is a half-duplex, bi-directional bus consisting of 16 bits of data, a dedicated input clock, and synchronization signals. The ADSP-BF561 EZ-KIT Lite board uti-lizes the PPI interfaces for video input and video output.
The PPI0 interface is configured to input video data from the ADV7183A video decoder device: bits 7–0 connect to the video decoder’s data outputs. The PPI1 interface is configured to output video data to the ADV7179 video encoder device: bits 7–0 connect to the video encoder’s data inputs.
Each PPI interface has a dedicated clock input configured independently by the SW5 switch. The clock source can be one of the following: 27 MHz crystal oscillator, ADV7183A video decoder’s clock output, or external clock from the expansion interface. See “PPI Clock Select Switch (SW5)” on page 2-13 for more information about the switch.
The SW2 switch allows flexible connectivity between dedicated synchroni-zation IOs (SYNC1 and SYNC2 of each PPI interface) and the encoder’s and decoder’s horizontal and vertical synchronization pins. See “Video Con-figuration Switch (SW2)” on page 2-10 for more information about the switch. For a detailed description of the ADSP-BF561 processor’s PPI interfaces, refer to the ADSP-BF561 Blackfin Processor Hardware Reference.
Table 2-2 describes the PPI pins and their use on the EZ-KIT Lite board.
Table 2-2. PPI Connections
Processor PPI Pin
Other PRocessor Function
EZ-KIT Function
PPI0 bits 7–0 ADV7183A data outputs P15–8
PPI1 bits 7–0 ADV7179 data inputs P7–0
PPI0 SYNC1 Timer 8 ADV7179 HSYNC. For more information, see “Video Configuration Switch (SW2)” on page 2-10.
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Video Output (PPI1)
The PPI1 interface is configured as output and connects to the on-board video encoder device, ADV7179. The ADV7179 encoder generates three analog video channels on DAC A, DAC B, and DAC C. The PPI1 bits 7–0 con-nect to P7–0 of the encoder’s pixel inputs. The encoder’s input clock is fixed and comes from an on-board 27 MHz oscillator.
The encoder’s synchronization signals, HSYNC and VSYNC, can be config-ured as inputs or outputs. Video Blanking control signal is at level “1”. The HSYNC and VSYNC signals can connect to the ADSP-BF561 processor’s PPI1 interface SYNC1 and SYNC2 via the SW2 switch, as described in “Video Configuration Switch (SW2)” on page 2-10.
PPI0 SYNC2 Timer 9 ADV7179 VSYNC. For more information, see “Video Configuration Switch (SW2)” on page 2-10.
PPI0 Clock A choice of ADV7183A output clock, a local 27 MHz oscillator, or an external clock from ADSP-BF533/BF561 EZ-KIT Extender 1 board.
PPI1 SYNC1 Timer 10 ADV7183A HSYNC. For more information, see “Video Configuration Switch (SW2)” on page 2-10.
PPI1 SYNC2 Timer 11 ADV7183A VSYNC. For more information, see “Video Configuration Switch (SW2)” on page 2-10.
PPI1 Clock A choice of ADV7183A output clock, a local 27 MHz oscillator, or an external clock from ADSP-BF53x/BF561 EZ-Extender 1.
Table 2-2. PPI Connections (Cont’d)
Processor PPI Pin
Other PRocessor Function
EZ-KIT Function
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System Architecture
Video Input (PPI0)
The PPI0 interface is configured as input and connect to the on-board video decoder device, ADV7183A. The ADV7183A decoder receives three analog video channels on AIN1, AIN4, and AIN5 input. The decoder’s pixel data outputs P15–8 drive the PPI0 inputs 8–0. The decoder’s 27 MHz pixel clock output can be selected to drive any of the PPI clocks, as shown in Table 2-7 on page 2-13.
Synchronization outputs of the decoder, HS/HACTIVE, VS/VACTIVE, and FIELD can connect to the processor’s PPI1 SYNC1, SYNC2, and PF3 flag via the SW2 DIP switch, as described in “Video Configuration Switch (SW2)” on page 2-10.
UART PortThe processor’s Universal Asynchronous Receiver/Transmitter (UART) port connects to the ADM3202 RS232 line driver as well as to the expan-sion interface. The RS232 line driver is attached to the DB9 male connector, allowing you to interface with a PC or other serial device.
Expansion InterfaceThe expansion interface consists of the three 90-pin connectors, J3–1. Table 2-3 shows the interfaces each connector provides. For the exact pinout of these connectors, refer to Appendix B, “Schematics” on page B-1. The mechanical dimensions of the connectors can be obtained from Technical or Customer Support.
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Limits to the current and to the interface speed must be taken into consid-eration when you use the expansion interface. The maximum current limit is dependent on the capabilities of the used regulator. Additional circuitry can also add extra loading to signals, decreasing their maximum effective speed.
Analog Devices does not support and is not responsible for the effects of additional circuitry.
JTAG Emulation PortThe JTAG emulation port allows an emulator to access the processor’s internal and external memory through a 6-pin interface. The JTAG emu-lation port of the processor also connects to the USB debugging interface. When an emulator connects to the board at P4, the USB debugging inter-face is disabled. See “JTAG (P4)” on page 2-20 for more information about the JTAG connector.
To learn more about available emulators, contact Analog Devices (see “Product Information”).
Table 2-3. Connector Interfaces
Connector Interfaces
J1 5V, G ND, Address, Data, PPI0 3–0, PF15–6, PF4
J2 3.3V, GND, SPI, NMI, PPI0 SYNC3–1, SPORT0, SPORT1, PF15–0, EBUI control signals
J3 5V, 3.3V, GND, UART, PPI1 15–0, Reset, Video control signals
ADSP-BF561 EZ-KIT Lite Evaluation System Manual 2-9
Jumper and DIP Switch Settings
Jumper and DIP Switch SettingsThis section describes the operation of the jumpers and DIP switches. The jumper and DIP switch locations are shown in Figure 2-2.
Video Configuration Switch (SW2)The video configuration switch (SW2) controls how some video signals from the ADV7183A video decoder and ADV7179 video encoder are routed to the processor’s PPIs. The switch also determines if the PF2 pin controls the ~OE signal of the ADV7183A video decoder outputs. Table 2-4 shows which processor’s signals are connected to the encoder and decoder when in the “ON” position.
Figure 2-2. DIP Switch Locations
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Positions 1 thorough 5 of SW2 determine how and if the SYNC1, SYNC2, and FIELD control signals of the PPI0 and PPI1 interfaces are routed to the pro-cessor’s PPIs. In standard configuration of the encoder and decoder, this is not necessary because the processor is capable of reading the embedded control information, which is in the data stream.
Position 6 of SW2 determines whether PF2 connects to the ~OE signal of the ADV7183A. When the switch is “OFF”, PF2 can be used for other opera-tions, and the decoder output enable is held “HIGH” with a pull-up resistor.
Boot Mode Switch (SW3)The SW3 switch positions 1 and 2 set the ADSP-BF561 processor’s boot mode as described in Table 2-5. Position 3 sets the processor’s PLL on boot. When SW3 position 3 is “ON”, the PLL is in bypass.
Table 2-4. Video Configuration Switch (SW2)
Switch Position (Default) Processor Signal Video Signal
1 (OFF) PPI1 SYNC1 ADV7179
2 (OFF) PPI0 SYNC1 ADV7183A
3 (OFF) PPI1 SYNC2 ADV7183A
4 (OFF) PPI1 SYNC2 ADV7179
5 (OFF) PF3 (FIELD) ADV7183A
6 (ON) PF2 ADV7183A
Table 2-5. Boot Mode Select Switch (SW3)
Position 1 BMODE0 Position 2 BMODE1 Boot Mode
ON ON Reserved
ON OFF Flash memory
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Jumper and DIP Switch Settings
Push Button Enable Switch (SW4)The push button enable switch (SW4) positions 1 through 4 allow to dis-connect the drivers associated with the push buttons from the PF pins of the processor. Positions 5 and 6 connect the transmit and receive frame syncs and clocks of SPORT0. This is important when the AD1836A video decoder and the processor are communicating in Two-Wire Interface (TWI) mode. Table 2-6 shows which PF is driven when the switch is in the “ON” position.
OFF ON 8-bit SPI PROM
OFF OFF 16-bit SPI PROM
Table 2-6. Push Button Enable Switch (SW4)
Switch Position Default Setting Pin # Signal (Side 1) Pin # Signal (Side 2)
1 ON 1 SW6 12 PF5
2 ON 2 SW7 11 PF6
3 ON 3 SW8 10 PF7
4 ON 4 SW9 9 PF8
5 OFF 5 TFS0 8 RFS0
6 OFF 6 RSCLK0 7 TSCLK0
Table 2-5. Boot Mode Select Switch (SW3) (Cont’d)
Position 1 BMODE0 Position 2 BMODE1 Boot Mode
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PPI Clock Select Switch (SW5)The SW5 switch controls a clock selection of PPI interfaces, as described in Table 2-7 and Table 2-8.
Test DIP Switches (SW10 and SW11)Two DIP switches (SW10 and SW11) are located on the bottom of the board. The switches are used only for testing and should be in the “OFF” position.
Table 2-7. PPICLK1 Clock Source Setup
SW5 Position 1 PPI0_CKSEL0
SW5 Position 2 PPI0_CKSEL1
PPICLK1 Source
ON ON 27 MHz Oscillator (default)
OFF ON ADV7183 Clock Out
X OFF Expansion Interface
Table 2-8. PPICLK2 Clock Source Setup
SW5 Position 3 PPI1_CKSEL0
SW5 Position 4 PPI1_CKSEL1
PPICLK2 Source
ON ON 27 MHz Oscillator (default)
OFF ON ADV7183 Clock Out
X OFF Expansion Interface
ADSP-BF561 EZ-KIT Lite Evaluation System Manual 2-13
LEDs and Push Buttons
LEDs and Push ButtonsThis section describes the functionality of the LEDs and push buttons. Figure 2-3 shows the locations of the LEDs and push buttons on the board.
Reset Push Button (SW1)The RESET push button resets all of the ICs on the board. One exception is the USB interface chip (U34). The chip is not being reset when the push button is pressed after the USB cable has been plugged in and communi-cation with the PC has been initialized correctly. Once communication is initialized, the only way to reset the USB is by powering down the board.
Figure 2-3. LED and Push Button Locations
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EZ-KIT Lite Hardware Reference
Programmable Flag Push Buttons (SW9–6)Four push buttons, SW9–6, are provided for general-purpose user input. The buttons connect to the processor’s programmable flag pins PF8–5. The push buttons are active “HIGH” and, when pressed, send a High (1) to the processor. Refer to “LEDs and Push Buttons” on page 1-9 for more information on how to use the PFs when programming the processor. The push button enable switch (SW4) is capable of disconnecting the push but-tons from the PF (refer to “Push Button Enable Switch (SW4)” on page 2-12). The programmable flag signals and their corresponding switches are shown in Table 2-9.
Power LED (J7)When J7 is lit (green), it indicates that power is being properly supplied to the board.
Reset LEDs (LED2 and LED3)When LED2 is lit, it indicates that the master reset of all the major ICs is active. When LED3 is lit, the USB interface chip (U34) is being reset. The USB chips only reset on power-up, or if USB communication has not been initialized.
Table 2-9. Programmable Flag Switches
Processor Programmable Flag Pin Push Button Reference Designator
PF5 SW6
PF6 SW7
PF7 SW8
PF8 SW9
ADSP-BF561 EZ-KIT Lite Evaluation System Manual 2-15
LEDs and Push Buttons
USB Monitor LED (LED4)The USB monitor LED (LED4) indicates that USB communication has been initialized successfully and you may connect to the processor using a VisualDSP++ EZ-KIT Lite session. This should take approximately 15 seconds. If the LED does not light, try cycling power on the board and/or reinstalling the USB driver.
When VisualDSP++ is actively communicating with the EZ-KIT Lite target board, the LED can flicker, indicating communications handshake.
User LEDs (LED12–5, LED20–13)Sixteen LEDs are connected to the ADSP-BF561 processor’s programma-ble flags. Eight LEDs labeled LED5 through LED12 are controlled by programmable flags PF40 through PF47 (equivalent to PPI0 D15–8). Eight LEDs labeled LED13 through LED20 are controlled by programmable flags PF32 through PF39 (equivalent to PPI1 D15–8). To learn how to use the flash memory when programming the LEDs, refer to “LEDs and Push Buttons” on page 1-9.
Table 2-10. User LEDs
LED Reference Designator Flash Port Name LED Reference Designator Flash Port Name
LED5 PB40 LED13 PB32
LED6 PB41 LED14 PB33
LED7 PB42 LED15 PB34
LED8 PB43 LED16 PB35
LED9 PB44 LED17 PB36
LED10 PB45 LED18 PB37
LED11 PB46 LED19 PB38
LED12 PB47 LED20 PB39
2-16 ADSP-BF561 EZ-KIT Lite Evaluation System Manual
EZ-KIT Lite Hardware Reference
ConnectorsThis section describes the connector functionality and provides informa-tion about mating connectors. The locations of the connectors are shown in Figure 2-4.
Expansion Interface (J3–1)Three board-to-board connector footprints provide signals for most of the processor’s peripheral interfaces. The connectors are located at the bottom of the board. For more information about the expansion interface, see on page 2-8. For the availability and pricing of the J1, J2, and J3 connec-tors, contact Samtec.
Figure 2-4. Connector Locations
ADSP-BF561 EZ-KIT Lite Evaluation System Manual 2-17
Connectors
Audio (J4 and J5)
Video (J6)
Power (J7)The power connector provides all of the power necessary to operate the EZ-KIT Lite board. The power connector supplies DC power to the board. The following table shows the power connector pinout.
Part Description Manufacturer Part Number
90 Position 0.05" Spacing, SMT (J1, J2, J3)
Samtec SFC-145-T2-F-D-A
Mating Connector
90 Position 0.05” Spacing (Through Hole)
Samtec TFM-145-x1 Series
90 Position 0.05” Spacing (Surface Mount)
Samtec TFM-145-x2 Series
90 Position 0.05” Spacing (Low Cost)
Samtec TFC-145 Series
Part Description Manufacturer Part Number
2x2 RCA Jacks (J4) SWITCHCRAFT PJRAS2X2S01
3x2 RCA Jacks (J5) SWITCHCRAFT PJRAS3X2S01
Mating Connector
Two channel RCA interconnect cable Monster Cable BI100-1M
Part Description Manufacturer Part Number
3x2 RCA Jacks (J6) SWITCHCRAFT PJRAS3X2S01
2-18 ADSP-BF561 EZ-KIT Lite Evaluation System Manual
EZ-KIT Lite Hardware Reference
The power connector supplies DC power to the EZ-KIT Lite board. Table 2-11 shows the power supply specifications.
USB (J8)The USB connector is a standard Type B USB receptacle.
Part Description Manufacturer Part Number
2.5 mm Power Jack (J7) SWITCHCRAFT RAPC712
Digi-Key SC1152-ND
Mating Power Supply (shipped with EZ-KIT Lite)
7.5V Power Supply GlobTek TR9CC2000LCP-Y
Table 2-11. Power Supply Specification
Terminal Connection
Center pin +7.5 VDC@3Amps
Outer Ring GND
Part Description Manufacturer Part Number
Type B USB receptacle (J8) Mill-Max 897-30-004-90-000
Digi-Key ED90003-ND
Mating Assembly
USB cable (provided with kit) Assmann AK672-5
Digi-Key AK672-5ND
ADSP-BF561 EZ-KIT Lite Evaluation System Manual 2-19
Connectors
RS232 (P2)The RS232-compatible connector is described in Table 2-12.
SPORT0 (P3)The SPORT0 connector is linked to a 20-pin connector. The connector’s pinout can be found in “Schematics” on page B-1. For pricing and avail-ability of the connectors, contact AMP.
JTAG (P4)The JTAG header is the connecting point for a JTAG in-circuit emulator
Table 2-12. RS232 Connector
Part Description Manufacturer Part Number
DB9, Male, Right Angle (P2) Digi-Key A2096-ND
Mating Assembly
2m Female to Female cable Digi-Key AE1016-ND
Part Description Manufacturer Part Number
20-position AMPMODU system 50 receptacle (P3)
AMP 104069-1
Mating Connectors
20-position ribbon cable connector AMP 111196-4
20-position AMPMODU system 20 connector
AMP 2-487937-0
20-position AMPMODU system 20 connector (w/o lock)
AMP 2-487938-0
Flexible film contacts (20 per con-nector)
AMP 487547-1
2-20 ADSP-BF561 EZ-KIT Lite Evaluation System Manual
EZ-KIT Lite Hardware Reference
pod. When an emulator is connected to the JTAG header, the USB debug interface is disabled.
Pin 3 is missing to provide keying. Pin 3 in the mating connector should have a plug.
When using an emulator with the EZ-KIT Lite board, follow the connection instructions provided with the emulator.
ADSP-BF561 EZ-KIT Lite Evaluation System Manual 2-21
Connectors
2-22 ADSP-BF561 EZ-KIT Lite Evaluation System Manual
A BILL OF MATERIALS
The bill of materials corresponds to the board schematics on page B-1.
Please check the latest schematics on the Analog Devices website, http://www.analog.com/Processors/Processors/DevelopmentTools/technicalLibrary/manuals/DevToolsIndex.html#Evalua-
tion%20Kit%20Manuals.
ADSP-BF561 EZ-KIT Lite Evaluation System Manual A-1
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A-2 ADSP-BF561 EZ-KIT Lite Evaluation System Manual
Bill Of Materials
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ADSP-BF561 EZ-KIT Lite Evaluation System Manual A-3
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A-4 ADSP-BF561 EZ-KIT Lite Evaluation System Manual
Bill Of Materials
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ADSP-BF561 EZ-KIT Lite Evaluation System Manual A-5
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A-6 ADSP-BF561 EZ-KIT Lite Evaluation System Manual
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ADSP-BF561 EZ-KIT Lite Evaluation System Manual A-7
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W 1
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206
R88
-89
AVX
CR
32-2
211F
-T
6610
0pF
100V
5%
120
6
NP
O
C
6-11
,C26
,C34
, C61
-63,
C72
AVX
1206
1A10
1JA
T2A
6710
uF 1
6V 1
0% B
TA
NT
C
T1-
4,C
T15
-16
AVX
TA
JB10
6K01
6R
6810
0 10
0MW
5%
805
R24
2-24
5AV
XC
R21
-101
J-T
Ref
.# D
escr
ipti
on R
efer
ence
Des
igna
tor
Man
ufac
ture
r P
art
Num
ber
A-8 ADSP-BF561 EZ-KIT Lite Evaluation System Manual
Bill Of Materials
6922
0pf 5
0V 1
0% 1
206
N
PO
C13
-18
AVX
1206
1A22
1JA
T2A
7060
0 10
0MH
Z 2
00M
A 6
03
0.
50 B
EA
D
FE
R18
-21
MU
RA
TA
BL
M11
A60
1SP
T
712A
S2A
_RE
CT
DO
-214
AA
SIL
ICO
N R
EC
TIF
IER
D
2-3,
D7
GE
NE
RA
LSE
MI
S2A
7260
0 10
0MH
Z 5
00M
A 1
206
0.
70 B
EA
D
FE
R2-
4,FE
R6-
12,F
ER
14-1
6D
IGI-
KE
Y24
0-10
19-1
-ND
7323
7 1/
8W 1
% 1
206
R
25-2
6,R
53-5
4AV
XC
R32
-237
0F-T
7475
0K 1
/8W
1%
120
6
R13
2,R
156,
R16
4,R
173
DA
LE
/VIS
HA
YC
RC
W12
0675
03FR
T1
755.
76K
1/8
W 1
% 1
206
R
8,R
15-1
6,R
40, R
49-5
0,R
58,
PHY
CO
MP
9C12
063A
5761
FKH
FT
7611
.0K
1/8
W 1
% 1
206
R
144-
149
DA
LE
CR
CW
1206
1102
FRT
1
7712
0PF
50V
5%
120
6
N
PO
C
103,
C10
5,C
128,
C
130,
C14
2,C
144,
C16
1,C
163
PHIL
LIP
S12
06C
G12
1J9B
200
7875
1/8
W 5
% 1
206
R4-
6,R
100-
102,
R10
4-10
5,R
107
,R11
4, R
134-
135
PHIL
IPS
9C12
063A
75R
0JL
HFT
7930
PF
100V
5%
120
6
C22
1-22
2AV
X12
061A
300J
AT
2A
8068
UF
6.3V
20%
D
TA
NT
C
T22
PAN
ASO
NIC
EC
S-T
OJD
686R
Ref
.# D
escr
ipti
on R
efer
ence
Des
igna
tor
Man
ufac
ture
r P
art
Num
ber
ADSP-BF561 EZ-KIT Lite Evaluation System Manual A-9
8134
0K 1
/8W
1%
805
R21
1D
AL
EC
RC
W08
05-3
403F
T
8269
8K 1
/8W
1%
805
R21
0D
AL
EC
RC
W08
05-6
983F
T
8368
0PF
50V
1%
805
NP
O
C11
6-12
1AV
X08
055A
681F
AT
2A
8410
UF
25V
+80
-20%
121
0
Y5V
C31
,C47
,C50
MU
RA
TA
GR
M23
5Y.5
V10
6Z02
5
852.
74K
1/8
W 1
% 1
206
R
150-
155
DA
LE
CR
CW
1206
2741
FRT
1
865.
49K
1/8
W 1
% 1
206
R
17-2
2,R
27,R
30-3
1,
R34
-35,
R38
PAN
ASO
NIC
ER
J-8E
NF5
491V
873.
32K
1/8
W 1
% 1
206
R13
7-14
2D
AL
EC
RC
W12
0633
21FR
T1
881.
65K
1/8
W 1
% 1
206
R28
-29,
R32
-33,
R36
-37
PAN
ASO
NIC
ER
J-8E
NF1
651V
8910
UF
16V
20%
CA
P00
2
E
LE
C
CT
5-14
DIG
01P
CE
3062
TR
-ND
902A
SL
22 D
O-2
14A
A
SCH
OT
TK
Y
D
6G
EN
ER
AL
SE
MI
SL22
9153
.6K
1/1
0W 1
% 8
05
R
75PH
ILIP
S9C
0805
2A53
62FK
RT
/R
9233
2K 1
/10W
1%
805
R20
7PH
ILIP
S9C
0805
2A33
23FK
RT
/R
9310
UH
47
+/-2
0 IN
D00
1
L
11D
IG01
445-
1202
-2-N
D
Ref
.# D
escr
ipti
on R
efer
ence
Des
igna
tor
Man
ufac
ture
r P
art
Num
ber
A-10 ADSP-BF561 EZ-KIT Lite Evaluation System Manual
Bill Of Materials
9410
K 3
1MW
5%
RN
ET
8
RN
3C
TS
746X
1011
03J
9510
K 5
0MW
5%
BG
A36
R
N2
CT
SR
T13
0B7
960.
00 1
00M
W 5
% 8
05
R
66,R
74,R
77,R
79,R
81,R
83-8
4,R
87,R
99, R
103,
R10
6,R
178,
R19
2, R
252
VIS
HA
YC
RC
W08
05 0
.0 R
T1
9719
0 10
0MH
Z 5
A F
ER
002
FE
R5
MU
RA
TA
DLW
5BSN
191S
Q2
983.
32K
100
MW
1%
805
R19
4-19
5, R
227
DIG
01P
3.32
KC
CT
R-N
D
9922
1/1
0W 5
% 8
05
R67
-68,
R18
7-18
8, R
204,
R22
6V
ISH
AY
/DA
LE
CR
CW
0805
220J
RT
1
100
0.68
UH
0.7
2 10
% 8
05
L1-
4,L
6,L
8M
UR
AT
AL
QG
21N
R68
K10
T1
101
82N
F 50
V 5
% 8
05
X7R
C
64AV
X08
055C
823J
AT
2A
102
1A Z
HC
S100
0 SO
T23
D
SCH
OT
TK
Y
D
5Z
ET
EX
ZH
CS1
000
103
2.2U
H 0
.63
10%
805
L
5,L
7,L
9M
UR
AT
ALQ
G21
N2R
2K10
104
0.47
UF
16V
10%
805
C
218,
C23
0AV
X08
05Y
C47
4KA
T2A
105
1UF
10V
10%
805
C
21,C
24,C
32,C
44-4
5AV
X08
05Z
C10
5KA
T2A
106
10U
F 6.
3V 1
0% 8
05
C20
8,C
217,
C21
9, C
243,
C25
5AV
X08
0560
106K
AT
2A
Ref
.# D
escr
ipti
on R
efer
ence
Des
igna
tor
Man
ufac
ture
r P
art
Num
ber
ADSP-BF561 EZ-KIT Lite Evaluation System Manual A-11
107
4.7U
F 6.
3V 1
0% 8
05
C16
9AV
X08
056D
475K
AT
2A
108
0.1U
F 10
V 1
0% 4
02
C
192-
199,
C20
6,
C20
9-21
3,C
215,
C
220,
C22
4-22
6, C
234-
235,
C
237-
238,
C24
2,
C24
4-24
5,C
248,
C25
0,C
253,
C
258-
259
AVX
0402
ZD
104K
AT
2A
109
0.01
UF
16V
10%
402
C20
4-20
5,C
207,
C21
4,C
216,
C22
3,C
227-
229,
C23
1-23
2,C
239
-240
, C
246-
247,
C25
1-25
2,C
254,
C2
57
AVX
0402
YC
103K
AT
2A
110
1.5U
H 4
5MO
HM
20%
IND
003
2.8A
L10
TY
CO
DS6
630-
1R5M
111
100M
A C
MD
SH-3
SO
D-3
23
SU
PER
MIN
I SC
HO
TT
KY
D
4C
EN
TR
AL
SE
MI
CM
DSH
-3
112
0.18
uF 2
5V 1
0% 8
05
CE
RM
C
170
AVX
0805
3C18
4KA
T2A
113
100u
F 10
V 1
0% C
TA
NT
-LO
W-E
SR
CT
19AV
XT
PSC
107K
010R
0075
114
2.2u
F 10
V 1
0% 8
05
CE
RM
C
43AV
X08
05Z
D22
5KA
T2A
115
76.8
K 1
00M
W 1
% 1
206
R
48
DA
LE
CR
CW
1206
-768
2FR
T1
Ref
.# D
escr
ipti
on R
efer
ence
Des
igna
tor
Man
ufac
ture
r P
art
Num
ber
A-12 ADSP-BF561 EZ-KIT Lite Evaluation System Manual
Bill Of Materials
116
147K
100
MW
1%
120
6
R
56
DA
LE
CR
CW
1206
-147
3FR
T1
117
10 6
2.5M
W/R
5%
RA
8/38
V
RE
SIST
OR
AR
RA
Y
R
N1,
RN
4-12
PAN
ASO
NIC
EX
B-3
8V10
0JV
118
17.4
K 1
/10W
1%
805
R
180
PAN
ASO
NIC
ER
J-6E
NF1
742V
119
AD
SP-B
F561
-EZ
LIT
E P
CB
AN
AL
OD
D
EV
ICE
S
120
DB
9 9P
IN D
B9M
RIG
HT
AN
GL
E M
AL
E
P2
3M78
7203
-2
121
1K 1
/8W
5%
120
6
R
10,R
95,R
115-
118,
R13
6AV
XC
R32
-102
J-T
122
100K
1/8
W 5
% 1
206
R
9,R
13,R
157
DA
LE
CR
1206
-100
3FR
T1
123
22 1
/8W
5%
120
6
R
92-9
3D
AL
EC
RC
W12
0622
0JR
T1
124
270
1/8W
5%
120
6
R
120,
R19
3,R
197,
R21
3-22
0,
R23
0-23
7AV
XC
R32
-271
J-T
125
680
1/8W
5%
120
6
R
119
AVX
CR
32-6
81J-
T
126
10.0
K 1
/8W
1%
120
6
R
186
DA
LE
CR
CW
1206
-100
2FR
T1
127
150
1/8W
1%
120
6
R3
PAN
ASO
NIC
ER
J-8E
NF1
500V
Ref
.# D
escr
ipti
on R
efer
ence
Des
igna
tor
Man
ufac
ture
r P
art
Num
ber
ADSP-BF561 EZ-KIT Lite Evaluation System Manual A-13
128
RE
D-S
MT
LE
D00
1
G
UL
L-W
ING
LE
D2-
3PA
NA
SON
ICL
N12
61C
129
GR
EE
N-S
MT
LE
D00
1
GU
LL
-WIN
G
L
ED
1PA
NA
SON
ICL
N13
61C
130
604
1/8W
1%
120
6
R
125-
130
DA
LE
CR
CW
1206
6040
FRT
1
131
1uF
25V
20%
A
T
AN
T -
55+1
25
CT
25-2
8PA
NA
SON
ICE
CS-
T1E
Y10
5R
132
AD
G77
4A Q
SOP
16
Q
UIC
KSW
ITC
H-2
57
U
36-3
7A
NA
LO
G
DE
VIC
ES
AD
G77
4AB
RQ
133
IDC
2X
1 ID
C2X
1
G
OL
D
P1
134
IDC
7X
2 ID
C7X
2
HE
AD
ER
P4
BE
RG
5410
2-T
08-0
7
135
2.5A
RE
SET
AB
LE
FU
S001
F1
RA
YC
HE
M C
OR
P.SM
D25
0-2
Ref
.# D
escr
ipti
on R
efer
ence
Des
igna
tor
Man
ufac
ture
r P
art
Num
ber
A-14 ADSP-BF561 EZ-KIT Lite Evaluation System Manual
JSZ
A0185-2003
ADSP-BF561 EZ-KIT LITE:10/10/03
1.3A
ANALOGDEVICES 4
3
2
1
A B C D
A B C D
4
3
2
1
Approvals Date
Drawn
Checked
Engineering Date
Size
Title
Board No.
Sheet ofC
PH: 1-800-ANALOGD
Nashua, NH 03063
20 Cotton Road
Rev
ADSP-BF561 EZ-KIT LiteSchematic
12-16-2003_11:50 1 18
TITLE
3.3V
3.3V
CLK2
CLK1
GND
CLK3VDD
CLK4
CLKOUTREF
3.3V
R4B
R3B
R2B
R1BR1A
R2A
R4A
R3A
R4B
R3B
R2B
R1BR1A
R2A
R4A
R3A
R4B
R3B
R2B
R1BR1A
R2A
R4A
R3A
R4B
R3B
R2B
R1BR1A
R2A
R4A
R3A
R4B
R3B
R2B
R1BR1A
R2A
R4A
R3A
R4B
R3B
R2B
R1BR1A
R2A
R4A
R3A
R4B
R3B
R2B
R1BR1A
R2A
R4A
R3A
R4B
R3B
R2B
R1BR1A
R2A
R4A
R3A
R4B
R3B
R2B
R1BR1A
R2A
R4A
R3A
OE OUT
3.3V
JSZ
A0185-2003
ADSP-BF561 EZ-KIT LITE:10/10/03
1.3A
ANALOGDEVICES 4
3
2
1
A B C D
A B C D
4
3
2
1
Approvals Date
Drawn
Checked
Engineering Date
Size
Title
Board No.
Sheet ofC
PH: 1-800-ANALOGD
Nashua, NH 03063
20 Cotton Road
Rev
ON1
23
4
A16
A23
A24
BMODE0
BMODE1
CLKIN
D0
D1
D10
D11
D12
D16
D17
D19
D2
D29
D3
D4
D5
D6
D7
D8
D9
NMI0
NMI1
SA10
SCKE
SCLK0
SCLK1
XTAL
ARDY
BYPASS
D15
D14
D13
D18
D20
D21
D22
D23
D24
D25
D26
D27
D28
D31
D30
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A17
A18
A19
A20
A21
A22
A25
BR
RESET
ABE0
ABE1
ABE2
ABE3
BG
BGH
AOE
ARE
AWE
AMS0
AMS1
AMS2
AMS3
SRAS
SCAS
SMS0
SMS1
SMS2
SMS3
SWE
SDQM0/
SDQM1/
SDQM2/
SDQM3/
OFF OFF
ON
RESERVED
8-BIT FLASH
SPI SROM 8-BIT
SPI SROM 16-BIT
ONON
OFF ON
OFF
BMODE11 2
BOOT MODEBMODE0
DEFAULT
SW3: BOOT MODE/BYPASS Select(Default = OFF, ON, ON, OFF)
A[25:2]
A14
A22
A25
A24
A23
A21
A20
A19
A18
A17
A16
A15
A12
A11
A9
A8
A7
A6
A5
A4
A2
A3
A10
A13
A25_S
A24_S
A23_S
A22_S
A21_S
A20_S
A19_S
A18_S
A17_S
A16_S
A14_S
A15_S
A2_S
A24_S
A23_S
A22_S
A21_S
A20_S
A19_S
A18_S
A17_S
A11_S
A12_S
A13_S
A14_S
A15_S
A16_S
A4_S
A5_S
A6_S
A7_S
A8_S
A9_S
A2_S
A3_S
A25_S
A10_S
A[25:2]_S
A5_S
A6_S
A7_S
A8_S
A9_S
A10_S
A11_S
A12_S
A13_S
A4_S
A3_S
1825-12-2004_16:35
DSP - EXT MEM INTERFACE
B4
D4
A2
M10
N10
F1
B16
C15
F12
F16
F14
H12
H15
H16
E12
L16
C16
E14
D15
D16
E15
F13
F15
P11
R9
D11
B10
A11
A12
G1
D9
G4
G12
G13
G15
H13
H14
J15
J13
J16
K14
K15
K13
L15
K12
M15
J12
D13
G11
B15
G10
B14
C14
F11
D7
A6
C6
B5
E6
A5
E5
F6
B3
C4
A3
F5
B2
C3
B12
F3
E11
B13
A14
A15
A13
C12
C7
B8
A8
C8
B7
E7
A7
C10
D10
E9
B9
C9
A10
E10
U48
MBGA256ADSP-BF561SKBC-600
2
3
1
4 5
6
7
8
DIP4SWT018
SW3
DSP_BYPASS
10K805
R16710K805
R17010K805
R168
BMODE0
SCLK0
SCLK0_S
BR
ABE0
SCAS_SSRAS
ABE2_S
ABE1_S
BMODE1
ABE2
DSPCK_30MHZ
ABE0_S
D[31:0]D1
D2
D3
D4
D14
D13
D12
D11
D10
D9
D8
D7
D6
D17
D18
D19
D20
D21
D22
D24
D25
D26
D27
D29
D31
D16
D5
D15
D23
D28
D0
D30
ABE1
BG
CLK_OUT_EXP2
CLK_OUT_EXP1
SCLK1
SCLK1_S
C42
8050.1UF
DNP
10K805
R17610K805
R169
NMI0NMI1
AREARDY
1 3
U14
30.0000MHZOSC003
R65
DNP
22805
ABE3ABE3_S
SMS3_S
SMS2_S
SMS1_S
SMS0_S
AMS3
AMS2
AMS1
AMS0
AWE
AOE
BGH
SA10_S
SWE_S
SRAS_S
SMS3
SMS2
SMS1
SMS0
SA10
SWE
SCAS
SCKE
RESET
5
6
7
81
2
4
3
RN8
RA8/38V10
5
6
7
81
2
4
3
RN6
RA8/38V10
5
6
7
81
2
4
3
RN12
RA8/38V10
5
6
7
81
2
4
3
RN9
RA8/38V10
5
6
7
81
2
4
3
RN10
RA8/38V10
5
6
7
81
2
4
3
RN11
RA8/38V10
5
6
7
81
2
4
3
RN7
RA8/38V10
5
6
7
81
2
4
3
RN5
RA8/38V10
5
6
7
81
2
4
3
RN4
RA8/38V10
1
2
3
4
56
7
8
U20
SOIC8IDT2305-1DC
80522R188
80522R187
R6033805
80522R67
R6822805
80510KR42
R196
80510K
R160
80510K
OSC_30MHZ
805DNPR51
EXT_DSP_CLK
R4B
R3B
R2B
R1BR1A
R2A
R4A
R3A
3.3V
JSZ
A0185-2003
ADSP-BF561 EZ-KIT LITE:10/10/03
1.3A
ANALOGDEVICES 4
3
2
1
A B C D
A B C D
4
3
2
1
Approvals Date
Drawn
Checked
Engineering Date
Size
Title
Board No.
Sheet ofC
PH: 1-800-ANALOGD
Nashua, NH 03063
20 Cotton Road
Rev
GND1
GND10GND11GND12GND13GND14GND15GND16GND17GND18GND19
GND2
GND20GND21 GND22
GND23GND24GND25GND26GND27GND28GND29
GND3
GND30GND31GND32GND33GND34GND35GND36GND37GND38GND39GND4GND40GND41
GND5GND6GND7GND8GND9
NC0NC1
VDDEXT1
VDDEXT10VDDEXT11VDDEXT12VDDEXT13VDDEXT14VDDEXT15VDDEXT16VDDEXT17VDDEXT18VDDEXT19
VDDEXT2
VDDEXT20VDDEXT21VDDEXT22VDDEXT23
VDDEXT3VDDEXT4VDDEXT5VDDEXT6VDDEXT7VDDEXT8VDDEXT9
VDDINT1
VDDINT10VDDINT11VDDINT12VDDINT13VDDINT14
VDDINT2VDDINT3VDDINT4VDDINT5VDDINT6VDDINT7VDDINT8VDDINT9
VROUT1
VROUT2
DR0PRI
DR0SEC/PF20
DR1PRI
DR1SEC/PF25
DT0PRI/PF18
DT0SEC/PF17
DT1SEC/PF22
DTIPRI/PF23
MISO
MOSI
PF0/SPISS/TMR0
PF1/SPIS1/TMR1
PF10
PF11
PF12
PF13
PF14
PF15/TMRXCLK
PF2/SPIS2/TMR2
PF3/SPIS3/TMR3
PF4/SPIS4/TMR4
PF5/SPIS5/TMR5
PF6/SPIS6/TMR6
PF7/SPIS7/TMR7
PF8
PF9
RFS0/PF19
RFS1/PF24
RSCLK0/PF28
RSCLK1/PF30
RX/PF27
SCK
SLEEP
TCK
TDI TDO
TFS0/PF16
TFS1/PF21
TMS
TSCLK0/PF29
TSCLK1/PF31
TX/PF26
TRST EMU GENERAL PURPOSE / PUSH BUTTON STATUS INPUT/ UART SIGNAL
GENERAL PURPOSE / PUSH BUTTON STATUS INPUT
GENERAL PURPOSE
GENERAL PURPOSE
PF15
PF14
PROGR. FLAG
AD1836 CODEC RESET
ADV7179 VIDEO ENCODER RESET
ADV7183A VIDEO DECODER RESETPF13
PF12 GENERAL PURPOSE
PF11
PF10 GENERAL PURPOSE
PF9
PF8 GENERAL PURPOSE / PUSH BUTTON STATUS INPUT
PF7
PF6 GENERAL PURPOSE / PUSH BUTTON STATUS INPUT/ UART SIGNAL
PF5
FUNCTION
PF4 GENERAL PURPOSE / AD1836 LATCH SIGNAL
PF3 GENERAL PURPOSE / VIDEO DECODER FIELD
PF2 GENERAL PURPOSE / VIDEO DECODER OUTPUT ENABLE
PF1 GENERAL PURPOSE / I2C SERIAL DATA
PF0 GENERAL PURPOSE / I2C SERIAL CLOCK
L12
P16
M12
T14
M16
N15
T15
R15
R12
N11
P4
N5
R7
P7
T7
N8
R8
P8
T4
M6
R5
P6
T5
M7
R6
N6
R16
N13
P15
P13
T13
M11
T11
T9
R10 N9
L13
P14
T10
N16
R14
R13
P10 R11
U48
MBGA256ADSP-BF561SKBC-600
C11
F10F8
G14G2G6G7G8H1
H10H2
C13
H8H9 J11
J14J7K10K7K9L11L14
C5
L3L7L9M4M9N12N14N7P12P2D14P5P9
D5D6D8E1
E13
M5M13
A1
G16G3J6
K16K6
L10L5
M14T1
T12
A16
T16T3T6T8
A4A9
B11B6
D12E16
F2
E8
J9K11K8L8M8
F7F9G9H11H6H7J10J8
J1
J2
U48
MBGA256ADSP-BF561SKBC-600
1835-6-2004_16:04
DSP - PROGR. FLAGS, SPI
VDEC_RESET
TMS
TRST
TCK
TDI
PF15PF[15:0]
PF13
PF14
PF15
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PF8
PF9
PF10
PF11
PF12
PF13
PF14
R85
80510K 10K
805
R179
VROUT
DSP_VDD_INTDSP_VDD_EXT
DT0SEC
DT0PRI
TFS0
DR0SEC
DR0PRI
RFS0
TX
RX
SCK
MISO
MOSI
VENC_RESET
AD1836_RESET
5
6
7
81
2
4
3
RN1
RA8/38V10
10K805
R200
TDO
4.7K805
R86
EMU
RSCLK0
TSCLK1
TFS1
DT1PRI
DT1SEC
DR1SEC
DR1PRI
RFS1
RSCLK1
TSCLK0
OE OUT
CLK2
CLK1
GND
CLK3VDD
CLK4
CLKOUTREF
3.3V
3.3V
1A1
1A2
1A3
1A4
2A2
2A3
2A4
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2A1
2Y4
2Y3
OE1
OE2
1A1
1A2
1A3
1A4
2A2
2A3
2A4
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2A1
2Y4
2Y3
OE1
OE2
3.3V
ON1
23
4
PPI0_CLK
PPI0_D10/PF42
PPI0_D11/PF43
PPI0_D12/PF44
PPI0_D13/PF45
PPI0_D14/PF46
PPI0_D2
PPI0_D3
PPI0_D4
PPI0_D5
PPI0_D6
PPI0_D7
PPI0_D8/PF40
PPI0_D9/PF41
PPI0_SYN1/TMR8
PPI0_SYN2/TMR9
PPI0_SYN3
PPI1_CLK
PPI1_D0
PPI1_D1
PPI1_D10/PF34
PPI1_D11/PF35
PPI1_D12/PF36
PPI1_D13/PF37
PPI1_D14/PF38
PPI1_D15/PF39
PPI1_D2
PPI1_D3
PPI1_D4
PPI1_D5
PPI1_D6
PPI1_D7
PPI1_D8/PF32
PPI1_D9/PF33
PPI1_SYN1/TMR10
PPI1_SYN2/TMR11
PPI1_SYN3
PPI0_D15/PF47
PPI0_D1
PPI0_D0
JSZ
A0185-2003
ADSP-BF561 EZ-KIT LITE:10/10/03
1.3A
ANALOGDEVICES 4
3
2
1
A B C D
A B C D
4
3
2
1
Approvals Date
Drawn
Checked
Engineering Date
Size
Title
Board No.
Sheet ofC
PH: 1-800-ANALOGD
Nashua, NH 03063
20 Cotton Road
Rev
PPIxCLK
ONON
OFF ON
OFF EXPANSION_CLK
1 or 3PPIxCLK_SEL0 PPIxCLK_SEL1
2 or 4
X
PPI_27MHZ_CLK
SW5: PPI CLK Routing Select
VDEC_CLKOUT
(Default: 1 = OFF, 2 = ON, 3 = ON, 4 = ON)
R17133805
DSP - PPI0 AND PPI1
5-12-2004_16:32 4 18
C2
L1
J5
F4
E2
E3
D1
G5
J3
J4
K2
H5
K1
H4
K3
H3
E4
C1
D3
B1
R4
N4
N2
L6
N1
M2
K5
M1
R3
N3
T2
P3
R2
R1
P1
M3
K4
L2
L4
D2
ADSP-BF561SKBC-600MBGA256
U48
PPI1_D0
PPI1_D[15:0]
PPI1_D8
PPI1_D9
PPI1_D10
PPI1_D11
PPI1_D12
PPI1_D13
PPI1_D14
PPI1_D15
PPI1_D1
PPI1_D2
PPI1_D3
PPI1_D4
PPI1_D5
PPI1_D6
PPI1_D7
PPI1_D8
PPI1_D9
PPI1_D10
PPI1_D11
PPI1_D12
PPI1_D13
PPI1_D14
PPI1_D15
2
3
1
4 5
6
7
8
DIP4SWT018
SW5
8050.00R66
4
6
3
1
U23
SOT23-6ADG752BRT
1
3
6
4
U22
SOT23-6ADG752BRT
EXT_27MHZ_CLK
VDEC_CLKOUT
PPI_27MHZ_CLK
R181
80510K
R182
80510K
R175
80510K
R174
80510K
EXP_PPI0_CLK
EXP_PPI1_CLK
PPI1_CLK
2
4
6
8
13
15
17
18
16
14
12
9
7
11
3
5
1
19
SSOP20IDT74FCT3244APY
U30
2
4
6
8
13
15
17
18
16
14
12
9
7
11
3
5
1
19
SSOP20IDT74FCT3244APY
U13
1
3
6
4
U26
SOT23-6ADG752BRT
4
6
3
1
U25
SOT23-6ADG752BRT
1206270R220
2701206
R219
1206270R218
2701206
R217
1206270R216
2701206
R215
AMBER-SMTLED001
LED7
LED001AMBER-SMTLED8
AMBER-SMTLED001
LED9AMBER-SMTLED001
LED10AMBER-SMTLED001
LED11
LED001AMBER-SMTLED12
AMBER-SMTLED001
LED18AMBER-SMTLED001
LED19
2701206
R236
1206270R235
PPI0_CLK
80533R165
80533R172
R16633805
8050.00R178
1
2
3
4
56
7
8
U19
SOIC8IDT2305-1DC
OSC27MOSC_27M80533R59
1 3
U17
OSC00327MHZ27MHZ
VDEC_27MHZ_CLK
VENC_27MHZ_CLK80510KR162
AMBER-SMTLED001
LED15
LED001AMBER-SMTLED16
AMBER-SMTLED001
LED17
LED001AMBER-SMTLED20
1206270R237
2701206
R2322701206
R234
1206270R233
AMBER-SMTLED001
LED14
2701206
R231
AMBER-SMTLED001
LED13
2701206
R230
AMBER-SMTLED001
LED6
2701206
R214
AMBER-SMTLED001
LED5
2701206
R213
PPI0CLK_SEL0
PPI0CLK_SEL1
PPI1CLK_SEL0
PPI1CLK_SEL1
PPI0_SYNC3
PPI0_SYNC2
PPI0_SYNC1
PPI0_CLK PPI1_CLK
PPI1_SYNC1
PPI1_SYNC2
PPI1_SYNC3
PPI0_D15
PPI0_D14
PPI0_D13
PPI0_D12
PPI0_D11
PPI0_D10
PPI0_D9
PPI0_D8
PPI0_D[15:0]PPI0_D15
PPI0_D14
PPI0_D13
PPI0_D12
PPI0_D11
PPI0_D10
PPI0_D9
PPI0_D8
PPI0_D7
PPI0_D6
PPI0_D5
PPI0_D4
PPI0_D3
PPI0_D2
PPI0_D1
PPI0_D0
A0
A1
A10
A11
A12_NC
A2
A3
A4
A5
A6
A7
A8
A9
CKE
CLK
DQ0
DQ1
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQMH
DQML
CAS
CS
RAS
WE
BA1
BA0
A0
A1
A10
A11
A12_NC
A2
A3
A4
A5
A6
A7
A8
A9
CKE
CLK
DQ0
DQ1
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQMH
DQML
CAS
CS
RAS
WE
BA1
BA0
3.3V
3.3V
3.3V
RDY
A16
A18
A21
D13
VSS1
VSS2BYTE
CE
OE
RP
WE
WP/VPP
A8
A7
A6
A5
A9
A10
A11
A12
A0
A1
A2
A3
A4
A13
A14
A15
A17
A20
A19
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D14
VCC
D15
JSZ
A0185-2003
ADSP-BF561 EZ-KIT LITE:10/10/03
1.3A
ANALOGDEVICES 4
3
2
1
A B C D
A B C D
4
3
2
1
Approvals Date
Drawn
Checked
Engineering Date
Size
Title
Board No.
Sheet ofC
PH: 1-800-ANALOGD
Nashua, NH 03063
20 Cotton Road
Rev
4M x 16
0x2000 00000x0000 0000 0x03FF FFFF
0x207F FFFF
END
ASYNC Memory Bank 0
BANK
SDRAM 64MB(256Mb x 2 Chips)
FLASH A (8MB)
SDRAM Bank 0 64MB SDRAM
DEVICE
8MB FLASH
START
Memory Map
MEMORY - FLASH & SDRAM
12-16-2003_11:03 5 18
15
48
16
13
41
27
4647
26
28
12
11
14
8
18
19
20
7
6
5
4
25
24
23
22
21
3
2
1
17
10
9
29
31
33
35
38
40
42
44
30
32
34
36
39
43
37
45
U27
TSOP48M29W64OD
FLASH_RDY
R183
80510K
R189
80510K
R177
80510K
R190
80510K
AWE
AMS0
AOE
FLASH_RP
FLASH_WP
D[31:0]
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D13
D14
D19
D21
D24
D25
D26
D31
D30
D29
D28
D27
D23
D22
D20
D18
D17
D16
D15
D12
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
ABE3
ABE3
ABE2
SMS0
SCKE
ABE1
ABE0
SRAS
SCAS
SWE
SA10
23
24
22
35
36
25
26
29
30
31
32
33
34
37
38
2
4
45
47
48
50
51
53
5
7
8
10
11
13
42
44
39
15
17
19
18
16
21
20
U32
TSOP54MT48LC16M16A2TG-75
23
24
22
35
36
25
26
29
30
31
32
33
34
37
38
2
4
45
47
48
50
51
53
5
7
8
10
11
13
42
44
39
15
17
19
18
16
21
20
U33
TSOP54MT48LC16M16A2TG-75
SCLK0
A[25:2]
A2
A19
A19
A18
A14
A13
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A18
A14
A13
A11
A10
A9
A8
A7
A6
A5
A4
A3
A22
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
3.3V
AGND
AGND
AGND
AGND
AGND
OE OUT
3.3V
12
45
6
ON
3
PD/RST
IN2R+/CR2/CR2
IN2R-/CR1/CR1
NC/IN2R1/IN2R+
NC/IN2R2/IN2R-
NC/IN2L2/IN2L-
NC/IN2L1/IN2L+
IN2L-/CL1/CL1
IN2L+/CL2/CL2
FILTD
FILTR
OUT3R-
OUT3R+
OUT3L-
OUT3L+
OUT2R-
OUT2R+
OUT2L-
OUT2L+
OUT1R-
OUT1R+
OUT1L-
OUT1L+
IN1R-
IN1R+
IN1L-
IN1L+
COUT
CDATA
CCLK
CLATCH
MCLK
DLRCLK
DBCLK
ASDATA1
ASDATA2
ALRCLK
ABCLK
DSDATA2
DSDATA1
DSDATA3
JSZ
A0185-2003
ADSP-BF561 EZ-KIT LITE:10/10/03
1.3A
ANALOGDEVICES 4
3
2
1
A B C D
A B C D
4
3
2
1
Approvals Date
Drawn
Checked
Engineering Date
Size
Title
Board No.
Sheet ofC
PH: 1-800-ANALOGD
Nashua, NH 03063
20 Cotton Road
Rev
Default = All OffFor Test Purposes
DAC1 RIGHT
DAC2 LEFT
DAC2 RIGHT
DAC3 LEFT
DAC3 RIGHT
ADC2 LEFT
ADC2 RIGHT
AUDIO CODEC
DA
C1
DA
C2
DA
C3
AD
C1
AD
C2
IN (J5)OUT (J4)
RIGHT (RED)
LEFT (WHITE)
DAC1 LEFT
DAC1 RIGHT
ADC1 RIGHT
ADC1 LEFT
DAC1 LEFT
SW10: Audio Loopback
1865-12-2004_16:35
AUDIO CODEC
R46
80510K
R47
80510K10K
805
R45
AD1836_VREF
9
7
J5
CON0243X2
8
9
J5
CON0243X2
3
27
26
25
24
23
22
21
20
12
13
34
35
5
4
32
33
7
6
30
31
9
8
19
18
17
16
49
2
51
50
45
38
41
42
36
37
47
48
44
43
MQFP52AD1836AAS
U15
PF4
R158
80510K
AD1836_RESET
1
2
3
4
5
6 7
8
9
10
11
12
SWT017DIP6
SW10
MISO
MOSI
TSCLK0
DT0SEC
DT0PRI
TFS0
SCK
AD1836_CLK
RSCLK0
RFS0
DR0SEC
DR0PRI
IN2L1
0.1UF805
C123
B10UFCT16
AD1836_CLK
IN1L+
OUT1L+
OUT1L-
OUT1R-
OUT1R+
33805
R61
IN1R-
IN1R+
IN1L-
IN2R1
IN2R2
IN2L2
10K805
R57
R44
12060.00
12060.00R43
0.001206
R55
6
5
7
SOIC8AD8606AR
U12
1
3
2
AD8606ARSOIC8
U12
1
3
2
AD8606ARSOIC8
U5
R1590.001206
DAC1_LEFT
CAP00210UFCT7
49.9K1206
R109
DAC1_RIGHT
CAP00210UFCT8
OUT3R+
OUT3R-
OUT3L-
OUT2R-
OUT2L-
12062.74KR150
1 3
OSC00312.288MHZ
U16
8050.001UFC40
10UFB
CT15
8050.1UFC124
ADC1_RIGHT
ADC1_LEFT
DAC2_LEFT
DAC3_LEFT
DAC3_RIGHT
DAC2_RIGHT
DAC1_RIGHT
DAC1_LEFT
80510KR161
ADC2_LEFT
ADC2_RIGHT
0.001UF805
C38
8050.001UFC39
0.001UF805
C133
OUT1L+
OUT1L-
OUT1R+
OUT1R-
OUT2L+
OUT2R+
OUT3L+
7
5
6
AD8606ARSOIC8
U5
5.49K1206
R30
11.0K1206
R145
12062.74KR151
1206604R126
220PF1206
C14
1.65K1206
R29
100PF1206
C7
3.32K1206
R138
5.49K1206
R18
680PF805
C117
330PF805
C96
2200PF1206
C77
5.49K1206
R27
1206604R125
220PF1206
C13
1.65K1206
R28
100PF1206
C6
3.32K1206
R137
5.49K1206
R17
680PF805
C116
330PF805
C95
11.0K1206
R144
2200PF1206
C7649.9K1206
R108
0.001206
R71
AGND
AGND
AGND
AGND
JSZ
A0185-2003
ADSP-BF561 EZ-KIT LITE:10/10/03
1.3A
ANALOGDEVICES 4
3
2
1
A B C D
A B C D
4
3
2
1
Approvals Date
Drawn
Checked
Engineering Date
Size
Title
Board No.
Sheet ofC
PH: 1-800-ANALOGD
Nashua, NH 03063
20 Cotton Road
Rev
DAC2 RIGHT
DAC3 RIGHT
DAC3 LEFTDAC2 LEFT
AUDIO OUT
18712-10-2003_18:18
2
3
J5
CON0243X2
3
1
J5
CON0243X2
5
6
J5
CON0243X2
4
6
J5
CON0243X2
AD1836_VREF
7
5
6
AD8606ARSOIC8
U7
1
3
2
AD8606ARSOIC8
U7
OUT2L+
OUT2L-
OUT3L+
OUT3L-
OUT3R+
OUT3R-
OUT2R-
OUT2R+
49.9K1206
R113
DAC3_RIGHT
CAP00210UFCT12
DAC3_LEFT
49.9K1206
R112
CAP00210UFCT11
49.9K1206
R110
DAC2_LEFT
CAP00210UFCT9
49.9K1206
R111
DAC2_RIGHT
CAP00210UFCT10
1206604R130
2200PF1206
C81
5.49K1206
R38
11.0K1206
R149
2200PF1206
C80
1206604R129
1.65K1206
R36
220PF1206
C17
100PF1206
C10
3.32K1206
R141
5.49K1206
R21
11.0K1206
R148
5.49K1206
R35
12062.74KR155
220PF1206
C18
1.65K1206
R37
100PF1206
C11
3.32K1206
R142
5.49K1206
R22
680PF805
C121
330PF805
C100
12062.74KR154
680PF805
C120
330PF805
C997
5
6
AD8606ARSOIC8
U6
12062.74KR153
5.49K1206
R34
1206604R127
220PF1206
C16
1.65K1206
R33
100PF1206
C9
3.32K1206
R140
5.49K1206
R20
680PF805
C119
330PF805
C98
11.0K1206
R147
2200PF1206
C78
1
3
2
AD8606ARSOIC8
U6
12062.74KR152
5.49K1206
R31
1206604R128
220PF1206
C15
1.65K1206
R32
100PF1206
C8
3.32K1206
R139
5.49K1206
R19
680PF805
C118
330PF805
C97
11.0K1206
R146
2200PF1206
C79
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGNDAGND
AGND
AGND
AGND
AGND
JSZ
A0185-2003
ADSP-BF561 EZ-KIT LITE:10/10/03
1.3A
ANALOGDEVICES 4
3
2
1
A B C D
A B C D
4
3
2
1
Approvals Date
Drawn
Checked
Engineering Date
Size
Title
Board No.
Sheet ofC
PH: 1-800-ANALOGD
Nashua, NH 03063
20 Cotton Road
Rev
ADC1 RIGHT
ADC1 LEFT
ADC2 RIGHT
ADC2 LEFT
AUDIO IN
12-10-2003_18:18 8 18
6
4
J4
CON0132X2
5
6
J4
CON0132X2
3
1
J4
CON0132X2
2
3
J4
CON0132X2
AD1836_VREF
IN2R1
IN2R2
IN2L1
IN2L2
6
5
7
AD8606AR
U24
SOIC8
7
5
6 U18
AD8606ARSOIC8
100PFC34
1206
C250.001UF805
C230.001UF805
C26100PF1206
0.001UFC33
805
0.001UFC36
805
2
3
1
AD8606AR
U24
SOIC8
1
3
2 U18
AD8606ARSOIC8
2
3
1
AD8606AR
U9
SOIC8
6
5
7
AD8606AR
U9
SOIC8
750KR173
1206
1206
C163120PF
5.76KR70
12065.76KR64
1206
120PFC161
1206
5.76KR69
12065.76KR124
1206CAP00210UFCT14
1206100PFC61
1206600FER9
ADC2_RIGHT
IN1R-
237R25
1206
120PFC103
1206
R155.76K1206
R1225.76K1206
10UFCT6
CAP002
ADC1_RIGHT
FER116001206
100PFC63
1206
750KR132
1206
R85.76K1206
R165.76K1206
1206
C105120PF
237R26
1206
IN1R+
ADC1_LEFT
IN1L+
IN1L-
7
5
6 U11
AD8606ARSOIC8
1
3
2 U11
AD8606ARSOIC8
FER106001206
ADC2_LEFT
R1235.76K1206
CT510UFCAP002
R405.76K1206
1206120PFC130
R505.76K1206
C128120PF1206
R532371206
R495.76K1206
C62100PF1206
R542371206
R156750K1206
12065.76KR121
R625.76K1206
R164750K1206
FER126001206
C72100PF1206
C142120PF1206
R585.76K1206
R635.76K1206
1206120PFC144
CT1310UFCAP002
ON1
23
4
AGND2
AGND2
AGND2
A3V
A3V
A3V
AGND2
SOT23DAD1580
ALSB
BLANK
CLOCK
COMP
DAC_A
DAC_B
DAC_C
FIELD/VSYNC
GND1
GND10
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
HSYNC
P0
P1
P2
P3
P4
P5
P6
P7
RSET
SCLOCK
SCRESET/RTC
SDATA
TTX
TTXREQ
VAA1
VAA2
VAA3
VAA4
VAA5
VREF
RESET
JSZ
A0185-2003
ADSP-BF561 EZ-KIT LITE:10/10/03
1.3A
ANALOGDEVICES 4
3
2
1
A B C D
A B C D
4
3
2
1
Approvals Date
Drawn
Checked
Engineering Date
Size
Title
Board No.
Sheet ofC
PH: 1-800-ANALOGD
Nashua, NH 03063
20 Cotton Road
Rev
CVSB
Component Video
S Video
Composite Video
Differential Component Video
CVSB
DAC B
DAC C
DAC A
VIDEO ENCODER
DAC A DAC B DAC C
C
G B R
VUY
Y C
SW11: Video Loopback
Default = All OffFor Test Purposes
5-12-2004_16:35 9 18
VIDEO ENCODER (VIDEO OUT)
3
2
J6
CON0243X2
5
6
J6
CON0243X2
8
9
J6
CON0243X2
16
15
1
23
29
28
24
14
6
40
7
8
9
11
12
17
19
26
13
35
36
37
38
39
3
4
5
31
21
32
22
34
33
2
10
18
25
27
30
20
U8
LFCSP40ADV7179
VENC_RESET
R143
80510K
1206100KR9
VENC_HS
VENC_VS
3V_B
12061.2KR23
3V_B 1501206
R3
10K805
R14
1
2
D1
VIDEO_DAC_B
VENC_27MHZ_CLK
PF[15:0]PF1
PF0
PPI1_D[15:0]PPI1_D6
PPI1_D5
PPI1_D4
PPI1_D3
PPI1_D2
PPI1_D1
PPI1_D7
PPI1_D0
100K1206
R132.2UH805
L7
0.1UF805
C12
805330PFC86
1
2
5
3
4
AD8061ART
U2
SOT23-5
2.2UH805
L9
2.2UH805
L5
8050.68UHL1
0.68UH805
L4
0.68UH805
L6
8050.68UHL3
8050.68UHL8
0.68UH805
L2
4
3
5
2
1
AD8061ART
U3
SOT23-5
4
3
5
2
1
AD8061ART
U1
SOT23-5
330PF805
C92
12061KR136
8050.1UFC115
120675R107
12061KR115
12061KR116
805330PFC82
751206
R4
120675R135
330PF805
C94
805330PFC93
751206
R134
120675R5
330PF805
C84
1K1206
R118
1K1206
R117
751206
R105
120675R104
12061KR10
751206
R6
120675R114
12060.00R133
VIDEO_DAC_C
VIDEO_DAC_A
VIDEO_AVIN4
VIDEO_AVIN1
VIDEO_AVIN5 VIDEO_DAC_B
VIDEO_DAC_C
VIDEO_DAC_A2
3
1
4 5
6
7
8
DIP4SWT018
SW11
AGND2
1.8V
A1.8V
3.3V
3.3V
AGND2
AGND2AGND2
AGND2 AGND2
A3V A5V
AGND2
AGND1
AGND2
AGND3
AGND4
AGND5
AIN1
AIN10
AIN11
AIN12
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
ALSB
AVDD
CAPC1
CAPC2
CAPY1
CAPY2
CML
DGND1
DGND2
DGND3
DGND4
DGND5
DVDD1
DVDD2
DVDD3
DVDDIO1
DVDDIO2
ELPF
FIELD
HS
LLC1
LLC2
NC[AEF]
NC[AFF]
NC[AGND6]
NC[CLKIN]
NC[GPO0]
NC[GPO1]
NC[GPO2]
NC[GPO3]
NC[ISO]
NC[DV]
NC[HREF]
NC[LLCREF]
NC[RD]
NC[VREF]
P0
P1
P10
P11
P12
P13
P14
P15
P2
P3
P4
P5
P6
P7
P8
P9
PVDD
REFOUT
SCLK
SDA
SFL[HFF]
VS
XTAL
XTAL1
OE
PWRDN
RESET
JSZ
A0185-2003
ADSP-BF561 EZ-KIT LITE:10/10/03
1.3A
ANALOGDEVICES 4
3
2
1
A B C D
A B C D
4
3
2
1
Approvals Date
Drawn
Checked
Engineering Date
Size
Title
Board No.
Sheet ofC
PH: 1-800-ANALOGD
Nashua, NH 03063
20 Cotton Road
Rev
3.3V
12
34
56
ON
SW2: Video Sync Signals and Encoder Enable Select
CVBSCVBSComposite Video
AVIN1 AVIN4 AVIN5
Y
YS Video
Differential Component Video
AVIN5
AVIN4
AVIN1
CVBS
(RED) IN
DA
C_B
DA
C_C
DA
C_D
AV
IN4
AV
IN1
AV
IN5
(WHITE) OUT
C
V U
VIDEO DECODER
OFF = Encoder digital interface always disabledthe encoder digital interface
ON = PF2 Used to enable or disable
Function1-5
Position
6
Connect video sync signals to DSP
Note: Signal Names in brackets refer to ADV7183KST
Defalut = OFF, OFF, OFF, OFF, OFF, ON
1
10
11
12
2
3
4
5
67
8
9
SW2
SWT017DIP6
181012-16-2003_11:24
VIDEO ENCODER (VIDEO IN)
1
3
J6
CON0243X2
6
4
J6
CON0243X2
7
9
J6
CON0243X2
39
40
47
53
56
42
57
59
61
44
46
58
60
62
41
43
45
66
50
54
55
48
49
52
3
9
14
31
71
30
10
72
4
15
37
80
2
27
26
13
11
63
16
78
35
34
18
17
70
65
77
69
25
33
32
6
5
76
75
74
73
24
23
22
21
20
19
8
7
38
51
68
67
12
1
29
28
79
36
64
U4
LQFP80ADV7183AKST
0.1UF805
C57
PVDD_ADV7183
1206600
DNPFER1
1206600FER2
8050.001UFC67
8050.001UFC68
8050.01UFC5
80582NFC64
PVDD_ADV7183
1.5K805
R1
6001206
FER15
1206600
DNPFER17
B10UFCT2
10UFB
CT40.1UF805
C59
0.1UF805
C2
B10UFCT1
B10UFCT3
751206
R102
120675R101
0.1UF805
C54
0.1UF805
C56
1206600FER14
DNP
6001206
FER13
0.1UF805
C1
0.1UF805
C4
0.1UF805
C73
PPI0_D[15:0]
PPI0_D1
PPI0_D6
PPI0_D5
PPI0_D4
PPI0_D3
PPI0_D2
PPI0_D7
PPI0_D0
VIDEO_AVIN1
DVDD_ADV7183
PF[15:0]PF1
PF0
VDEC_HREF
VDEC_FIELD
VDEC_VS
PPI0_SYNC2
R41
80533
VENC_VS
VENC_HS
VDEC_VREF
PPI1_SYNC1
VDEC_CLKOUT
PF[15:0]PF3
PF2
10K805
R24
33805
R39VDEC_RESET
VDEC_27MHZ_CLK
VIDEO_AVIN5
VIDEO_AVIN4
8050.1UFC60
0.1UF805
C66
TP1
TP2
TP3
1
24
U10
SOT23-5SN74LVC1G32
8050.01UFC74
8050.1UFC55
0.01UF805
C3
8050.00R99
80510KR11
10K805
R12
0.00805
R103
8050.1UFC65
80510KR131
10K805
R2
120675R100
8050.00R106
PPI0_SYNC1
PPI1_SYNC2
VDEC_HS
R7
80510K
0.1UF805
C58
JSZ
A0185-2003
ADSP-BF561 EZ-KIT LITE:10/10/03
1.3A
ANALOGDEVICES 4
3
2
1
A B C D
A B C D
4
3
2
1
Approvals Date
Drawn
Checked
Engineering Date
Size
Title
Board No.
Sheet ofC
PH: 1-800-ANALOGD
Nashua, NH 03063
20 Cotton Road
Rev
3.3V
PFI
RESETMR
PFO
RESET
3.3V
3.3V
3.3V
5V 3.3V
3.3V
3.3V
3.3V
3.3V
C1+
C1-
C2+
C2-
R1INR1OUT
R2INR2OUT
T1OUT
T2IN T2OUT
V-
V+
T1IN
3.3V
12
34
56
ON
SW4 PB Enable Switch
USB RESET
POWERRESET
RESET
FunctionConnects the push buttons to the Programmable Flags of the DSPUseful if using the PFs for another purpose.
Position
1-4
5,6
PF5
PF6
PF7
PF8
NOTE: Remove R192 when populating R191 and R184
UART
Default = ON, ON, ON, ON, OFF, OFF
OFF, OFF = AD1836A -> TDM ModeON, ON = AD1836A -> I2S Mode
1
10
11
12
2
3
4
5
6 7
8
9
SW4
SWT017DIP6
RESET, PUSH-BUTTON SWITCHES, UART
12-16-2003_11:24 11 18
2
1P1
IDC2X12X1
1
24
U28
SOT23-5SN74AHC1G00
1
3
4
5
1312
89
14
10 7
6
2
11
ADM3202ARN
U21
SOIC16
TSCLK0RSCLK0
1 2
74LVC14ASOIC14
U47
8050.1UFC158
80510KR98
PF6
PF5
PF8
PF7
PF6
PF[15:0]
PF5
RESET
USB_RESETUSB_CONFIGURED
SOFT_RESET
RFS0
603600FER18
TFS0
4
81
5
7
SOIC8ADM708SAR
U46
R1920.00805
DNP
0.00805
R191
R184
8050.00
DNP
3
4
5
1
6
2
7
8
9
P2
DB9M9PIN
SWT013SPST-MOMENTARY
SW6
SPST-MOMENTARYSWT013SW7
SWT013SPST-MOMENTARY
SW8
SPST-MOMENTARYSWT013SW9
100805
R245
12060.00R225
5 6
SOIC1474LVC14A
U47
805100R244
0.001206
R224
89
SOIC1474LVC14A
U47
600603
FER20
600603
FER19
603600FER21
SWT013SPST-MOMENTARY
SW1
0.1UF805
C159
0.1UF805
C147
8050.1UFC148
TX
RX
LED001RED-SMTLED2
1206270R120
13 12
74LVC14ASOIC14
U47
10K805
R251
1206680R119
GREEN-SMTLED001
LED1
80510KR229
RED-SMTLED001
LED3
2701206
R19312060.00R223
10K805
R185
11 10
74LVC14ASOIC14
U47
0.001206
R247
80510KR250
100805
R243
43
74LVC14ASOIC14
U47
A1UFCT27
1UFA
CT28
10K805
R249
80510KR248
805100R242
1UFA
CT26
A1UFCT25
80510KR246
5V
5V
3.3V
3.3V
JSZ
A0185-2003
ADSP-BF561 EZ-KIT LITE:10/10/03
1.3A
ANALOGDEVICES 4
3
2
1
A B C D
A B C D
4
3
2
1
Approvals Date
Drawn
Checked
Engineering Date
Size
Title
Board No.
Sheet ofC
PH: 1-800-ANALOGD
Nashua, NH 03063
20 Cotton Road
Rev
SPORT0
EXPANSION INTERFACE (TYPE B)
5-12-2004_16:35 12 18
EXTENDER CARD CONNECTORS
PF13
PF11
PF9
PF4
PF10
PF12PF[15:0]
PF14
PF8
PF6
PF7
PF3
PF1PF0
PF2
PF0
PF5
PF15
87
85
83
81
77
75
73
69
67
65
63
61
59
57
1
10
1112
1314
1516
1718
19
2
20
2122
2324
2526
2728
29
3
30
3132
3334
3536
3738
39
4
40
4142
4344
4546
4748
5
50
6
78
9
49
55
51
53
52
54
56
58
60
62
66
70
68
72
74
76
78
80
82
84
86
88
90 89
64
71
79
CON01945X2
J3
87
85
83
81
77
75
73
69
67
65
63
61
59
57
1
10
1112
1314
1516
1718
19
2
20
2122
2324
2526
2728
29
3
30
3132
3334
3536
3738
39
4
40
4142
4344
4546
4748
5
50
6
78
9
49
55
51
53
52
54
56
58
60
62
66
70
68
72
74
76
78
80
82
84
86
88
90 89
64
71
79
J2
45X2CON019
87
85
83
81
77
75
73
69
67
65
63
61
59
57
1
10
1112
1314
1516
1718
19
2
20
2122
2324
2526
2728
29
3
30
3132
3334
3536
3738
39
4
40
4142
4344
4546
4748
5
50
6
78
9
49
55
51
53
52
54
56
58
60
62
66
70
68
72
74
76
78
80
82
84
86
88
90 89
64
71
79
J1
45X2CON019
EXT_27MHZ_CLK
PPI1_SYNC1
DSP_VDD_EXT DSP_3V_VOUT
PPI1_SYNC2
EXT_DSP_CLK
RSCLK1
MISO
MOSI
ABE0
ABE1
ABE2
ABE3
SMS0
SMS2
SWE
SA10
SRAS
ARE
ARDY
SMS3
AMS0
AMS1
AMS2
AMS3
SCAS
SCKE
DR0PRI
DR0SEC
PPI0_SYNC1
PPI0_SYNC2
PPI1_SYNC3
PPI1_D[15:0]
PPI1_D15
PPI1_D9
PPI1_D7
PPI1_D5
PPI1_D3
PPI1_D1
PPI1_D2
PPI1_D4
PPI1_D6
PPI1_D8
PPI1_D10
PPI1_D12
PPI1_D14
PPI1_D0
PPI1_D11
PPI1_D13
D[31:0]
D1
D30D31
D16
D18
D26
D28
D24
D22
D20
D17
D19
D21
D23
D25
D27
D29
D10
D14
D12
D4
D6
D8
D0
D2D3
D5
D7
D9
D11
D13
D15
EXP_PPI1_CLK
RESET
VDEC_HS
VDEC_FIELD
VDEC_HREF
TX RX
PPI0_SYNC3
DR0PRI
RSCLK0
RFS0
0.001206
R80
DR0SEC
DT0PRI
TSCLK0
TFS0
DT0SEC
A[25:2]
A3
A20
A22
A21
A23
A19 A18
A2
A16
A14
A12
A10
A8
A6
A4
A17
A15
A13
A11
A9
A7
A5
A25 A24
PPI0_D[15:0]
PPI0_D5
PPI0_D15
PPI0_D1
PPI0_D3
PPI0_D0
PPI0_D2
PPI0_D14
PPI0_D12
PPI0_D10
PPI0_D8
PPI0_D6
PPI0_D4
PPI0_D13
PPI0_D11
PPI0_D9
PPI0_D7
EXP_PPI0_CLKAWE
AOE
TSCLK0
TFS0
DT0PRI
DT0SEC
TSCLK1
TFS1
DT1PRI
DT1SEC
CLK_OUT_EXP1
SCK
NMI0
DR1SEC
DR1PRI
RFS1
RFS0
RSCLK0
SMS1
CLK_OUT_EXP2
VDEC_VREF
12060.00R72
5
2
4
8
10
6
1
3
9
11
13
15
17
19
12
14
16
20
18
7
10X2CON014
P3
BGH
BG
BR
VDEC_VS
GND
INPUT OUTPUT1
OUTPUT2
GND
INPUT OUTPUT1
OUTPUT2
3.3V
FBGND
INPUT
OUTPUT
ERR
SD
SHGNDSHGND
1.8V
A3V
A5V
A1.8V
SHGND
SHGND
3.3V 3.3V
CHOKE_COIL
VIN
SHDN
SYNC
GND
BOOST
SW
FB
VC
5V
OUT1
OUT2
OUT3
IN1
IN2
FBSD GND
3.3V
JSZ
A0185-2003
ADSP-BF561 EZ-KIT LITE:10/10/03
1.3A
ANALOGDEVICES 4
3
2
1
A B C D
A B C D
4
3
2
1
Approvals Date
Drawn
Checked
Engineering Date
Size
Title
Board No.
Sheet ofC
PH: 1-800-ANALOGD
Nashua, NH 03063
20 Cotton Road
Rev
3.3V
GND
INPUT OUTPUT1
OUTPUT2
OUT1
OUT2
OUT3
IN1
IN2
FBSD GND
NOTE: R252 or R253 gets populated
Default is R252 IN and R253 OUT
1
2
3
7
8
56
4MSOP8ADP3336ARM
VR4
0.00805
R82
DNP
0.00805
R81
POWER
18135-12-2004_16:35
1
3 2
4
VR6
SOT-223ADP3339AKC-33
UNREG_IN
DSP_3V_VOUT
DSP_VDD_EXT
3.32KR195
805
CT21
C10UF
8050.00R252
DNP
0.00805
R253
1
3
2
CON0052.5MM_JACK
7.5V_POWER
J7
MH4
0.00805
R84
8050.00R74
147KR56
1206
76.8KR48
12068051UFC24
8051UFC21
10K805
R52
8051UFC45
10K805
R781
2
3
7
8
56
4MSOP8ADP3336ARM
VR26001206
FER4
6001206
FER3
CT19100UFC
4.7UFC169
805
R211340K805
3.32KR194
805
10.0KR186
1206
R18017.4K805
12060.00R163
DSP_VCORE
FPGA_1V8
3V_B
DSP_VDD_INT
DSP_VDD_EXT
2ADO-214AA
D7
805698KR210
VROUT
UNREG_IN
7
6
3
1
4
8
5
2
LT1765SO-8
VR5
4
1
3
2
FER5
UNREG_IN D4
100MASOD-323
CMDSH-3
8051UFC44
CT22
D68UF
CT18
C10UF
4
3
2
1
8
7
6
5
U29
SO-8NDS8434A
TP7
53.6KR75
805
FUS0012.5AF1
8050.00R77
1MR76
805
8051UFC32
C48
8050.1UF
TP10
8050.00R83
IND00110UHL11
3
1 1A
ZHCS1000SOT23D
D5
8050.1UFC122
10UFC
CT240.1UF805
C29
C10UFCT17
C530.1UF805
0.001206
R73
TP9
12061000PFC153
DO-214AA2AD2
12061000PFC160
1206600FER6
TP6
1206600FER16
MH2 MH1 MH5MH3
DO-214AA2AD3
1206100KR157
C10UFCT23
1206600FER8
TP4
8050.1UFC35
TP5 TP11TP8
CT2010UFC
1.5UHL10
IND003
D6
2ADO-214AA
SL22
0.18UFC170
805
2200PFC46
1206
C432.2UF805
R79
8050.00
5
4
2
6 1
3
VR7
SOT23-6ADP3331ART
12060.00R90
0.47UF805
C230C218
8050.47UF
805332KR207
UNREG_IN
1
3 2
4
ADP3338AKC-33SOT-223
VR31
3 2
4
ADP3339AKC-5SOT-223
VR1
1V2
DSP_VDD_INT
3.3V
3.3V 3.3V 3.3V
3.3V
3.3V
AGND2
A3V A3V A3VA5V A5VA5V
AGND
AGND AGND AGND
A5V
AGND
A5V
AGND
AGND
A5V
AGND
A5V A5V
5V
AGND
A5V
AGND2AGND2
3.3V
3.3V 3.3V3.3V3.3V3.3V
3.3V 3.3V 3.3V
3.3V 3.3V3.3V3.3V3.3V
JSZ
A0185-2003
ADSP-BF561 EZ-KIT LITE:10/10/03
1.3A
ANALOGDEVICES 4
3
2
1
A B C D
A B C D
4
3
2
1
Approvals Date
Drawn
Checked
Engineering Date
Size
Title
Board No.
Sheet ofC
PH: 1-800-ANALOGD
Nashua, NH 03063
20 Cotton Road
RevSDRAM
IDT74FCT3244APY ADG752 ADG752
AD8606 AD8606AD8606AD8606 AD8606 AD8061AD8061U23 U24U22
AD8061U15 U17U16 U20U18
ADG752 ADG752U26U25
U30ADM3202
U29ADM708SAR
U27ADV7183
U28IDT74FCT3244APY
U31
AD1836U14
U5SDRAM
U874LVC00AD
U974LVC14A
U10 AD8606U12
AD8606U13
AD8606U19
IDT2305U46
U21SN74AHC1G08
IDT2305U4
M29W640D
ADV7179U54
39MHZ OSC
U327MHZ OSC
ADSP-DM203
U40 U45U36
U53
U1
DECOUPLING CAPS
18145-12-2004_16:35
DVDD_ADV7183
3V_B
DSP_VDD_INT
C28
8050.01UF
0.1UF805
C1750.01UF805
C1370.01UF805
C1400.1UF805
C1550.01UF805
C49
8050.01UFC146
8050.01UFC138
0.01UF805
C176
8050.1UFC184
8050.1UFC183
8050.1UFC126
8050.1UFC135
8050.01UFC101
0.01UF805
C1140.1UF805
C91
8050.1UFC89
0.1UF805
C1020.1UF805
C90
8050.1UFC109
8050.1UFC110
0.01UF805
C113 C112
8050.01UF
8050.1UFC87
0.1UF805
C111
8050.1UFC88
0.01UF805
C2490.01UF805
C1410.01UF805
C181
8050.01UFC150
8050.01UFC149
8050.01UFC69
8050.1UFC83C70
8050.01UF0.1UF
805
C850.01UF805
C75
8050.1UFC71
0.22UF805
C1040.22UF805
C1290.22UF805
C1430.22UF805
C1620.22UF805
C1070.22UF805
C1080.1UF805
C22
8050.1UFC131
8050.1UFC37
8050.1UFC19
0.01UF805
C134
0.22UF805
C106
8050.22UFC125
0.01UF805
C256C180
8050.01UF
C182
8050.01UF
8050.01UFC200
8050.01UFC201
8050.01UFC186
8050.01UFC185
0.01UF805
C156
8050.01UFC157
8050.01UFC168
8050.01UFC136
0.1UF805
C171
8050.1UFC139
0.1UF805
C164
8050.1UFC52
8050.1UFC152
0.1UF805
C178
8050.1UFC172
0.1UF805
C1450.01UF805
C154
8050.01UFC173
10UF1210
C4710UF1210
C50
121010UF
C31
8050.01UFC174
8050.1UFC30
0.1UF805
C151
8050.1UFC179
8050.1UFC27
C200.1UF805
8050.1UFC132
8050.01UFC166
8050.01UFC165
0.01UF805
C127
C188
8050.01UF
8050.1UFC191
8050.1UFC189
8050.01UFC187
8050.01UFC190
8050.01UFC203
8050.01UFC202
0.1UF805
C167
8050.1UFC177
8050.01UFC41
0.1UF805
C51
DSP_VDD_EXT
3.3V
3.3V
3.3V3.3V
I0A
I0B
I0C
I0D
I1A
I1B
I1C
I1D
S
YA
YB
YC
YD
E
I0A
I0B
I0C
I0D
I1A
I1B
I1C
I1D
S
YA
YB
YC
YD
E
3.3V
JSZ
A0185-2003
ADSP-BF561 EZ-KIT LITE:10/10/03
1.3A
ANALOGDEVICES 4
3
2
1
A B C D
A B C D
4
3
2
1
Approvals Date
Drawn
Checked
Engineering Date
Size
Title
Board No.
Sheet ofC
PH: 1-800-ANALOGD
Nashua, NH 03063
20 Cotton Road
Rev
ADG774A12.288MHz ADG774A
DSP JTAG HEADER
All USB interface circuitry is considered propreitary andh hasbeen omitted from this schematic
When designin your JTAG interface please refer to theEngineer to Engineer Note EE-68 which can be found athttp://www.analog.com
12-11-2003_13:22 15 18
DEBUG AGENT - JTAG
EMU
TDO
TDI
TMS
TRST
TCK
8050.00R87
USB_TCK
USB_TDO
EMULATOR_EMU
USB_EMU
805
R20110K
805
R23910K
C209
4020.1UF0.1UF
402
C195
2
5
11
14
3
6
10
13
1
4
7
9
12
15
U37
QSOP16ADG774A
USB_TDI
USB_TRST
USB_TMS
EMULATOR_TMS
EMULATOR_TCK
EMULATOR_TRST
EMULATOR_TDI
EMULATOR_TDO
2
5
11
14
3
6
10
13
1
4
7
9
12
15
U36
QSOP16ADG774A
10KR241
805
1
3
5
7
9
11
13
2
4
6
8
10
12
14
P4
IDC7X27X2
C196
4020.1UF
I INDEX
A C
AD1836A, audio codec, 1-10, 2-3, 2-12address bus (A25-A2), 2-3ADSP-BF561 processoraudio interface, see SPORT0core voltage, 2-2External Bus Interface Unit (EBIU), 2-3external memory, 1-6IO voltage, 2-2parallel peripheral interfaces (PPIs), 2-6peripheral ports, xiiSDRAM memory map, 1-7see also input clock
ADV7179, video encoder, 1-11, 2-7, 2-10ADV7183A, video decoder, 1-11, 2-8, 2-10~AMS0, memory select pin, 1-7ASYNC memory bank 0, 1-6audio
applications, xiiconnectors (J4, J5), 2-18interface, see SPORT0see AD1836A
Bbackground telemetry channel (BTC), 1-13bill of materials, A-1boot mode switch (SW3), 2-11
clockfrequency, 1-8PPI interfaces, 2-13select switch (SW5), 2-13source setup, 2-13
codecs, see AD1836A, ADV7179, ADV7183Aconnectors, 1-3, 2-17
J1-3 (expansion interface), 2-9J4-5 (audio), 2-18J6 (video), 2-18J7 (power), 2-18J8 (USB), 2-19P4 (JTAG), 2-9, 2-20P9 (SPORT0), 2-20RS232 (P2), 2-20
contents, EZ-KIT Lite package, 1-2control bus, 2-3customer support, xivcycle counters, 1-16
DD15-8 pins
PPI0, 1-9PPI1, 1-9
data bus, 2-3, 2-6default configuration, 1-3DIP switches, 2-10
see also SWdisabling breakpoints in shared memory, 1-16
ADSP-BF561 EZ-KIT Lite Evaluation System Manual I-1
INDEX
EEBIU_SDBCTL register, 1-8, 1-9EBIU_SDGCTL register, 1-8, 1-9EBIU_SDRRC register, 1-8, 1-9evaluation license restrictions, 1-6example programs, 1-12expansion
connectors (J3-1), 2-3interface, 2-3, 2-8, 2-17
External Bus Interface Unit (EBIU), 2-3external memory, 1-6, 2-9EZ-KIT Lite board
architecture, 2-2features, x
Ffeatures, EZ-KIT Lite board, xField pin, 2-4FIO0_FLAG_D register, 1-9flag pins, see programmable flags (PFs)flash
memory, xi, 2-3ports PB39-P32, 2-16ports PB47-P40, 2-16
flash programmer, 1-12
Ggeneral purpose IO, 1-9graphical user interface (GUI), 1-13
HHelp, online, xixHSYNC signal, 2-6, 2-7
Iinput clock, 2-2, 2-6, 2-7IO voltage, 2-2
JJTAG
connector (P4), 2-20emulation port, 2-9
jumper settings, 1-3, 2-10
LLEDs, 1-3, 1-9, 2-14
J7 (power), 2-15LED12-5, 2-5, 2-16LED20-13, 2-5, 2-16LED2-3, 2-15LED4, 1-5, 2-16
Mmemory
external memory map, 1-6select pins, see ~AMS0 &~SMS0writes, 1-16
Nnotation conventions, xxi
O~OE (ADV7183A video decoder) signal, 2-10opcode scan method, 1-16
PP3 (SPORT) connector, 2-3package contents, 1-2Parallel Peripheral Interfaces (PPIs), xii, 1-11,
1-12, 2-6clock select switch (SW5), 2-13see also PPI0 and PPI1
PFs, see programmable flags
I-2 ADSP-BF561 EZ-KIT Lite Evaluation System Manual
INDEX
powerconnector (J7), 2-18specifications, 2-19supply, 2-19
PPI0, 1-9, 1-11, 2-6, 2-8, 2-16Clock, primary processor pin, 2-7primary processor pins 7-0, 2-6SYNC1, primary processor pin, 2-6SYNC2, primary processor pin, 2-7
PPI1, 1-9, 2-6Clock, primary processor pin, 2-7primary processor pins 7-0, 2-6SYNC1 signal, 2-7, 2-11SYNC2 signal, 2-7, 2-11video output, 2-7
primary processor pins (PPIs)PPI0 Clock, 2-7PPI0 SYNC1, 2-6PPI0 SYNC2, 2-7PPI1 Clock, 2-7PPI1 SYNC1, 2-7PPI1 SYNC2, 2-7PPIs bits 7-0, 2-6
processor SDRAM map, see ADSP-BF561 processor
programmable flags (PFs), 2-4, 2-16PF0-1, 1-12, 2-4PF12-PF9, 2-5PF13, 1-11, 2-5PF14, 1-11, 2-5PF15, 1-11, 2-5PF16-19, 2-5PF2, 1-12, 2-4, 2-10PF20-31, 2-5PF3, 2-4PF39-32, 2-5PF4, 1-10, 2-3, 2-4PF47-40, 2-5PF5-8, 1-9, 2-4, 2-12, 2-15see also push buttons
push buttons, 1-9, 2-14connecting to PF pins, 2-15see also SW
Rregistering, this product, 1-3reset
cycle counters, 1-16options, 1-14processor, 2-15push button (SW1), 2-14
RFS0, signal, 2-12RSCLK0
register, 1-10signals, 2-12
SSDRAM, xi, 1-6, 1-7
default settings, 1-8optimum settings, 1-9
SDRAM memory, 1-7core MMRs, 1-7data bank A SRAM, 1-7data bank B SRAM, 1-7instruction SRAM, 1-7instruction SRAM/CACHE, 1-7reserved, 1-7scratch pad SRAM, 1-7system MMRs, 1-7
serialclock (SCL), 1-12data (SDAT), 1-12
Serial Peripheral Interconnect (SPI), 2-3setting target options, 1-14~SMS0, memory select pin, 1-7SPI interface, 2-4SPORT0, xii, 1-10, 2-3, 2-12, 2-20starting EZ-KIT Lite, 1-5SW1, reset push button, 2-14
ADSP-BF561 EZ-KIT Lite Evaluation System Manual I-3
INDEX
SW10-11, test DIP switches, 2-13SW2, video config switch, 1-11, 2-6, 2-7, 2-8,
2-10SW3, boot mode switch, 2-10, 2-11SW4, enable push button, 1-10, 2-12, 2-15SW5, clock select switch, 2-6, 2-13SW6-9, general input push buttons, 2-4, 2-12,
2-15synchronization (SYNC1-2) signals, 2-6system
architecture, EZ-KIT Lite board, 2-2
Ttarget options
miscellaneous, 1-15on emulator exit, 1-14reset, 1-14XML file, 1-15
Target Options dialog box, 1-14test DIP switches (SW10, SW11), 2-13TFS0, signal, 2-12time-division multiplexed (TDM) mode, 1-10Timer 0-6, 2-4Timer 1, 2-4Timer 10, 2-7Timer 11, 2-7Timer 2, 2-4Timer 3, 2-4Timer 4, 2-4Timer 5, 2-4Timer 6, 2-4Timer 8, 2-6Timer 9, 2-7TSCLK0
register, 1-10signal, 2-12
two-wire interface (TWI) mode, 1-10, 2-12
UUART, xi, xii, 2-5, 2-8USB
cable, 1-3connector (P7), 2-19, 2-20interface, 2-9interface chip (U34), 2-14, 2-15monitor LED (LED4), 2-16
user LEDsLED12-5, 2-16LED20-13, 2-16see also LEDs
Vvideo, 1-11
blanking control, 2-7configuration switch (SW2), 2-10connecting to PPI, xiiconnector (J6), 2-18encoder/decoder, xiiinput mode, 2-8interface, 1-11output mode, 2-7
VisualDSP++documentation, xxonline Help, xixsession, 1-7
VSYNC signal, 2-7
XXML
file version, 1-15parser version, 1-15register reset values, 1-16
I-4 ADSP-BF561 EZ-KIT Lite Evaluation System Manual
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