a scalable architecture for multiplier over finite fields gf (2 m )

A Scalable Architecture for Multiplier over Finite Fields GF(2m)

*Kwang-Jin Lee, *Yong-Hee Jang , *Yong-Jin Kwon

Dept. Telecommunication and Information Eng. Hankuk Aviation University

Logic Circuit Lab. Hankuk Aviation Univ.Logic Circuit Lab. Hankuk Aviation Univ.

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Overview Introduction

Importance of multiplication over GF(2m) Problem on current multipliers over GF(2m) Scalable architecture

Multiplication Algorithm over GF(2m) for Scalable Architecture Scalable Architecture for Multiplier over GF(2m)

Structure of PE(Processing Element) Pipeline organization Memory organization

Evaluation and Analysis of the proposed architecture for multiplier Analysis of execution time by hardware configuration Comparison of the execution time

Conclusion

Logic Circuit Lab. Hankuk Aviation Univ.Logic Circuit Lab. Hankuk Aviation Univ.

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Introduction (Continue)

Finite Fields are used in various applications : cryptography, digital signal processing and error

correcting code Importance of multiplication over GF(2m)

Operations over GF(2m) : addition, subtraction, multiplication and

multiplicative inversion Multiplication has the highest time and area

complexities

Logic Circuit Lab. Hankuk Aviation Univ.Logic Circuit Lab. Hankuk Aviation Univ.

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Introduction (Continue)

Problem of current multipliers over GF(2m) Bit by parallel

To reduce time complexity Bit-Serial by parallel

To reduce area complexity Multiplier has to be redesigned when input precision is

increased

Logic Circuit Lab. Hankuk Aviation Univ.Logic Circuit Lab. Hankuk Aviation Univ.

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Introduction

Scalable Architecture The architecture which performs operations regardless

of input precision Originally designed arithmetic unit can be reused or

replicated in order to generate long precision result Without change the data path precision for the

arithmetic unit Easily used for various systems

Logic Circuit Lab. Hankuk Aviation Univ.Logic Circuit Lab. Hankuk Aviation Univ.

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Multiplication Algorithm over GF(2m) for Scalable Architecture

MSB-First multiplication method Bit-Serial by word multiplication method XOR, AND, shift operation without modular operation

Logic Circuit Lab. Hankuk Aviation Univ.Logic Circuit Lab. Hankuk Aviation Univ.

1≤ i≤ m-1

i=0

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Scalable Architecture for Multiplier over GF(2m)

Logic Circuit Lab. Hankuk Aviation Univ.Logic Circuit Lab. Hankuk Aviation Univ.

Consists of PE, FF, Memory, Register-A and Control Block

Every data path has the width of w-bit expect ai

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Structure of PE

Logic Circuit Lab. Hankuk Aviation Univ.Logic Circuit Lab. Hankuk Aviation Univ.

PE is designed to perform repeated function in the algorithm

Consists of AND, XOR, FF, ALIGNMENT, MUX

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Memory Organization

RAM A, B and P perform reading only RAM C performs both reading and writing

Perform both reading and writing on different addresses at a time Eliminate delaying factors

Logic Circuit Lab. Hankuk Aviation Univ.Logic Circuit Lab. Hankuk Aviation Univ.

RAM Area(width · depth)

SPRAMA 1 · mB

w · dPDPRAM C

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Pipeline Organization

Logic Circuit Lab. Hankuk Aviation Univ.Logic Circuit Lab. Hankuk Aviation Univ.

The property of the algorithm is that it performs the same function repeatedly

PE is designed to perform repeated function in this algorithm

The output of PE in step-(j) depends on the output of PE in step-(j+1)

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Simulation Result of The Proposed Architecture

The result of timing simulation Simulation vectors

A(x) = x3 + x2 + x + 1B(x) = x3 + x2 + xP(x) = x4 + x + 1

Logic Circuit Lab. Hankuk Aviation Univ.Logic Circuit Lab. Hankuk Aviation Univ.

C(x) = x2 + 1

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Evaluation and Analysis of the Proposed Architecture for Multiplier (Continue)

Execution timeT = tcycle · period

Clock cyclestcycle = tinit + (tloop · ttotle-PE) + tDPRAM - tR

Logic Circuit Lab. Hankuk Aviation Univ.Logic Circuit Lab. Hankuk Aviation Univ.

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Evaluation and Analysis of the Proposed Architecture for Multiplier (Continue)

Clock period according to word length obtained by analysis of P&R(Post-place &Route)

Logic Circuit Lab. Hankuk Aviation Univ.Logic Circuit Lab. Hankuk Aviation Univ.

Word length Clock period(ns)4 3.3248 3.619

16 3.78632 3.978

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Evaluation and Analysis of the Proposed Architecture for Multiplier (Continue)

Execution time by the number of PEs and word length

Logic Circuit Lab. Hankuk Aviation Univ.Logic Circuit Lab. Hankuk Aviation Univ.

k w=4 w=8 w=16 w=3245 3.825 3.037 2.636 2.43150 3.914 3.138 2.748 2.550

(k, w) = (10, 32), (20, 16), (40, 8)

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Evaluation and Analysis of the Proposed Architecture for Multiplier

Comparison of the execution time between multiplier[4] and proposed multiplier (k=4, w=4)

Logic Circuit Lab. Hankuk Aviation Univ.Logic Circuit Lab. Hankuk Aviation Univ.

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Conclusion We proposed a scalable architecture for multiplier

over GF(2m) which does not need to be redesigned when the precision is increased MSB-First multiplication method Bit-serial by word multiplication method Less execution time compare to the current system in

other paper Easily used for various systems

Logic Circuit Lab. Hankuk Aviation Univ.Logic Circuit Lab. Hankuk Aviation Univ.

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Thank You!

Logic Circuit Lab. Hankuk Aviation Univ.Logic Circuit Lab. Hankuk Aviation Univ.