39. transistor with band pass. comparison calculation, simulation … · 2014. 11. 18. ·...
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39. Single Transistor Amplifier with Low- and High Pass,
Comparison between calculation, Pspice simulation and Experiment
UFO Doctor, March 22th, 2012
1. Introduction
Here we investigate a single transistor band pass preamplifier. The goal is a low-
noise preamplifier for a 40 kHz microphone.
2. Excel calculation according Tietze-Schenk
select original ECXEL sheet Nr. 38 here:
http://ufo-doctor.ch/?select=A_The%20Duck%20Project
For verification of the formulae we use here the example page 24 to 54
Tab.1. EXCEL Sheet
1. Check Circuit
(Note the block capacitors,
minimal 100nF if power
supply or regulator is only
a few Millimeters apart!)
2. Choose Input Data
3. Choose Standard Values
4. Insert Values in Circuit
for:
- Pspice Simulation
- Experiments
5. Simulate with Pspice
6. Verify by experiment
Comments:
- The input impedance will be reduced by CE, re shows the input resistance only.
- Important difference in gain between theory and practice!
- The noise (Noise figure *�Bandwidth) depends mainly on the source resistance Rg
38. Transistor with Band Pass: Calculation, pSpice Simulation and Experiment UFO Doctor, March 2012
Literature : Tietze Schenk, Halbleiter Schaltungstechnik, Ed. 1986,
Description Name Value Units
Supply Voltage Vcc 15 V
Collector Current Ic 0.2 mA
Current Amplification B (hfe) 250
Col/Emitter minimal Voltage UCEmin 1 V
Output Swing max +/- dVC 2 V
Emitter Voltage (> 1V, temp.st.) VE 2 V
Collector working point (<Vcc!) VCA 7 V
Source Resistance Rg 10 kOhm
Load resistor RL 100 kOhm
Lower Cutoff Frequency Flow 20 Hz
Higher Cutoff Frequency Fhigh 20000 Hz
Source Input Voltage ug 10 mV Circuit Fig. 4.28, Page 54
Description Name Value Units Formula Comment Choice
Transistor Q1 low power NPN 2N2222
Temperatur Voltage UT 0.026 V p 24
Inital Input resistance rBE 32.5 kOhm B*UT/Ic p 41
Temp Coef Si Diode dV/E/dT -0.002 V/deg C p 25
Forward Voltage Si-Diode UBE 0.6 V p 37, Si diode
Base Voltage VB 2.6 V VE+UBE
Early Voltage Uy 100 V p 30, 80 to 200V
Diff Output resistance rCE 500 kOhm Uy/Ic p 30
Emitter Resistance RE 10 kOhm VE/Ic p 53, ok for you? RE=10k
Collector Resistor RC 40 kOhm (VCC-VCA)/Ic p 53 , ok for you? RC=39k
Base Current IB 0.0008 mA Ic/B p 53
Current thru div R1/R2 Iq 0.008 mA 10*IB p 53
Base Resistor to Vcc R1 1409 kOhm (Vcc-VB)/(Iq+IB) p 53 R1=1500k
Base Resistor to Gnd R2 325 kOhm VB/iq p 53 R2=330k
Input Resistance re 29 kOhm rBE//R1//R2 p 54
Output Resistance ra 37 kOhm RC//rCE p 54
Amplification idle Aid -285 -Ic/UT*ra p 54
Input reduction factor Irf 0.743 re/(Rg+re) p 54
Output reduction factor Orf 0.730 RL/(RL+ra) p 54
Amplification A -155 Aid*Irf*Orf check it in practise!
High Pass Filter Calculation
Number of LP Filters n 3 for this circuit
Calc lower cutoff freq fgL 12 Hz Flow/Sqroot(n) p 54
Input Capacity CB 3.54E-01 uF 1/(2*Pi*fgL*(Rg+re)) p 54 CB=330nF
Emitter Capacity CE 1.06E+02 uF Ic/(2*Pi*fgL*UT) p 54, ok for you? CE=100uF
Output Capacity Ca 1.01E-01 uF 1/(2*Pi*fgL*(ra+RL)) p 54 Ca=100nF
Low Pass Filter Calculation
Collector Capacity CC 0.000199 uF 1/(2*Pi*fhigh*RC) CC=180pF
Comparsion of the design methods:
Method A flow Hz fhigh Hz Bandwidth and S/N Noise uV/Sqr(Hz) Noise mV
Calculations by Tietze_Schenk -155 20 20000 19980 no yet available
pSpice simulation with Q1 -139 20 19000 18980 2 0.28
Actual experiment with Q1 -82 7 19000 18993 3.6 0.50
Signal/ Noise Ratio in practice S/N 64 dB 20*log(ug*A/noise) measured in practise!
ugua
Rg CB
R1
R2
RC
RE
CC
CE
Ca
RL
Vcc
VC
VE
VB
ue
Q1
Cblock
Gnd
100nF 10uF
2
3. Pspice Simulation of Tietze-Schenk Example
Fig.1. Pspice Simulation
Gain -139, Bandwidth 20Hz to 19kHz, Noise 2uV/���@ 100-10kHz, about 0.5mV
4. Practical Experiment
Fig.3a: Bread Board Test-setup No shielding! Thus we will see a 20mV 50Hz ripple voltage out the output
Fig.3b: Gain -82 at 10kHz, 10mV Input Bandwidth 7Hz to 19kHz Settings: 1V/Div, 50usec/Div Top: Collector Voltage 7.5V, ok Middle: Base Voltage 2.6V, ok Bottom: Emitter Voltage 2.05V, ok
Fig. 3c: Noise investigations Rg connected to Gnd Osci Settings: AC 2mV/Div, 0.1msec/Div Noise about 0.5mV Only small ripples be considered, without 50Hz ripple
Comment: Much less gain than calculated or simulated!
3
5. Band Pass 40 kHz, 100uV Input, 5V Supply, 2mA
5.1. EXCEL Calculations
Tab. 5. EXCEL Sheet for 40kHz Band Pass Amplifier 2mA
5. 40 kHz Band Pass 2mA: Calculation, pSpice Simulation and Experiment UFO Doctor, March 2012
Literature : Tietze Schenk, Halbleiter Schaltungstechnik, Ed. 1986,
Description Name Value Units
Supply Voltage Vcc 5 V
Collector Current Ic 2 mA
Current Amplification B (hfe) 250
Col/Emitter minimal Voltage UCEmin 1 V
Output Swing max +/- dVC 0.5 V
Emitter Voltage (> 1V, temp.st.) VE 1 V
Collector working point (<Vcc!) VCA 3 V
Source Resistance Rg 0.5 kOhm
Load resistor RL 100 kOhm
Lower Cutoff Frequency Flow 1000 Hz
Higher Cutoff Frequency Fhigh 200000 Hz
Source Input Voltage ug 0.1 mV Circuit Fig. 4.28, Page 54
Description Name Value Units Formula Comment Choice
Transistor Q1 low power NPN 2N2222
Temperatur Voltage UT 0.026 V p 24
Inital Input resistance rBE 3.25 kOhm B*UT/Ic p 41
Temp Coef Si Diode dV/E/dT -0.002 V/deg C p 25
Forward Voltage Si-Diode UBE 0.6 V p 37, Si diode
Base Voltage VB 1.6 V VE+UBE
Early Voltage Uy 100 V p 30, 80 to 200V
Diff Output resistance rCE 50 kOhm Uy/Ic p 30
Emitter Resistance RE 0.5 kOhm VE/Ic p 53, ok for you? RE=470E
Collector Resistor RC 1 kOhm (VCC-VCA)/Ic p 53 , ok for you? RC=1k
Base Current IB 0.008 mA Ic/B p 53
Current thru div R1/R2 Iq 0.08 mA 10*IB p 53
Base Resistor to Vcc R1 39 kOhm (Vcc-VB)/(Iq+IB) p 53 R1=39k
Base Resistor to Gnd R2 20 kOhm VB/iq p 53 R2=22k
Input Resistance re 3 kOhm rBE//R1//R2 p 54
Output Resistance ra 1 kOhm RC//rCE p 54
Amplification idle Aid -75 -Ic/UT*ra p 54
Input reduction factor Irf 0.839 re/(Rg+re) p 54
Output reduction factor Orf 0.990 RL/(RL+ra) p 54
Amplification A -63 Aid*Irf*Orf check it in practise!
High Pass Filter Calculation
Number of LP Filters n 3 for this circuit
Calc lower cutoff freq fgL 577 Hz Flow/Sqroot(n) p 54
Input Capacity CB 8.88E-02 uF 1/(2*Pi*fgL*(Rg+re)) p 54 CB=100nF
Emitter Capacity CE 2.12E+01 uF Ic/(2*Pi*fgL*UT) p 54, ok for you? CE=2.2uF
Output Capacity Ca 2.73E-03 uF 1/(2*Pi*fgL*(ra+RL)) p 54 Ca=3.3nF
Low Pass Filter Calculation
Collector Capacity CC 0.000796 uF 1/(2*Pi*fhigh*RC) CC=1nF
Comparsion of the design methods:
Method A flow Hz fhigh Hz Bandwidth and S/N Noise uV/Sqr(Hz) Noise mV
Calculations by Tietze_Schenk -63 1000 200000 199000 no yet available
pSpice simulation with Q1 -48 10000 120000 110000 0.124 0.04
Actual experiment with Q1 -35 3000 114000 111000 0.240 0.08
Signal/ Noise Ratio in practice S/N 33 dB 20*log(ug*A/noise) measured in practise!
ugua
Rg CB
R1
R2
RC
RE
CC
CE
Ca
RL
Vcc
VC
VE
VB
ue
Q1
Cblock
Gnd
100nF 10uF
4
5.2. Pspice Simulation
Fig.5a: Pspice Simulation
Gain -45, Bandwidth 11kHz to 110kHz, Noise 0.116uV/���@ 40kHz, about 0.04mV Comment: The gain presented here is much less than calculated or in reality!
5.3. Practical Experiment
Fig.5b: Gain -40 at 40kHz, 10mV Input Bandwidth 3.0kHz to 125kHz Settings: 0.5V/Div, 20usec/Div Top: Collector Voltage 2.9 V, ok Middle: Base Voltage 1.7V, ok Bottom: Emitter Voltage 1V, ok
Fig.5c: Noise investigations Rg connected to Gnd Settings: AC 0.1mV/Div, 50usec/Div Noise about 0.08mV, close to simulated value of 0.04mV!
Fig.5d: S/N Investigation 100uV Input (47k/470E divider at 10mV Generator) Settings: AC 5mV/Div, 20usec/Div Gain –35, 3 kHz to 114 kHz Very good!
Fig.5e: S/N Investigation 10uV Input (470k/470E divider at 10mV Generator) Settings: AC 0.05mV/Div, 20usec/Div Acceptable!
5
6. Band Pass 40 kHz, 100uV Input, 5V Supply, 1mA
6.1. EXCEL Calculations
Tab. 6. EXCEL Sheet for 40kHz Band Pass Amplifier 1mA
6. 40 kHz Band Pass 1mA: Calculation, pSpice Simulation and Experiment UFO Doctor, March 2012
Literature : Tietze Schenk, Halbleiter Schaltungstechnik, Ed. 1986,
Description Name Value Units
Supply Voltage Vcc 5 V
Collector Current Ic 1 mA
Current Amplification B (hfe) 250
Col/Emitter minimal Voltage UCEmin 1 V
Output Swing max +/- dVC 0.5 V
Emitter Voltage (> 1V, temp.st.) VE 1 V
Collector working point (<Vcc!) VCA 3 V
Source Resistance Rg 0.5 kOhm
Load resistor RL 100 kOhm
Lower Cutoff Frequency Flow 1000 Hz
Higher Cutoff Frequency Fhigh 200000 Hz
Source Input Voltage ug 0.1 mV Circuit Fig. 4.28, Page 54
Description Name Value Units Formula Comment Choice
Transistor Q1 low power NPN 2N2222
Temperatur Voltage UT 0.026 V p 24
Inital Input resistance rBE 6.5 kOhm B*UT/Ic p 41
Temp Coef Si Diode dV/E/dT -0.002 V/deg C p 25
Forward Voltage Si-Diode UBE 0.6 V p 37, Si diode
Base Voltage VB 1.6 V VE+UBE
Early Voltage Uy 100 V p 30, 80 to 200V
Diff Output resistance rCE 100 kOhm Uy/Ic p 30
Emitter Resistance RE 1 kOhm VE/Ic p 53, ok for you? RE=1k
Collector Resistor RC 2 kOhm (VCC-VCA)/Ic p 53 , ok for you? RC=2.2k
Base Current IB 0.004 mA Ic/B p 53
Current thru div R1/R2 Iq 0.04 mA 10*IB p 53
Base Resistor to Vcc R1 77 kOhm (Vcc-VB)/(Iq+IB) p 53 R1=68k
Base Resistor to Gnd R2 40 kOhm VB/iq p 53 R2=33k
Input Resistance re 5 kOhm rBE//R1//R2 p 54
Output Resistance ra 2 kOhm RC//rCE p 54
Amplification idle Aid -75 -Ic/UT*ra p 54
Input reduction factor Irf 0.912 re/(Rg+re) p 54
Output reduction factor Orf 0.981 RL/(RL+ra) p 54
Amplification A -67 Aid*Irf*Orf check it in practise!
High Pass Filter Calculation
Number of LP Filters n 3 for this circuit
Calc lower cutoff freq fgL 577 Hz Flow/Sqroot(n) p 54
Input Capacity CB 4.83E-02 uF 1/(2*Pi*fgL*(Rg+re)) p 54 CB=47nF
Emitter Capacity CE 1.06E+01 uF Ic/(2*Pi*fgL*UT) p 54, ok for you? CE=1uF
Output Capacity Ca 2.71E-03 uF 1/(2*Pi*fgL*(ra+RL)) p 54 Ca=3.3nF
Low Pass Filter Calculation
Collector Capacity CC 0.000398 uF 1/(2*Pi*fhigh*RC) CC=470pF
Comparsion of the design methods:
Method A flow Hz fhigh Hz Bandwidth and S/N Noise uV/Sqr(Hz) Noise mV
Calculations by Tietze_Schenk -67 1000 200000 199000 no yet available
pSpice simulation with Q1 -38 10000 120000 110000 0.124 0.04
Actual experiment with Q1 -25 16000 94000 78000 0.179 0.05
Signal/ Noise Ratio in practice S/N 34 dB 20*log(ug*A/noise) measured in practise!
ugua
Rg CB
R1
R2
RC
RE
CC
CE
Ca
RL
Vcc
VC
VE
VB
ue
Q1
Cblock
Gnd
100nF 10uF
6
6.2. Pspice Simulation
Fig.6a: Pspice Simulation
Gain -38, Bandwidth 10kHz to 120kHz, Noise 0.113uV/���@ 40kHz, about 0.04mV Comment: The gain presented here is much less than calculated or in reality!
6.3. Practical Experiment
Fig.6b: Gain -30 at 40kHz, 10mV Input Bandwidth 16kHz to 94kHz Settings: 0.5V/Div, 20usec/Div Top: Collector Voltage 2.7 V, ok Middle: Base Voltage 1.6V, ok Bottom: Emitter Voltage 0.95V, ok
Fig.6c: Noise investigations Rg connected to Gnd Settings: AC 0.05mV/Div, 50usec/Div Noise about 0.05mV, good match to simulated value of 0.04mV!
Fig.6d: S/N Investigation 100uV Input (47k/470E divider at 10mV Generator) Settings: AC 10mV/Div, 20usec/Div Gain –25, 15 kHz to 90 kHz Very good!
Fig.6e: S/N Investigation 10uV Input (470k/470E divider at 10mV Generator) Settings: AC 1mV/Div, 20usec/Div Acceptable!
7. Conclusion
2mA: Gain = -35, S/N = 33dB;
1mA: Gain = -25, S/N = 34dB, very similar!
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